Update Sys, Adjust HSync / 60 Hz (HFreq)

- Update Sys to include Y/C
- Extended the HSYNC to improve compatibility with CRTs
- Adjusted the 60 Hz option to match a HFreq of 15.734 kHz (closer to NTSC Spec)
- FIxed HPS update through new_vmode to be more reliable

cave/src/Config.scala

@@ -211,7 +211,7 @@ object Config {
   val compatibilityVideoTimingConfig = VideoTimingConfig(
     clockFreq = VIDEO_CLOCK_FREQ,
     clockDiv = VIDEO_CLOCK_DIV,
-    hFreq = 15_625, // Hz
+    hFreq = 15_734, // Hz (Match NTSC SPEC)
     vFreq = 60 // Hz
   )
 

cave/src/VideoSys.scala

@@ -121,7 +121,7 @@ object VideoSys {
     vSize = Config.SCREEN_HEIGHT,
     hFrontPorch = 36,
     vFrontPorch = 12,
-    hRetrace = 20,
+    hRetrace = 28,
     vRetrace = 2
   )
 }

quartus/cave.sv

@@ -61,6 +61,7 @@ module emu (
   output        VGA_F1,
   output [1:0]  VGA_SL,
   output        VGA_SCALER, // Force VGA scaler
+  output        VGA_DISABLE,
 
   input  [11:0] HDMI_WIDTH,
   input  [11:0] HDMI_HEIGHT,
@@ -388,6 +389,15 @@ video_mixer #(.LINE_LENGTH(320), .HALF_DEPTH(0), .GAMMA(1)) video_mixer (
   .VGA_DE(VGA_DE)
 );
 
+// Update HPS when video mode changes
+reg [1:0] video_status;
+always @(posedge clk_sys) begin
+    if (video_status != status[8]) begin
+        video_status <= status[8];
+        new_vmode <= ~new_vmode;
+    end
+end
+
 ////////////////////////////////////////////////////////////////////////////////
 // CONTROLS
 ////////////////////////////////////////////////////////////////////////////////
@@ -524,7 +534,7 @@ Cave cave (
   .player_1_pause(player_2_pause),
   // Video signals
   .video_clockEnable(ce_pix),
-  .video_changeMode(new_vmode),
+  .video_changeMode(0),
   .video_hSync(hsync),
   .video_vSync(vsync),
   .video_hBlank(hblank),

quartus/sys/hps_io.sv

@@ -891,22 +891,28 @@ always @(posedge clk_sys) begin
 	  11: dout <= vid_pix[31:16];
 	  12: dout <= vid_vtime_hdmi[15:0];
 	  13: dout <= vid_vtime_hdmi[31:16];
+	  14: dout <= vid_ccnt[15:0];
+	  15: dout <= vid_ccnt[31:16];
 	  default dout <= 0;
 	endcase
 end
 
 reg [31:0] vid_hcnt = 0;
 reg [31:0] vid_vcnt = 0;
+reg [31:0] vid_ccnt = 0;
 reg  [7:0] vid_nres = 0;
 reg  [1:0] vid_int  = 0;
 
 always @(posedge clk_vid) begin
 	integer hcnt;
 	integer vcnt;
+	integer ccnt;
 	reg old_vs= 0, old_de = 0, old_vmode = 0;
 	reg [3:0] resto = 0;
 	reg calch = 0;
 
+	if(calch & de) ccnt <= ccnt + 1;
+
 	if(ce_pix) begin
 		old_vs <= vs;
 		old_de <= de;
@@ -927,9 +933,11 @@ always @(posedge clk_vid) begin
 					if(&resto) vid_nres <= vid_nres + 1'd1;
 					vid_hcnt <= hcnt;
 					vid_vcnt <= vcnt;
+					vid_ccnt <= ccnt;
 				end
 				vcnt <= 0;
 				hcnt <= 0;
+				ccnt <= 0;
 				calch <= 1;
 			end
 		end

quartus/sys/ltc2308.sv

@@ -102,19 +102,19 @@ end
 
 endmodule
 
-module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000)
+module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000, NUM_CH = 1)
 (
-	input        reset,
-	input        clk,
-
-	inout  [3:0] ADC_BUS,
-	output reg   dout,
-	output       active
+	input         reset,
+	input         clk,
+
+	inout  [3:0]  ADC_BUS,
+	output reg    dout,
+	output        active,
+	output        adc_sync,
+	output [(NUM_CH*12)-1:0] adc_data
 );
 
-wire [11:0] adc_data;
-wire        adc_sync;
-ltc2308 #(1, ADC_RATE, CLK_RATE) adc
+ltc2308 #(NUM_CH, ADC_RATE, CLK_RATE) adc
 (
 	.reset(reset),
 	.clk(clk),
@@ -133,8 +133,8 @@ always @(posedge clk) begin
 		data1 <= data2;
 		data2 <= data3;
 		data3 <= data4;
-		data4 <= adc_data;
-		
+		data4 <= adc_data[11:0];
+
 		sum <= data1+data2+data3+data4;
 
 		if(sum[13:2]<HIST_LOW)  dout <= 0;
@@ -148,7 +148,7 @@ reg [1:0] act;
 always @(posedge clk) begin
 	reg [31:0] onesec;
 	reg old_dout;
-	
+
 	onesec <= onesec + 1;
 	if(onesec>CLK_RATE) begin
 		onesec <= 0;

quartus/sys/sys.qip

@@ -16,6 +16,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) v
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) arcade_video.v ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) osd.v ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) yc_out.sv ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2c.v ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2s.v ]