ЛР2. Исправление подключения модуля в nexys_alu

MPSU · Sep 9, 2024 · ffec97f · ffec97f
1 parent 8396bb5
commit ffec97f
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv b/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv
@@ -45,7 +45,7 @@ module nexys_alu(
   logic [31:0]              result;
   logic                     flag;
 
-  alu_riscv alu_riscv (
+  alu alu_riscv (
     .alu_op_i (operator),
     .a_i      (operand_a),
     .b_i      (operand_b),