ЛР7. Исправление адресации в ext_mem

MPSU · Apr 23, 2024 · fedc917 · fedc917
1 parent bcaea16
commit fedc917
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/Labs/Made-up modules/lab_07.ext_mem.sv b/Labs/Made-up modules/lab_07.ext_mem.sv
@@ -34,7 +34,7 @@ assign ready_o = 1'b1;
 logic [31:0] RAM [2**12];
 
 logic [31:0] addr;
-assign addr = addr_i >> 2;
+assign addr = addr_i;
 
 always_ff@(posedge clk_i) begin
   case(1)