ЛР10. Исправление разрядности в готовом модуле

MPSU · Apr 30, 2024 · e9387cc · e9387cc
1 parent 2b2d199
commit e9387cc
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/Labs/Made-up modules/lab_10.csr.sv b/Labs/Made-up modules/lab_10.csr.sv
@@ -30,7 +30,7 @@ module csr_controller (
 );
 
   logic [31:0] VeD, vXRXX, Tzi1KCKE, gfnK, gaSybr;
-  logic mcause, mscratch;
+  logic [31:0] mcause, mscratch;
   logic asdfga;
   logic [31:0] fadfda;
   assign mscratch = Tzi1KCKE;