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Merge branch 'master' of github.com:MPSU/APS
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@HepoH3
HepoH3 committed Sep 12, 2024
2 parents 4c7cbb8 + 7735685 commit 4169b66
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Showing 18 changed files with 338 additions and 353 deletions.
49 changes: 26 additions & 23 deletions Labs/01. Adder/lab_01.tb_fulladder.sv
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Expand Up @@ -11,33 +11,36 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.

module lab_01_tb_fulladder();

logic tb_a_i;
logic tb_b_i;
logic tb_carry_i;
logic tb_carry_o;
logic tb_sum_o;
logic [2:0] test_case;
logic tb_a_i;
logic tb_b_i;
logic tb_carry_i;
logic tb_carry_o;
logic tb_sum_o;
logic [2:0] test_case;

fulladder DUT (
.a_i(tb_a_i),
.b_i(tb_b_i),
.sum_o(tb_sum_o),
.carry_i(tb_carry_i),
.carry_o(tb_carry_o)
);
fulladder DUT (
.a_i(tb_a_i),
.b_i(tb_b_i),
.sum_o(tb_sum_o),
.carry_i(tb_carry_i),
.carry_o(tb_carry_o)
);

assign {tb_a_i, tb_b_i, tb_carry_i} = test_case;
assign {tb_a_i, tb_b_i, tb_carry_i} = test_case;

initial begin
$display("\nTest has been started\n");
initial begin
$display("\nTest has been started\n");
#5ns;
test_case = 3'd0;
repeat(8) begin
#5ns;
test_case = 3'd0;
repeat(8) begin
#5ns;
test_case++;
end
$display("\nTest has been finished. Check results at waveform window.\n");
$finish();
test_case++;
end
$display("\nTest has been finished. Check results at waveform window.\n");
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end

endmodule
119 changes: 61 additions & 58 deletions Labs/01. Adder/lab_01.tb_fulladder32.sv
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Expand Up @@ -11,72 +11,75 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.

module lab_01_tb_fulladder32();

logic [31:0] tb_a_i;
logic [31:0] tb_b_i;
logic tb_carry_i;
logic tb_carry_o;
logic [31:0] tb_sum_o;
logic [31:0] tb_a_i;
logic [31:0] tb_b_i;
logic tb_carry_i;
logic tb_carry_o;
logic [31:0] tb_sum_o;

logic clk = 0;
always #5ns clk = ~clk;
logic clk = 0;
always #5ns clk = ~clk;

int err_cnt = 0;
int err_cnt = 0;

fulladder32 DUT (
.a_i(tb_a_i),
.b_i(tb_b_i),
.sum_o(tb_sum_o),
.carry_i(tb_carry_i),
.carry_o(tb_carry_o)
);
fulladder32 DUT (
.a_i(tb_a_i),
.b_i(tb_b_i),
.sum_o(tb_sum_o),
.carry_i(tb_carry_i),
.carry_o(tb_carry_o)
);

initial begin
$display("Test has been started");
sequential_add_test();
random_test();
$display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
$finish();
end

task sequential_add_test();
@(posedge clk);
tb_a_i = 0;
tb_b_i = 0;
tb_carry_i = 0;
@(posedge clk);
for(int i = 0; i < 16; i++) begin
tb_a_i += 256;
for(int j = 0; j < 16; j++) begin
tb_b_i += 256;
tb_carry_i = ~tb_carry_i;
@(posedge clk);
end
end
endtask
initial begin
$display("Test has been started");
sequential_add_test();
random_test();
$display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end

task random_test();
repeat(1e4) begin
tb_a_i = $urandom();
tb_b_i = $urandom();
tb_carry_i = $urandom_range(1);
task sequential_add_test();
@(posedge clk);
tb_a_i = 0;
tb_b_i = 0;
tb_carry_i = 0;
@(posedge clk);
for(int i = 0; i < 16; i++) begin
tb_a_i += 256;
for(int j = 0; j < 16; j++) begin
tb_b_i += 256;
tb_carry_i = ~tb_carry_i;
@(posedge clk);
end
endtask
end
endtask

logic [32:0] reference;
assign reference = {1'b0, tb_a_i} + {1'b0, tb_b_i} + tb_carry_i;
task random_test();
repeat(1e4) begin
tb_a_i = $urandom();
tb_b_i = $urandom();
tb_carry_i = $urandom_range(1);
@(posedge clk);
end
endtask

sum_check: assert property (
@(negedge clk)
reference === {tb_carry_o, tb_sum_o}
)
else begin
err_cnt++;
$error("\noperands : a_i = 0x%08h, b_i = 0x%08h, carry_i = %b\nyour res : sum = 0x%08h, carry_o = %b\nreference: sum = 0x%08h, carry_o = %b",
tb_a_i, tb_b_i, tb_carry_i, tb_sum_o, tb_carry_o, reference[31:0], reference [32]);
if(err_cnt == 10) begin
$display("\nTest has been stopped after 10 errors");
$stop();
end
logic [32:0] reference;
assign reference = {1'b0, tb_a_i} + {1'b0, tb_b_i} + tb_carry_i;

sum_check: assert property (
@(negedge clk)
reference === {tb_carry_o, tb_sum_o}
)
else begin
err_cnt++;
$error("\noperands : a_i = 0x%08h, b_i = 0x%08h, carry_i = %b\nyour res : sum = 0x%08h, carry_o = %b\nreference: sum = 0x%08h, carry_o = %b",
tb_a_i, tb_b_i, tb_carry_i, tb_sum_o, tb_carry_o, reference[31:0], reference [32]);
if(err_cnt == 10) begin
$display("\nTest has been stopped after 10 errors");
$stop();
end
end
endmodule
49 changes: 26 additions & 23 deletions Labs/01. Adder/lab_01.tb_fulladder4.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -11,33 +11,36 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.

module lab_01_tb_fulladder4();

logic [3:0] tb_a_i;
logic [3:0] tb_b_i;
logic tb_carry_i;
logic tb_carry_o;
logic [3:0] tb_sum_o;
logic [8:0] test_case;
logic [3:0] tb_a_i;
logic [3:0] tb_b_i;
logic tb_carry_i;
logic tb_carry_o;
logic [3:0] tb_sum_o;
logic [8:0] test_case;

fulladder4 DUT (
.a_i(tb_a_i),
.b_i(tb_b_i),
.sum_o(tb_sum_o),
.carry_i(tb_carry_i),
.carry_o(tb_carry_o)
);
fulladder4 DUT (
.a_i(tb_a_i),
.b_i(tb_b_i),
.sum_o(tb_sum_o),
.carry_i(tb_carry_i),
.carry_o(tb_carry_o)
);

assign {tb_a_i, tb_b_i, tb_carry_i} = test_case;
assign {tb_a_i, tb_b_i, tb_carry_i} = test_case;

initial begin
$display("Test has been started");
initial begin
$display("Test has been started");
#5ns;
test_case = 9'd0;
repeat(512) begin
#5ns;
test_case = 9'd0;
repeat(512) begin
#5ns;
test_case++;
end
$display("\nTest has been finished Check results at waveform window.\n");
$finish();
test_case++;
end
$display("\nTest has been finished Check results at waveform window.\n");
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end

endmodule
2 changes: 1 addition & 1 deletion Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv
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Expand Up @@ -45,7 +45,7 @@ module nexys_alu(
logic [31:0] result;
logic flag;

alu_riscv alu_riscv (
alu alu_riscv (
.alu_op_i (operator),
.a_i (operand_a),
.b_i (operand_b),
Expand Down
28 changes: 15 additions & 13 deletions Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,9 @@ initial
direct_test();
$display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
$finish();
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.");
$fatal();
end

task X_test();
Expand Down Expand Up @@ -247,23 +250,22 @@ end

endmodule

parameter ALUOP_W = 5;
parameter OP_W = 32;
parameter SHIFT_W = $clog2(OP_W);
parameter STAGE_LEN = OP_W+1;
parameter HASH_LEN = 1000;
parameter START_CODING = 10366;
parameter START_MUX = START_CODING+100;

module alu_ref (
input logic [ALUOP_W-1:0] alu_op_i,
input logic [OP_W-1:0] a_i,
input logic [OP_W-1:0] b_i,
output logic [OP_W-1:0] result_o,
output logic flag_o
input logic [ 4:0] alu_op_i,
input logic [31:0] a_i,
input logic [31:0] b_i,
output logic [31:0] result_o,
output logic flag_o
);


localparam ALUOP_W = 5;
localparam OP_W = 32;
localparam SHIFT_W = $clog2(OP_W);
localparam STAGE_LEN = OP_W+1;
localparam HASH_LEN = 1000;
localparam START_CODING = 10366;
localparam START_MUX = START_CODING+100;

genvar i, j, k;

Expand Down
2 changes: 1 addition & 1 deletion Labs/03. Register file and memory/board files/nexys_rf_riscv.sv
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Expand Up @@ -34,7 +34,7 @@ module nexys_rf_riscv(
logic [7:0][3:0] rd1;
logic [7:0][3:0] rd2;

rf_riscv rf_riscv (
register_file rf_riscv (
.clk_i (clk_i),
.read_addr1_i (ra1 ),
.read_addr2_i (ra2 ),
Expand Down
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