ЛР3. Исправление адресов в nexys_rf_riscv

MPSU · Nov 24, 2023 · 149b500 · 149b500
1 parent 80107e1
commit 149b500
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv
@@ -30,9 +30,9 @@ reg [31:0] rd2;
 rf_riscv DUT
 (
   .clk_i            (CLK100 ),
-  .write_addr_i     (a1     ),
-  .read_addr1_i     (a2     ),
-  .read_addr2_i     (a3     ),
+  .read_addr1_i     (a1     ),
+  .read_addr2_i     (a2     ),
+  .write_addr_i     (a3     ),
   .write_data_i     (WD3    ),
   .write_enable_i   (WE     ),
   .read_data1_o     (RD1    ),