GitHub - LazuriteCoder/RISC-V-CPU-pipeline: Verilog实现的简单五级RISC-V流水线CPU

LazuriteCoder / RISC-V-CPU-pipeline Public

Verilog实现的简单五级RISC-V流水线CPU

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
ALU.v		ALU.v
ALU_decoder.v		ALU_decoder.v
CU.v		CU.v
EX.v		EX.v
EX_MEM.v		EX_MEM.v
ID.v		ID.v
ID_EX.v		ID_EX.v
IF.v		IF.v
IF_ID.v		IF_ID.v
MEM.v		MEM.v
MEM_WB.v		MEM_WB.v
NPC.v		NPC.v
PC.v		PC.v
README.md		README.md
SEXT.v		SEXT.v
WB.v		WB.v
barrelshifter.v		barrelshifter.v
forwardng_unit.v		forwardng_unit.v
hazard_detection_unit.v		hazard_detection_unit.v
regfile.v		regfile.v
static_branch.v		static_branch.v
top.v		top.v