Verilog_Coding_Practice

First Verilog Phrase using three different modeling styles

Above three modeling styles are used to design

Name		Name	Last commit message	Last commit date
Latest commit History 67 Commits
Miscellaneous		Miscellaneous
Samir palnitkar Book		Samir palnitkar Book
README.md		README.md
behavioral_comparator.v		behavioral_comparator.v
behavioral_mux.v		behavioral_mux.v
dataflow_comparator.v		dataflow_comparator.v
dataflow_mux.v		dataflow_mux.v
full_adder.v		full_adder.v
full_adder_tb.v		full_adder_tb.v
module_d.v		module_d.v
module_d_tb.v		module_d_tb.v
mux.v		mux.v
mux_tb.v		mux_tb.v
nand.v		nand.v
nand_tb.v		nand_tb.v
parameter_mux.v		parameter_mux.v
s_r_latch.v		s_r_latch.v
s_r_latch_tb.v		s_r_latch_tb.v
structural_comparator.v		structural_comparator.v
structural_mux.v		structural_mux.v

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