-
https://github.com/Cadence
- Noida
-
13:30
(UTC -12:00) - in/khalique13
- @abd_al_khalique
- _abdul_khalique_
- khalique13
Pinned Loading
-
dvsd_pe_sky130
dvsd_pe_sky130 PublicThis project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral RTL of an 8-bit Priority Encoder, using SkyWater 130 nm PDK.
-
caravel_vsd_priority_encoder
caravel_vsd_priority_encoder PublicForked from efabless/caravel_user_project
https://caravel-user-project.readthedocs.io
Verilog 1
-
skywater-pdk
skywater-pdk PublicForked from google/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Python
-
vsdflow
vsdflow PublicForked from kunalg123/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using…
Verilog 2
-
PLL_OSU180_Workshop
PLL_OSU180_Workshop PublicOn-Chip Clock Multiplier (PLL) on OSU180 Workshop
SourcePawn
If the problem persists, check the GitHub status page or contact support.