GitHub - JanithGan/UART: Verilog Code for UART (FPGA Project)

JanithGan / UART Public

Verilog Code for UART (FPGA Project)

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
db		db
incremental_db		incremental_db
output_files		output_files
UART.qpf		UART.qpf
UART.qsf		UART.qsf
UART.qws		UART.qws
UART_baudrate_gen.v		UART_baudrate_gen.v
UART_baudrate_gen.v.bak		UART_baudrate_gen.v.bak
UART_rx.v		UART_rx.v
UART_rx.v.bak		UART_rx.v.bak
UART_tx.v		UART_tx.v
UART_tx.v.bak		UART_tx.v.bak
cr_ie_info.json		cr_ie_info.json
router.v		router.v
router.v.bak		router.v.bak