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1. Handwritten-Queue-Library-with-its-own-Iterator-and-Allocator-like-STL-Queue Handwritten-Queue-Library-with-its-own-Iterator-and-Allocator-like-STL-Queue Public

   This is a handwritten queue library with its own iterator and allocator that just like STL Queue in C++

   C++ 6

2. A-C-language-subset-compiler-with-RISC-V-backend-design A-C-language-subset-compiler-with-RISC-V-backend-design Public

   此项目为第四届“华为毕昇杯”全国大学生计算机系统能力培养大赛团队赛参赛作品。我们在其中做了部分较为创新的尝试，比如添加前端优化，添加GVN for Array优化等等

   C++ 3

3. 7-stage-sequential-four-issue-superscalar-MIPS-processor-design 7-stage-sequential-four-issue-superscalar-MIPS-processor-design Public

   7-stage sequential four-issue superscalar MIPS processor design

   SystemVerilog 2

4. 4-way-set-associative-cache-with-tree-based-pseudo-LRU 4-way-set-associative-cache-with-tree-based-pseudo-LRU Public

   4-way set-associative cache with tree-based pseudo LRU design

   1

5. 7-stage-sequential-dual-issue-superscalar-MIPS-processor-design 7-stage-sequential-dual-issue-superscalar-MIPS-processor-design Public

   7-stage sequential dual-issue superscalar MIPS processor design

   1

6. 4.-4-way-set-associative-cache-with-tree-based-pseudo-LRU-design 4.-4-way-set-associative-cache-with-tree-based-pseudo-LRU-design Public

   此缓存总容量为32KB，Write Back, 替换策略为tree-based pseudo LRU，缓存内部两级流水。地址解码和选择将会被替换的缓存行由第一级流水线实现，访存操作在第二级流水线实现（多周期访存）。在FPGA上工作频率能接近170MHz。

   SystemVerilog 1