Various IPs implemented in Verilog
- stack.v - A circular stack
- deserializer.sv - A formally verified, parameterizable deserializer.
- deserializer_rst.sv - With a reset signal.
- serializer.sv - A formally verified, parameterizable serializer.
- serializer_rst.sv - With a reset signal.
The deserializer, deserializer_rst, serializer, and serializer_rst IPs come with formal specifications. You need to install SymbiYosys
first. To check a specific IP, run make <IP name> or if you want to check all of them, run make formal.
The stack implementation has only been partially formally verified, and is being worked on.
verilog_ips is free and open hardware and is licensed under the ISC licence.