Ensuring the safety of an electronic device during its execution is a very important issue, especially in cases where the design and manufacture are carried out by different companies.The aim of the project is to instantiate hardware architectures that differ both ins tructure and in computational capacity in order to test the impact of the AES algorithm on system performance and how performance varies with cryptographic and system characteristics variation.
The development of the project into 3 well defined parts:
- Creation of hardware architectures
- Implementation of a test bench based on an AES algorithm
- Testing and Analysis of Results
In the first phase I used the gem5 hardware simulation tool with which I decided to create 3 very different systems with different performances. After I searched the net for a library that implemented the AES cryptographic functions, and then I implemented a C program to be used as a test bench. In the final part of the project I decided which simulations to perform and analyze the data for final report and conclusion.
📚 A final report (and presentation) is available in which all the phases of the project are described in detail linked with the analysis of the result