i#7050: reset expected read/write record counts after kernel transfer #7051
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…ansfer. When an instruction is preempted by a kernel transfer, the instruction is not retired. The trace might not have captured all the read and write records. To avoid false positive, the invariant checker should reset the expected read and write record counters. Fixes #7050
| { gen_marker(TID_A, TRACE_MARKER_TYPE_CACHE_LINE_SIZE, 64), nullptr }, | ||
| { gen_marker(TID_A, TRACE_MARKER_TYPE_PAGE_SIZE, 4096), nullptr }, | ||
| { gen_instr(TID_A), store }, | ||
| { gen_marker(TID_A, TRACE_MARKER_TYPE_KERNEL_EVENT, 2), nop }, |
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I think raw2trace needs to remove the store instruction in this case. For an asynchronous signal we should not have a partially complete instruction with an instruction record but no address record (for a synchronous signal it's less clear what should be done: there is an issue on it somewhere): that will just be confusing and violate our invariants without benefit as it's the same as the signal arriving completely before the store. The store will be executed as the resumption point of the signal.
raw2trace has logic trying to place the signal properly: I think there must be a bug in that logic or it fails to consider this case?
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I have a new pull request #7058 which removed preempted instructions and memrefs from the trace in raw2trace. The new PR does not change the invariant checker and take a different path to address the issue by changing the behavior of raw2trace.
When an instruction is preempted by a kernel transfer, the instruction is not retired. The trace might not have captured all the read and write records. To avoid false positive, the invariant checker should reset the expected read and write record counters.
Fixes #7050