i#6662 regdeps ISA: virtual registers

api/docs/release.dox

@@ -226,7 +226,10 @@ Further non-compatibility-affecting changes include:
    purpose of preserving register dependencies.
  - Added instr_convert_to_isa_regdeps() API that converts an #instr_t from a real ISA
    (e.g., #DR_ISA_AMD64) to the #DR_ISA_REGDEPS synthetic ISA.
-
+ - Added reg_to_virtual() which takes a regular DR_REG_ register and returns a DR_REG_V
+   virtual register for #DR_ISA_REGDEPS.
+ - Added get_virtual_register_name() which takes a virtual DR_REG_V register (used by
+   #DR_ISA_REGDEPS) and returns its string name (as const char *).
 
 **************************************************
 <hr>

core/CMakeLists.txt

@@ -279,6 +279,7 @@ set(DECODER_SRCS
   ir/${ARCH_NAME}/decode.c
   ir/encode_shared.c
   ir/${ARCH_NAME}/encode.c
+  ir/isa_regdeps/encoding_common.c
   ir/isa_regdeps/encode.c
   ir/isa_regdeps/decode.c
   ir/disassemble_shared.c

core/ir/aarch64/encode.c

@@ -32,6 +32,7 @@
  */
 
 #include "../globals.h"
+#include "../isa_regdeps/encoding_common.h"
 #include "arch.h"
 #include "instr.h"
 #include "decode.h"
@@ -198,6 +199,80 @@ const reg_id_t dr_reg_fixer[] = { REG_NULL,
 };
 /* clang-format on */
 
+/* Maps containing-registers to their DR_ISA_REGDEPS virtual-register.
+ * Same size as dr_reg_fixer[], keep them synched.
+ * Note: DR_REG_INVALID (== DR_REG_V1 == 1) has been excluded to avoid failures on opnd_t
+ * operations.
+ */
+const reg_id_t dr_reg_virtual[] = {
+    DR_REG_V0,   DR_REG_V0,   DR_REG_V2,   DR_REG_V3,   DR_REG_V4,   DR_REG_V5,
+    DR_REG_V6,   DR_REG_V7,   DR_REG_V8,   DR_REG_V9,   DR_REG_V10,  DR_REG_V11,
+    DR_REG_V12,  DR_REG_V13,  DR_REG_V14,  DR_REG_V15,  DR_REG_V16,  DR_REG_V17,
+    DR_REG_V18,  DR_REG_V19,  DR_REG_V20,  DR_REG_V21,  DR_REG_V22,  DR_REG_V23,
+    DR_REG_V24,  DR_REG_V25,  DR_REG_V26,  DR_REG_V27,  DR_REG_V28,  DR_REG_V29,
+    DR_REG_V30,  DR_REG_V31,  DR_REG_V32,  DR_REG_V33,  DR_REG_V34,  DR_REG_V2,
+    DR_REG_V3,   DR_REG_V4,   DR_REG_V5,   DR_REG_V6,   DR_REG_V7,   DR_REG_V8,
+    DR_REG_V9,   DR_REG_V10,  DR_REG_V11,  DR_REG_V12,  DR_REG_V13,  DR_REG_V14,
+    DR_REG_V15,  DR_REG_V16,  DR_REG_V17,  DR_REG_V18,  DR_REG_V19,  DR_REG_V20,
+    DR_REG_V21,  DR_REG_V22,  DR_REG_V23,  DR_REG_V24,  DR_REG_V25,  DR_REG_V26,
+    DR_REG_V27,  DR_REG_V28,  DR_REG_V29,  DR_REG_V30,  DR_REG_V31,  DR_REG_V32,
+    DR_REG_V33,  DR_REG_V34,  DR_REG_V35,  DR_REG_V36,  DR_REG_V37,  DR_REG_V38,
+    DR_REG_V39,  DR_REG_V40,  DR_REG_V41,  DR_REG_V42,  DR_REG_V43,  DR_REG_V44,
+    DR_REG_V45,  DR_REG_V46,  DR_REG_V47,  DR_REG_V48,  DR_REG_V49,  DR_REG_V50,
+    DR_REG_V51,  DR_REG_V52,  DR_REG_V53,  DR_REG_V54,  DR_REG_V55,  DR_REG_V56,
+    DR_REG_V57,  DR_REG_V58,  DR_REG_V59,  DR_REG_V60,  DR_REG_V61,  DR_REG_V62,
+    DR_REG_V63,  DR_REG_V64,  DR_REG_V65,  DR_REG_V66,  DR_REG_V35,  DR_REG_V36,
+    DR_REG_V37,  DR_REG_V38,  DR_REG_V39,  DR_REG_V40,  DR_REG_V41,  DR_REG_V42,
+    DR_REG_V43,  DR_REG_V44,  DR_REG_V45,  DR_REG_V46,  DR_REG_V47,  DR_REG_V48,
+    DR_REG_V49,  DR_REG_V50,  DR_REG_V51,  DR_REG_V52,  DR_REG_V53,  DR_REG_V54,
+    DR_REG_V55,  DR_REG_V56,  DR_REG_V57,  DR_REG_V58,  DR_REG_V59,  DR_REG_V60,
+    DR_REG_V61,  DR_REG_V62,  DR_REG_V63,  DR_REG_V64,  DR_REG_V65,  DR_REG_V66,
+    DR_REG_V35,  DR_REG_V36,  DR_REG_V37,  DR_REG_V38,  DR_REG_V39,  DR_REG_V40,
+    DR_REG_V41,  DR_REG_V42,  DR_REG_V43,  DR_REG_V44,  DR_REG_V45,  DR_REG_V46,
+    DR_REG_V47,  DR_REG_V48,  DR_REG_V49,  DR_REG_V50,  DR_REG_V51,  DR_REG_V52,
+    DR_REG_V53,  DR_REG_V54,  DR_REG_V55,  DR_REG_V56,  DR_REG_V57,  DR_REG_V58,
+    DR_REG_V59,  DR_REG_V60,  DR_REG_V61,  DR_REG_V62,  DR_REG_V63,  DR_REG_V64,
+    DR_REG_V65,  DR_REG_V66,  DR_REG_V35,  DR_REG_V36,  DR_REG_V37,  DR_REG_V38,
+    DR_REG_V39,  DR_REG_V40,  DR_REG_V41,  DR_REG_V42,  DR_REG_V43,  DR_REG_V44,
+    DR_REG_V45,  DR_REG_V46,  DR_REG_V47,  DR_REG_V48,  DR_REG_V49,  DR_REG_V50,
+    DR_REG_V51,  DR_REG_V52,  DR_REG_V53,  DR_REG_V54,  DR_REG_V55,  DR_REG_V56,
+    DR_REG_V57,  DR_REG_V58,  DR_REG_V59,  DR_REG_V60,  DR_REG_V61,  DR_REG_V62,
+    DR_REG_V63,  DR_REG_V64,  DR_REG_V65,  DR_REG_V66,  DR_REG_V35,  DR_REG_V36,
+    DR_REG_V37,  DR_REG_V38,  DR_REG_V39,  DR_REG_V40,  DR_REG_V41,  DR_REG_V42,
+    DR_REG_V43,  DR_REG_V44,  DR_REG_V45,  DR_REG_V46,  DR_REG_V47,  DR_REG_V48,
+    DR_REG_V49,  DR_REG_V50,  DR_REG_V51,  DR_REG_V52,  DR_REG_V53,  DR_REG_V54,
+    DR_REG_V55,  DR_REG_V56,  DR_REG_V57,  DR_REG_V58,  DR_REG_V59,  DR_REG_V60,
+    DR_REG_V61,  DR_REG_V62,  DR_REG_V63,  DR_REG_V64,  DR_REG_V65,  DR_REG_V66,
+    DR_REG_V35,  DR_REG_V36,  DR_REG_V37,  DR_REG_V38,  DR_REG_V39,  DR_REG_V40,
+    DR_REG_V41,  DR_REG_V42,  DR_REG_V43,  DR_REG_V44,  DR_REG_V45,  DR_REG_V46,
+    DR_REG_V47,  DR_REG_V48,  DR_REG_V49,  DR_REG_V50,  DR_REG_V51,  DR_REG_V52,
+    DR_REG_V53,  DR_REG_V54,  DR_REG_V55,  DR_REG_V56,  DR_REG_V57,  DR_REG_V58,
+    DR_REG_V59,  DR_REG_V60,  DR_REG_V61,  DR_REG_V62,  DR_REG_V63,  DR_REG_V64,
+    DR_REG_V65,  DR_REG_V66,  DR_REG_V67,  DR_REG_V68,  DR_REG_V69,  DR_REG_V70,
+    DR_REG_V71,  DR_REG_V72,  DR_REG_V73,  DR_REG_V74,  DR_REG_V75,  DR_REG_V76,
+    DR_REG_V77,  DR_REG_V78,  DR_REG_V79,  DR_REG_V80,  DR_REG_V81,  DR_REG_V82,
+    DR_REG_V83,  DR_REG_V84,  DR_REG_V85,  DR_REG_V86,  DR_REG_V87,  DR_REG_V88,
+    DR_REG_V89,  DR_REG_V90,  DR_REG_V91,  DR_REG_V92,  DR_REG_V93,  DR_REG_V94,
+    DR_REG_V95,  DR_REG_V96,  DR_REG_V97,  DR_REG_V98,  DR_REG_V99,  DR_REG_V100,
+    DR_REG_V101, DR_REG_V102, DR_REG_V103, DR_REG_V104, DR_REG_V105, DR_REG_V106,
+    DR_REG_V107, DR_REG_V108, DR_REG_V109, DR_REG_V110, DR_REG_V111, DR_REG_V112,
+    DR_REG_V113, DR_REG_V114, DR_REG_V115, DR_REG_V116, DR_REG_V117, DR_REG_V118,
+    DR_REG_V119, DR_REG_V120, DR_REG_V121, DR_REG_V122, DR_REG_V123, DR_REG_V124,
+    DR_REG_V125, DR_REG_V126, DR_REG_V127, DR_REG_V128, DR_REG_V129, DR_REG_V130,
+    DR_REG_V131, DR_REG_V132, DR_REG_V133, DR_REG_V134, DR_REG_V135, DR_REG_V136,
+    DR_REG_V137, DR_REG_V138, DR_REG_V139, DR_REG_V140, DR_REG_V141, DR_REG_V142,
+    DR_REG_V143, DR_REG_V144, DR_REG_V145, DR_REG_V146, DR_REG_V147, DR_REG_V148,
+    DR_REG_V149, DR_REG_V150, DR_REG_V151, DR_REG_V152, DR_REG_V153, DR_REG_V154,
+    DR_REG_V155, DR_REG_V156, DR_REG_V157, DR_REG_V158, DR_REG_V159, DR_REG_V160,
+    DR_REG_V161, DR_REG_V162, DR_REG_V163, DR_REG_V164, DR_REG_V165, DR_REG_V166,
+    DR_REG_V167, DR_REG_V168, DR_REG_V169, DR_REG_V170, DR_REG_V171, DR_REG_V172,
+    DR_REG_V173, DR_REG_V174, DR_REG_V175, DR_REG_V176, DR_REG_V177, DR_REG_V178,
+    DR_REG_V179, DR_REG_V180, DR_REG_V181, DR_REG_V182, DR_REG_V183, DR_REG_V184,
+    DR_REG_V185, DR_REG_V186, DR_REG_V187, DR_REG_V188, DR_REG_V189, DR_REG_V190,
+    DR_REG_V191, DR_REG_V192, DR_REG_V193, DR_REG_V194, DR_REG_V195, DR_REG_V196,
+    DR_REG_V197, DR_REG_V198,
+};
+
 #ifdef DEBUG
 void
 encode_debug_checks(void)

core/ir/arm/encode.c

@@ -34,6 +34,7 @@
 /* FIXME i#1569: add A64 support: for now just A32 */
 
 #include "../globals.h"
+#include "../isa_regdeps/encoding_common.h"
 #include "arch.h"
 #include "instr.h"
 #include "decode.h"
@@ -461,6 +462,43 @@ const reg_id_t dr_reg_fixer[] = {
     DR_REG_TPIDRURO,
 };
 
+/* Maps containing-registers to their DR_ISA_REGDEPS virtual-register.
+ * Same size as dr_reg_fixer[], keep them synched.
+ * Note: DR_REG_INVALID (== DR_REG_V1 == 1) has been excluded to avoid failures on opnd_t
+ * operations.
+ */
+const reg_id_t dr_reg_virtual[] = {
+    DR_REG_V0,  DR_REG_V0,  DR_REG_V2,  DR_REG_V3,  DR_REG_V4,  DR_REG_V5,  DR_REG_V6,
+    DR_REG_V7,  DR_REG_V8,  DR_REG_V9,  DR_REG_V10, DR_REG_V11, DR_REG_V12, DR_REG_V13,
+    DR_REG_V14, DR_REG_V15, DR_REG_V16, DR_REG_V17, DR_REG_V18, DR_REG_V19, DR_REG_V20,
+    DR_REG_V21, DR_REG_V22, DR_REG_V23, DR_REG_V24, DR_REG_V25, DR_REG_V26, DR_REG_V27,
+    DR_REG_V28, DR_REG_V29, DR_REG_V30, DR_REG_V31, DR_REG_V32, DR_REG_V33, DR_REG_V34,
+    DR_REG_V35, DR_REG_V36, DR_REG_V37, DR_REG_V38, DR_REG_V39, DR_REG_V40, DR_REG_V41,
+    DR_REG_V42, DR_REG_V43, DR_REG_V44, DR_REG_V45, DR_REG_V46, DR_REG_V47, DR_REG_V48,
+    DR_REG_V49, DR_REG_V18, DR_REG_V18, DR_REG_V19, DR_REG_V19, DR_REG_V20, DR_REG_V20,
+    DR_REG_V21, DR_REG_V21, DR_REG_V22, DR_REG_V22, DR_REG_V23, DR_REG_V23, DR_REG_V24,
+    DR_REG_V24, DR_REG_V25, DR_REG_V25, DR_REG_V26, DR_REG_V26, DR_REG_V27, DR_REG_V27,
+    DR_REG_V28, DR_REG_V28, DR_REG_V29, DR_REG_V29, DR_REG_V30, DR_REG_V30, DR_REG_V31,
+    DR_REG_V31, DR_REG_V32, DR_REG_V32, DR_REG_V33, DR_REG_V33, DR_REG_V18, DR_REG_V18,
+    DR_REG_V18, DR_REG_V18, DR_REG_V19, DR_REG_V19, DR_REG_V19, DR_REG_V19, DR_REG_V20,
+    DR_REG_V20, DR_REG_V20, DR_REG_V20, DR_REG_V21, DR_REG_V21, DR_REG_V21, DR_REG_V21,
+    DR_REG_V22, DR_REG_V22, DR_REG_V22, DR_REG_V22, DR_REG_V23, DR_REG_V23, DR_REG_V23,
+    DR_REG_V23, DR_REG_V24, DR_REG_V24, DR_REG_V24, DR_REG_V24, DR_REG_V25, DR_REG_V25,
+    DR_REG_V25, DR_REG_V25, DR_REG_V18, DR_REG_V19, DR_REG_V20, DR_REG_V21, DR_REG_V22,
+    DR_REG_V23, DR_REG_V24, DR_REG_V25, DR_REG_V26, DR_REG_V27, DR_REG_V28, DR_REG_V29,
+    DR_REG_V30, DR_REG_V31, DR_REG_V32, DR_REG_V33, DR_REG_V50, DR_REG_V51, DR_REG_V52,
+    DR_REG_V53, DR_REG_V54, DR_REG_V55, DR_REG_V56, DR_REG_V57, DR_REG_V58, DR_REG_V59,
+    DR_REG_V60, DR_REG_V61, DR_REG_V62, DR_REG_V63, DR_REG_V64, DR_REG_V65, DR_REG_V18,
+    DR_REG_V19, DR_REG_V20, DR_REG_V21, DR_REG_V22, DR_REG_V23, DR_REG_V24, DR_REG_V25,
+    DR_REG_V26, DR_REG_V27, DR_REG_V28, DR_REG_V29, DR_REG_V30, DR_REG_V31, DR_REG_V32,
+    DR_REG_V33, DR_REG_V50, DR_REG_V51, DR_REG_V52, DR_REG_V53, DR_REG_V54, DR_REG_V55,
+    DR_REG_V56, DR_REG_V57, DR_REG_V58, DR_REG_V59, DR_REG_V60, DR_REG_V61, DR_REG_V62,
+    DR_REG_V63, DR_REG_V64, DR_REG_V65, DR_REG_V66, DR_REG_V67, DR_REG_V68, DR_REG_V69,
+    DR_REG_V70, DR_REG_V71, DR_REG_V72, DR_REG_V73, DR_REG_V74, DR_REG_V75, DR_REG_V76,
+    DR_REG_V77, DR_REG_V78, DR_REG_V79, DR_REG_V80, DR_REG_V81, DR_REG_V82, DR_REG_V83,
+    DR_REG_V84, DR_REG_V85, DR_REG_V86,
+};
+
 const char *const type_names[] = {
     "TYPE_NONE",
     "TYPE_R_A",

core/ir/instr_shared.c

@@ -3018,9 +3018,10 @@ instr_convert_to_isa_regdeps(void *drcontext, instr_t *instr_real_isa,
                 /* Map sub-registers to their containing register.
                  */
                 reg_id_t reg_canonical = reg_to_pointer_sized(reg);
-                if (!src_reg_used[reg_canonical]) {
+                reg_id_t reg_virtual = reg_to_virtual(reg_canonical);
+                if (!src_reg_used[reg_virtual]) {
                     ++num_srcs;
-                    src_reg_used[reg_canonical] = true;
+                    src_reg_used[reg_virtual] = true;
                 }
             }
         } else {
@@ -3029,9 +3030,10 @@ instr_convert_to_isa_regdeps(void *drcontext, instr_t *instr_real_isa,
                 /* Map sub-registers to their containing register.
                  */
                 reg_id_t reg_canonical = reg_to_pointer_sized(reg);
-                if (!dst_reg_used[reg_canonical]) {
+                reg_id_t reg_virtual = reg_to_virtual(reg_canonical);
+                if (!dst_reg_used[reg_virtual]) {
                     ++num_dsts;
-                    dst_reg_used[reg_canonical] = true;
+                    dst_reg_used[reg_virtual] = true;
                 }
             }
         }
@@ -3058,9 +3060,10 @@ instr_convert_to_isa_regdeps(void *drcontext, instr_t *instr_real_isa,
             /* Map sub-registers to their containing register.
              */
             reg_id_t reg_canonical = reg_to_pointer_sized(reg);
-            if (!src_reg_used[reg_canonical]) {
+            reg_id_t reg_virtual = reg_to_virtual(reg_canonical);
+            if (!src_reg_used[reg_virtual]) {
                 ++num_srcs;
-                src_reg_used[reg_canonical] = true;
+                src_reg_used[reg_virtual] = true;
             }
         }
     }
@@ -3092,7 +3095,8 @@ instr_convert_to_isa_regdeps(void *drcontext, instr_t *instr_real_isa,
     /* Convert max_src_opnd_size_bytes from number of bytes to opnd_size_t (which holds
      * OPSZ_ enum values).
      */
-    instr_regdeps_isa->operation_size = opnd_size_from_bytes(max_src_opnd_size_bytes);
+    opnd_size_t max_opnd_size = opnd_size_from_bytes(max_src_opnd_size_bytes);
+    instr_regdeps_isa->operation_size = max_opnd_size;
 
     /* Set the source and destination register operands for the converted instruction.
      */
@@ -3101,6 +3105,7 @@ instr_convert_to_isa_regdeps(void *drcontext, instr_t *instr_real_isa,
         for (uint reg = 0; reg < REGDEPS_MAX_NUM_REGS; ++reg) {
             if (dst_reg_used[reg]) {
                 opnd_t dst_opnd = opnd_create_reg((reg_id_t)reg);
+                opnd_set_size(&dst_opnd, max_opnd_size);
                 instr_set_dst(instr_regdeps_isa, reg_counter, dst_opnd);
                 ++reg_counter;
             }
@@ -3112,6 +3117,7 @@ instr_convert_to_isa_regdeps(void *drcontext, instr_t *instr_real_isa,
         for (uint reg = 0; reg < REGDEPS_MAX_NUM_REGS; ++reg) {
             if (src_reg_used[reg]) {
                 opnd_t src_opnd = opnd_create_reg((reg_id_t)reg);
+                opnd_set_size(&src_opnd, max_opnd_size);
                 instr_set_src(instr_regdeps_isa, reg_counter, src_opnd);
                 ++reg_counter;
             }

core/ir/isa_regdeps/decode.c

@@ -98,6 +98,7 @@ decode_isa_regdeps(dcontext_t *dcontext, byte *encoded_instr, instr_t *instr)
     for (uint i = 0; i < num_dsts; ++i) {
         reg_id_t dst = (reg_id_t)encoded_instr[i + REGDEPS_OPND_INDEX];
         opnd_t dst_opnd = opnd_create_reg((reg_id_t)dst);
+        opnd_set_size(&dst_opnd, max_opnd_size);
         instr_set_dst(instr, i, dst_opnd);
     }
 
@@ -106,6 +107,7 @@ decode_isa_regdeps(dcontext_t *dcontext, byte *encoded_instr, instr_t *instr)
     for (uint i = 0; i < num_srcs; ++i) {
         reg_id_t src = (reg_id_t)encoded_instr[i + REGDEPS_OPND_INDEX + num_dsts];
         opnd_t src_opnd = opnd_create_reg((reg_id_t)src);
+        opnd_set_size(&src_opnd, max_opnd_size);
         instr_set_src(instr, i, src_opnd);
     }
 

core/ir/isa_regdeps/encoding_common.c

@@ -0,0 +1,67 @@
+/* **********************************************************
+ * Copyright (c) 2024 Google, Inc.  All rights reserved.
+ * **********************************************************/
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright notice,
+ *   this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright notice,
+ *   this list of conditions and the following disclaimer in the documentation
+ *   and/or other materials provided with the distribution.
+ *
+ * * Neither the name of VMware, Inc. nor the names of its contributors may be
+ *   used to endorse or promote products derived from this software without
+ *   specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL VMWARE, INC. OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ */
+
+#include "encoding_common.h"
+
+/* Keep reg_virtual_names[] and DR_REG_V* enum in encoding_common.h synched.
+ */
+const char *const reg_virtual_names[] = {
+    "rv0",   "rv1",   "rv2",   "rv3",   "rv4",   "rv5",   "rv6",   "rv7",   "rv8",
+    "rv9",   "rv10",  "rv11",  "rv12",  "rv13",  "rv14",  "rv15",  "rv16",  "rv17",
+    "rv18",  "rv19",  "rv20",  "rv21",  "rv22",  "rv23",  "rv24",  "rv25",  "rv26",
+    "rv27",  "rv28",  "rv29",  "rv30",  "rv31",  "rv32",  "rv33",  "rv34",  "rv35",
+    "rv36",  "rv37",  "rv38",  "rv39",  "rv40",  "rv41",  "rv42",  "rv43",  "rv44",
+    "rv45",  "rv46",  "rv47",  "rv48",  "rv49",  "rv50",  "rv51",  "rv52",  "rv53",
+    "rv54",  "rv55",  "rv56",  "rv57",  "rv58",  "rv59",  "rv60",  "rv61",  "rv62",
+    "rv63",  "rv64",  "rv65",  "rv66",  "rv67",  "rv68",  "rv69",  "rv70",  "rv71",
+    "rv72",  "rv73",  "rv74",  "rv75",  "rv76",  "rv77",  "rv78",  "rv79",  "rv80",
+    "rv81",  "rv82",  "rv83",  "rv84",  "rv85",  "rv86",  "rv87",  "rv88",  "rv89",
+    "rv90",  "rv91",  "rv92",  "rv93",  "rv94",  "rv95",  "rv96",  "rv97",  "rv98",
+    "rv99",  "rv100", "rv101", "rv102", "rv103", "rv104", "rv105", "rv106", "rv107",
+    "rv108", "rv109", "rv110", "rv111", "rv112", "rv113", "rv114", "rv115", "rv116",
+    "rv117", "rv118", "rv119", "rv120", "rv121", "rv122", "rv123", "rv124", "rv125",
+    "rv126", "rv127", "rv128", "rv129", "rv130", "rv131", "rv132", "rv133", "rv134",
+    "rv135", "rv136", "rv137", "rv138", "rv139", "rv140", "rv141", "rv142", "rv143",
+    "rv144", "rv145", "rv146", "rv147", "rv148", "rv149", "rv150", "rv151", "rv152",
+    "rv153", "rv154", "rv155", "rv156", "rv157", "rv158", "rv159", "rv160", "rv161",
+    "rv162", "rv163", "rv164", "rv165", "rv166", "rv167", "rv168", "rv169", "rv170",
+    "rv171", "rv172", "rv173", "rv174", "rv175", "rv176", "rv177", "rv178", "rv179",
+    "rv180", "rv181", "rv182", "rv183", "rv184", "rv185", "rv186", "rv187", "rv188",
+    "rv189", "rv190", "rv191", "rv192", "rv193", "rv194", "rv195", "rv196", "rv197",
+    "rv198", "rv199", "rv200", "rv201", "rv202", "rv203", "rv204", "rv205", "rv206",
+    "rv207", "rv208", "rv209", "rv210", "rv211", "rv212", "rv213", "rv214", "rv215",
+    "rv216", "rv217", "rv218", "rv219", "rv220", "rv221", "rv222", "rv223", "rv224",
+    "rv225", "rv226", "rv227", "rv228", "rv229", "rv230", "rv231", "rv232", "rv233",
+    "rv234", "rv235", "rv236", "rv237", "rv238", "rv239", "rv240", "rv241", "rv242",
+    "rv243", "rv244", "rv245", "rv246", "rv247", "rv248", "rv249", "rv250", "rv251",
+    "rv252", "rv253", "rv254", "rv255",
+};