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i#5505 kernel trace: Support privileged xsaves xrstors instrs #6488

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Dec 3, 2023
Merged

i#5505 kernel trace: Support privileged xsaves xrstors instrs #6488

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6ecd0ce
i#5505 kernel trace: Support privileged xsaves xrstors instrs
abhinav92003 Dec 1, 2023
725b7c6
Clang format
abhinav92003 Dec 1, 2023
a26138e
Remove disabled xsaves test that is already included in new ones.
abhinav92003 Dec 1, 2023
ab707f7
Add more variants of xrstors/xsaves to tests.
abhinav92003 Dec 3, 2023
64f4585
Merge branch 'master' into i5505-add-priv-opcodes
abhinav92003 Dec 3, 2023
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22 changes: 19 additions & 3 deletions core/ir/x86/decode_table.c
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Expand Up @@ -1626,7 +1626,15 @@ const instr_info_t * const op_instr[] =

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/* Supervisor Mode Access Prevention (SMAP) */
/* OP_clac */ &rm_extensions[1][2],
/* OP_stac */ &rm_extensions[1][3]
/* OP_stac */ &rm_extensions[1][3],

/* Supervisor versions of save/restore processor extended
* state operations.
*/
/* OP_xsaves32 */ &rex_w_extensions[6][0],
/* OP_xsaves64 */ &rex_w_extensions[6][1],
/* OP_xrstors32 */ &rex_w_extensions[7][0],
/* OP_xrstors64 */ &rex_w_extensions[7][1],
};


Expand Down Expand Up @@ -2949,9 +2957,9 @@ const instr_info_t base_extensions[][8] = {
{INVALID, 0x0fc730, catUncategorized, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
{OP_cmpxchg8b, 0x0fc731, catUncategorized, "cmpxchg8b", Mq_dq, eAX, Mq_dq, eAX, eDX, mrm_xop, fWZ, exop[0x07]},/*"cmpxchg16b" w/ rex.w*/
{INVALID, 0x0fc732, catUncategorized, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
{INVALID, 0x0fc733, catUncategorized, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
{REX_W_EXT, 0x0fc733, catUncategorized, "(rex.w ext 7)", xx, xx, xx, xx, xx, mrm, x, 7},
{REX_W_EXT, 0x0fc734, catUncategorized, "(rex.w ext 5)", xx, xx, xx, xx, xx, mrm, x, 5},
{INVALID, 0x0fc735, catUncategorized, "(bad)", xx, xx, xx, xx, xx, no, x, NA},
{REX_W_EXT, 0x0fc735, catUncategorized, "(rex.w ext 6)", xx, xx, xx, xx, xx, mrm, x, 6},
{MOD_EXT, 0x0fc736, catUncategorized, "(group 9 mod ext 12)", xx, xx, xx, xx, xx, mrm, x, 12},
{MOD_EXT, 0x0fc737, catUncategorized, "(mod ext 13)", xx, xx, xx, xx, xx, mrm, x, 13},
},
Expand Down Expand Up @@ -7238,6 +7246,14 @@ const instr_info_t rex_w_extensions[][2] = {
{OP_xsavec32, 0x0fc734, catFP | catState, "xsavec", Mxsave, xx, edx, eax, xx, mrm, x, END_LIST},
{OP_xsavec64, 0x0fc734, catFP | catState, "xsavec64", Mxsave, xx, edx, eax, xx, mrm|rex, o64, END_LIST},
},
{ /* rex.w extension 6 */
{OP_xsaves32, 0x0fc735, catFP | catState, "xsaves", Mxsave, xx, edx, eax, xx, mrm, x, END_LIST},
{OP_xsaves64, 0x0fc735, catFP | catState, "xsaves64", Mxsave, xx, edx, eax, xx, mrm|rex, o64, END_LIST},
},
{ /* rex.w extension 7 */
{OP_xrstors32, 0x0fc733, catFP | catState, "xrstors", xx, xx, Mxsave, edx, eax, mrm, x, END_LIST},
{OP_xrstors64, 0x0fc733, catFP | catState, "xrstors64", xx, xx, Mxsave, edx, eax, mrm|rex, o64, END_LIST},
},
};

/****************************************************************************
Expand Down
13 changes: 13 additions & 0 deletions core/ir/x86/instr_create_api.h
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Original file line number Diff line number Diff line change
Expand Up @@ -966,6 +966,10 @@
#define INSTR_CREATE_xrstor32(dc, s) \
instr_create_0dst_3src((dc), OP_xrstor32, (s), opnd_create_reg(DR_REG_EDX), \
opnd_create_reg(DR_REG_EAX))
#define INSTR_CREATE_xrstors32(dc, s) \
instr_create_0dst_3src((dc), OP_xrstors32, (s), opnd_create_reg(DR_REG_EDX), \
opnd_create_reg(DR_REG_EAX))

/**
* This INSTR_CREATE_xxx macro creates an instr_t with opcode OP_xxx, automatically
* supplying any implicit operands.
Expand All @@ -976,6 +980,9 @@
#define INSTR_CREATE_xrstor64(dc, s) \
instr_create_0dst_3src((dc), OP_xrstor64, (s), opnd_create_reg(DR_REG_EDX), \
opnd_create_reg(DR_REG_EAX))
#define INSTR_CREATE_xrstors64(dc, s) \
instr_create_0dst_3src((dc), OP_xrstors64, (s), opnd_create_reg(DR_REG_EDX), \
opnd_create_reg(DR_REG_EAX))
/** @} */ /* end doxygen group */

/** @name No destination, 3 sources */
Expand Down Expand Up @@ -3250,9 +3257,15 @@
#define INSTR_CREATE_xsave32(dc, d) \
instr_create_1dst_2src((dc), OP_xsave32, (d), opnd_create_reg(DR_REG_EDX), \
opnd_create_reg(DR_REG_EAX))
#define INSTR_CREATE_xsaves32(dc, d) \
instr_create_1dst_2src((dc), OP_xsaves32, (d), opnd_create_reg(DR_REG_EDX), \
opnd_create_reg(DR_REG_EAX))
#define INSTR_CREATE_xsave64(dc, d) \
instr_create_1dst_2src((dc), OP_xsave64, (d), opnd_create_reg(DR_REG_EDX), \
opnd_create_reg(DR_REG_EAX))
#define INSTR_CREATE_xsaves64(dc, d) \
instr_create_1dst_2src((dc), OP_xsaves64, (d), opnd_create_reg(DR_REG_EDX), \
opnd_create_reg(DR_REG_EAX))
#define INSTR_CREATE_xsaveopt32(dc, d) \
instr_create_1dst_2src((dc), OP_xsaveopt32, (d), opnd_create_reg(DR_REG_EDX), \
opnd_create_reg(DR_REG_EAX))
Expand Down
4 changes: 4 additions & 0 deletions core/ir/x86/opcode_api.h
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Expand Up @@ -1617,6 +1617,10 @@ enum {
/* Supervisor Mode Access Prevention (SMAP) */
/* 1435 */ OP_clac,
/* 1436 */ OP_stac,
/* 1437 */ OP_xsaves32,
/* 1438 */ OP_xsaves64,
/* 1439 */ OP_xrstors32,
/* 1440 */ OP_xrstors64,
OP_AFTER_LAST,
OP_FIRST = OP_add, /**< First real opcode. */
OP_LAST = OP_AFTER_LAST - 1, /**< Last real opcode. */
Expand Down
4 changes: 4 additions & 0 deletions suite/tests/api/ir_x86_1args.h
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Expand Up @@ -111,9 +111,13 @@ OPCODE(vmptrld, vmptrld, vmptrld, X64_ONLY, MEMARG(OPSZ_8))
OPCODE(vmxon, vmxon, vmxon, X64_ONLY, MEMARG(OPSZ_8))
OPCODE(vmclear, vmclear, vmclear, X64_ONLY, MEMARG(OPSZ_8))
OPCODE(xsave32, xsave32, xsave32, 0, MEMARG(OPSZ_xsave))
OPCODE(xsaves32, xsaves32, xsaves32, 0, MEMARG(OPSZ_xsave))
OPCODE(xsave64, xsave64, xsave64, X64_ONLY, MEMARG(OPSZ_xsave))
OPCODE(xsaves64, xsaves64, xsaves64, X64_ONLY, MEMARG(OPSZ_xsave))
OPCODE(xrstor32, xrstor32, xrstor32, 0, MEMARG(OPSZ_xsave))
OPCODE(xrstors32, xrstors32, xrstors32, 0, MEMARG(OPSZ_xsave))
OPCODE(xrstor64, xrstor64, xrstor64, X64_ONLY, MEMARG(OPSZ_xsave))
OPCODE(xrstors64, xrstors64, xrstors64, X64_ONLY, MEMARG(OPSZ_xsave))
OPCODE(xsaveopt32, xsaveopt32, xsaveopt32, 0, MEMARG(OPSZ_xsave))
OPCODE(xsaveopt64, xsaveopt64, xsaveopt64, X64_ONLY, MEMARG(OPSZ_xsave))
OPCODE(xsavec32, xsavec32, xsavec32, 0, MEMARG(OPSZ_xsave))
Expand Down
60 changes: 60 additions & 0 deletions third_party/binutils/test_decenc/drdecode_decenc_x86.expect
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Expand Up @@ -138762,6 +138762,66 @@ test_s:
7b 00 00 00
62 f2 7d 29 91 b4 f5 vpgatherqd 0x0000007b(%ebp,%ymm6,8), %ymm6 {%k1} {%k1}
7b 00 00 00
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
0f c7 28 xsaves (%eax)
0f c7 69 37 xsaves 0x37(%ecx)
0f c7 2c 71 xsaves (%ecx,%esi,2)
0f c7 ac f4 c0 1d fe xsaves -0x0001e240(%esp,%esi,8)
ff
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
0f c7 18 xrstors (%eax)
0f c7 1b xrstors (%ebx)
0f c7 59 37 xrstors 0x37(%ecx)
0f c7 1c 71 xrstors (%ecx,%esi,2)
0f c7 9c f0 23 01 00 xrstors 0x00000123(%eax,%esi,8)
00
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop
90 nop

0f 01 ca clac
0f 01 cb stac
90 nop
Expand Down
26 changes: 26 additions & 0 deletions third_party/binutils/test_decenc/drdecode_decenc_x86_64.expect
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Expand Up @@ -102826,6 +102826,32 @@ test_x86_64_s:
c4 e2 59 53 11 vpdpwssds %xmm4, (%rcx), %xmm2
62 b2 5d 08 53 d6 vpdpwssds %xmm4, %xmm22, %xmm2 {%k0}
62 d2 5d 08 50 d4 vpdpbusd %xmm4, %xmm12, %xmm2 {%k0}
0f c7 28 xsaves (%rax)
0f c7 69 37 xsaves 0x37(%rcx)
42 0f c7 2c 01 xsaves (%rcx,%r8)
0f c7 ac f0 23 01 00 xsaves 0x00000123(%rax,%rsi,8)
00
48 0f c7 28 xsaves64 (%rax)
48 0f c7 69 37 xsaves64 0x37(%rcx)
4a 0f c7 2c 01 xsaves64 (%rcx,%r8)
4a 0f c7 ac f0 23 01 xsaves64 0x00000123(%rax,%r14,8)
00 00
0f c7 18 xrstors (%rax)
0f c7 59 37 xrstors 0x37(%rcx)
41 0f c7 18 xrstors (%r8)
41 0f c7 1c 00 xrstors (%r8,%rax)
42 0f c7 1c 00 xrstors (%rax,%r8)
0f c7 9c f0 23 01 00 xrstors 0x00000123(%rax,%rsi,8)
00
43 0f c7 1c 38 xrstors (%r8,%r15)
48 0f c7 18 xrstors64 (%rax)
48 0f c7 59 37 xrstors64 0x37(%rcx)
49 0f c7 18 xrstors64 (%r8)
48 0f c7 9c f0 23 01 xrstors64 0x00000123(%rax,%rsi,8)
00 00
49 0f c7 1c 00 xrstors64 (%r8,%rax)
4a 0f c7 1c 00 xrstors64 (%rax,%r8)
4b 0f c7 1c 38 xrstors64 (%r8,%r15)
0f 01 ca clac
0f 01 cb stac
90 nop
Expand Down
21 changes: 19 additions & 2 deletions third_party/binutils/test_decenc/test_decenc_x86.asm
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Expand Up @@ -304,8 +304,6 @@ GLOBAL_LABEL(FUNCNAME:)
/* FIXME i3577: clzero, AMD only. */
/* RAW(0f) RAW(01) RAW(fc) */
RAW(0f) RAW(c7) RAW(21)
/* xsaves, CPL 0 instruction. */
/* RAW(0f) RAW(c7) RAW(29) */
RAW(66) RAW(0f) RAW(ae) RAW(39)
/* monitorx, AMD only. */
RAW(0f) RAW(01) RAW(fa)
Expand Down Expand Up @@ -139588,6 +139586,25 @@ GLOBAL_LABEL(FUNCNAME:)
RAW(7b) RAW(00) RAW(00) RAW(00)
RAW(62) RAW(f2) RAW(7d) RAW(29) RAW(91) RAW(b4) RAW(f5)
RAW(7b) RAW(00) RAW(00) RAW(00)
END_OF_SUBTEST_MARKER

/* xsaves.s CPL 0 instruction */
RAW(0f) RAW(c7) RAW(28)
RAW(0f) RAW(c7) RAW(69) RAW(37)
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RAW(0f) RAW(c7) RAW(2c) RAW(71)
RAW(0f) RAW(c7) RAW(ac) RAW(f4) RAW(c0) RAW(1d) RAW(fe)
RAW(ff)
END_OF_SUBTEST_MARKER

/* xrstors.s */
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RAW(0f) RAW(c7) RAW(18)
RAW(0f) RAW(c7) RAW(1b)
RAW(0f) RAW(c7) RAW(59) RAW(37)
RAW(0f) RAW(c7) RAW(1c) RAW(71)
RAW(0f) RAW(c7) RAW(9c) RAW(f0) RAW(23)
RAW(01) RAW(00) RAW(00)

END_OF_SUBTEST_MARKER

/* TODO i#5505: Move the following back under
* arch_13.s in a separate PR to keep the huge
Expand Down
34 changes: 32 additions & 2 deletions third_party/binutils/test_decenc/test_decenc_x86_64.asm
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Expand Up @@ -231,8 +231,6 @@ GLOBAL_LABEL(FUNCNAME:)
RAW(48)
RAW(0f) RAW(c7) RAW(21)
RAW(48)
/* xsaves, CPL 0 instruction. */
/* RAW(0f) RAW(c7) RAW(29) */
RAW(66) RAW(0f) RAW(ae) RAW(39)
/* monitorx, AMD only. */
RAW(0f) RAW(01) RAW(fa)
Expand Down Expand Up @@ -106651,6 +106649,38 @@ GLOBAL_LABEL(FUNCNAME:)
RAW(62) RAW(b2) RAW(5d) RAW(08) RAW(53) RAW(d6)
RAW(62) RAW(d2) RAW(5d) RAW(08) RAW(50) RAW(d4)

/* x86_64_xsaves.s CPL 0 instruction */
RAW(0f) RAW(c7) RAW(28)
RAW(0f) RAW(c7) RAW(69) RAW(37)
RAW(42) RAW(0f) RAW(c7) RAW(2c) RAW(01)
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RAW(0f) RAW(c7) RAW(ac) RAW(f0) RAW(23) RAW(01)
RAW(00) RAW(00)
RAW(48) RAW(0f) RAW(c7) RAW(28)
RAW(48) RAW(0f) RAW(c7) RAW(69) RAW(37)
RAW(4a) RAW(0f) RAW(c7) RAW(2c) RAW(01)
RAW(4a) RAW(0f) RAW(c7) RAW(ac) RAW(f0) RAW(23) RAW(01)
RAW(00) RAW(00)

/* x86_64_xrstors.s */

RAW(0f) RAW(c7) RAW(18)
RAW(0f) RAW(c7) RAW(59) RAW(37)
RAW(41) RAW(0f) RAW(c7) RAW(18)
RAW(41) RAW(0f) RAW(c7) RAW(1c) RAW(00)
RAW(42) RAW(0f) RAW(c7) RAW(1c) RAW(00)
RAW(0f) RAW(c7) RAW(9c) RAW(f0) RAW(23)
RAW(01) RAW(00) RAW(00)
RAW(43) RAW(0f) RAW(c7) RAW(1c) RAW(38)
RAW(48) RAW(0f) RAW(c7) RAW(18)
RAW(48) RAW(0f) RAW(c7) RAW(59) RAW(37)
RAW(49) RAW(0f) RAW(c7) RAW(18)
RAW(48) RAW(0f) RAW(c7) RAW(9c) RAW(f0)
RAW(23) RAW(01) RAW(00) RAW(00)
RAW(49) RAW(0f) RAW(c7) RAW(1c) RAW(00)
RAW(4a) RAW(0f) RAW(c7) RAW(1c) RAW(00)
RAW(4b) RAW(0f) RAW(c7) RAW(1c) RAW(38)


/* TODO i#5505: Move the following back under
* x86_64_arch_3.s in a separate PR to keep the huge
* diff isolated from PR #6484.
Expand Down
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