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i#3544 RV64: Adds immediate display format via IR (#6489)
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Instructions created by `INSTR_CREATE_*` macros now automatically set
the immediate display format. Also enables tool.drdisas test.

Issue #3544
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@ksco
ksco authored Dec 6, 2023
1 parent a8cf1df commit d833458
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Showing 12 changed files with 279 additions and 349 deletions.
7 changes: 7 additions & 0 deletions clients/drdisas/test_simple.template
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Original file line number Diff line number Diff line change
Expand Up @@ -22,4 +22,11 @@ disassembly failed: invalid instruction: not enough bytes: 0x88
c4 e2 65 90 14 80 vpgatherdd (%eax,%ymm0,4)[4byte] %ymm3 -> %ymm2 %ymm3
# endif
disassembly failed: invalid instruction: not enough bytes: 0x88
#elif defined(RISCV64)
853e c.mv zero a5 -> a0
4581 c.li zero 0 -> a1
1d27b783 ld +466(a5)[8byte] -> a5
00f55733 srl a0 a5 -> a4
9d89 c.subw a1 a0 -> a1
disassembly failed: invalid instruction: not enough bytes: 0x88
#endif
9 changes: 4 additions & 5 deletions core/arch/mangle_shared.c
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Original file line number Diff line number Diff line change
Expand Up @@ -584,12 +584,11 @@ insert_parameter_preparation(dcontext_t *dcontext, instrlist_t *ilist, instr_t *
if (opnd_is_reglike(arg)) {
/* sd x(...), i*XSP_SZ(sp) */
PRE(ilist, instr,
XINST_CREATE_store(
dcontext,
opnd_add_flags(opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0,
XINST_CREATE_store(dcontext,
opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0,
i * XSP_SZ, OPSZ_PTR),
DR_OPND_IMM_PRINT_DECIMAL),
opnd_is_reg(arg) ? arg : opnd_create_reg(DR_REG_ZERO)));
opnd_is_reg(arg) ? arg
: opnd_create_reg(DR_REG_ZERO)));
}
}
# else /* ARM */
Expand Down
13 changes: 4 additions & 9 deletions core/arch/riscv64/emit_utils.c
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Original file line number Diff line number Diff line change
Expand Up @@ -866,14 +866,11 @@ emit_indirect_branch_lookup(dcontext_t *dc, generated_code_t *code, byte *pc,
/* Now, a1 holds the hash table index, use slli+add to get the table entry. */
ASSERT(4 - HASHTABLE_IBL_OFFSET(ibl_code->branch_type) >= 0);
if (4 - HASHTABLE_IBL_OFFSET(ibl_code->branch_type) > 0) {
/* TODO i#3544: Immediate display format should be auto-added by the IR. */
APP(&ilist,
INSTR_CREATE_slli(
dc, opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_A1),
opnd_add_flags(
opnd_create_immed_int(4 - HASHTABLE_IBL_OFFSET(ibl_code->branch_type),
OPSZ_6b),
DR_OPND_IMM_PRINT_DECIMAL)));
opnd_create_immed_int(4 - HASHTABLE_IBL_OFFSET(ibl_code->branch_type),
OPSZ_6b)));
}
APP(&ilist,
INSTR_CREATE_add(dc, opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_A0),
Expand Down Expand Up @@ -1076,10 +1073,8 @@ append_fcache_enter_prologue(dcontext_t *dcontext, instrlist_t *ilist, bool abso
XINST_CREATE_move(dcontext, opnd_create_reg(REG_DCXT),
opnd_create_reg(DR_REG_A0)));
APP(ilist,
INSTR_CREATE_lb(
dcontext, opnd_create_reg(DR_REG_A2),
opnd_add_flags(OPND_DC_FIELD(absolute, dcontext, OPSZ_1, SIGPENDING_OFFSET),
DR_OPND_IMM_PRINT_DECIMAL)));
INSTR_CREATE_lb(dcontext, opnd_create_reg(DR_REG_A2),
OPND_DC_FIELD(absolute, dcontext, OPSZ_1, SIGPENDING_OFFSET)));
APP(ilist,
INSTR_CREATE_bge(dcontext, opnd_create_instr(no_signals),
opnd_create_reg(DR_REG_ZERO), opnd_create_reg(DR_REG_A2)));
Expand Down
99 changes: 37 additions & 62 deletions core/arch/riscv64/mangle.c
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Original file line number Diff line number Diff line change
Expand Up @@ -86,8 +86,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
PRE(ilist, instr,
INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_SP),
opnd_create_reg(DR_REG_SP),
opnd_add_flags(opnd_create_immed_int(-max_offs, OPSZ_12b),
DR_OPND_IMM_PRINT_DECIMAL)));
opnd_create_immed_int(-max_offs, OPSZ_12b)));

/* Skip X0 slot. */
dstack_offs += XSP_SZ;
Expand All @@ -98,12 +97,10 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
continue;

PRE(ilist, instr,
INSTR_CREATE_sd(
dcontext,
opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0,
dstack_offs + i * XSP_SZ, OPSZ_8),
DR_OPND_IMM_PRINT_DECIMAL),
opnd_create_reg(DR_REG_START_GPR + i)));
INSTR_CREATE_sd(dcontext,
opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0,
dstack_offs + i * XSP_SZ, OPSZ_8),
opnd_create_reg(DR_REG_START_GPR + i)));
}

dstack_offs += DR_NUM_GPR_REGS * XSP_SZ;
Expand All @@ -127,12 +124,10 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
/* Push FPRs. */
for (int i = 0; i < DR_NUM_FPR_REGS; i++) {
PRE(ilist, instr,
INSTR_CREATE_fsd(
dcontext,
opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0,
dstack_offs + i * XSP_SZ, OPSZ_8),
DR_OPND_IMM_PRINT_DECIMAL),
opnd_create_reg(DR_REG_F0 + i)));
INSTR_CREATE_fsd(dcontext,
opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0,
dstack_offs + i * XSP_SZ, OPSZ_8),
opnd_create_reg(DR_REG_F0 + i)));
}

dstack_offs += DR_NUM_FPR_REGS * XSP_SZ;
Expand Down Expand Up @@ -187,11 +182,9 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist
/* Pop FPRs. */
for (int i = 0; i < DR_NUM_FPR_REGS; i++) {
PRE(ilist, instr,
INSTR_CREATE_fld(
dcontext, opnd_create_reg(DR_REG_F0 + i),
opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0,
current_offs + i * XSP_SZ, OPSZ_8),
DR_OPND_IMM_PRINT_DECIMAL)));
INSTR_CREATE_fld(dcontext, opnd_create_reg(DR_REG_F0 + i),
opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0,
current_offs + i * XSP_SZ, OPSZ_8)));
}

/* Skip pc field. */
Expand All @@ -205,11 +198,9 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist
continue;

PRE(ilist, instr,
INSTR_CREATE_ld(
dcontext, opnd_create_reg(DR_REG_START_GPR + i),
opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0,
current_offs + i * XSP_SZ, OPSZ_8),
DR_OPND_IMM_PRINT_DECIMAL)));
INSTR_CREATE_ld(dcontext, opnd_create_reg(DR_REG_START_GPR + i),
opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0,
current_offs + i * XSP_SZ, OPSZ_8)));
}
}

Expand Down Expand Up @@ -471,25 +462,21 @@ mangle_stolen_reg_and_tp_reg(dcontext_t *dcontext, instrlist_t *ilist, instr_t *
if (opnd_is_reg(curop) && opnd_get_reg(curop) == DR_REG_TP)
instr_set_dst(instr, i, opnd_create_reg(scratch_reg));
else if (opnd_is_base_disp(curop) && opnd_get_base(curop) == DR_REG_TP) {
instr_set_dst(
instr, i,
opnd_add_flags(opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0,
opnd_get_disp(curop),
opnd_get_size(curop)),
DR_OPND_IMM_PRINT_DECIMAL));
instr_set_dst(instr, i,
opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0,
opnd_get_disp(curop),
opnd_get_size(curop)));
}
}
for (i = 0; i < instr_num_srcs(instr); i++) {
curop = instr_get_src(instr, i);
if (opnd_is_reg(curop) && opnd_get_reg(curop) == DR_REG_TP)
instr_set_src(instr, i, opnd_create_reg(scratch_reg));
else if (opnd_is_base_disp(curop) && opnd_get_base(curop) == DR_REG_TP) {
instr_set_src(
instr, i,
opnd_add_flags(opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0,
opnd_get_disp(curop),
opnd_get_size(curop)),
DR_OPND_IMM_PRINT_DECIMAL));
instr_set_src(instr, i,
opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0,
opnd_get_disp(curop),
opnd_get_size(curop)));
}
}
instr_set_translation(instr, instrlist_get_translation_target(ilist));
Expand Down Expand Up @@ -517,25 +504,21 @@ mangle_stolen_reg_and_tp_reg(dcontext_t *dcontext, instrlist_t *ilist, instr_t *
if (opnd_is_reg(curop) && opnd_get_reg(curop) == dr_reg_stolen)
instr_set_dst(instr, i, opnd_create_reg(scratch_reg));
else if (opnd_is_base_disp(curop) && opnd_get_base(curop) == dr_reg_stolen) {
instr_set_dst(
instr, i,
opnd_add_flags(opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0,
opnd_get_disp(curop),
opnd_get_size(curop)),
DR_OPND_IMM_PRINT_DECIMAL));
instr_set_dst(instr, i,
opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0,
opnd_get_disp(curop),
opnd_get_size(curop)));
}
}
for (i = 0; i < instr_num_srcs(instr); i++) {
curop = instr_get_src(instr, i);
if (opnd_is_reg(curop) && opnd_get_reg(curop) == dr_reg_stolen)
instr_set_src(instr, i, opnd_create_reg(scratch_reg));
else if (opnd_is_base_disp(curop) && opnd_get_base(curop) == dr_reg_stolen) {
instr_set_src(
instr, i,
opnd_add_flags(opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0,
opnd_get_disp(curop),
opnd_get_size(curop)),
DR_OPND_IMM_PRINT_DECIMAL));
instr_set_src(instr, i,
opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0,
opnd_get_disp(curop),
opnd_get_size(curop)));
}
}
instr_set_translation(instr, instrlist_get_translation_target(ilist));
Expand Down Expand Up @@ -749,10 +732,8 @@ mangle_exclusive_load(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
instr_set_opcode(instr, opcode);
instr_set_num_opnds(dcontext, instr, 1, 1);
instr_set_dst(instr, 0, dst);
instr_set_src(
instr, 0,
opnd_add_flags(opnd_create_base_disp(opnd_get_reg(src0), DR_REG_NULL, 0, 0, opsz),
DR_OPND_IMM_PRINT_DECIMAL));
instr_set_src(instr, 0,
opnd_create_base_disp(opnd_get_reg(src0), DR_REG_NULL, 0, 0, opsz));
instr_set_translation(instr, instrlist_get_translation_target(ilist));

/* Keep the acquire semantics if needed. */
Expand All @@ -773,9 +754,7 @@ mangle_exclusive_load(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
PRE(ilist, next_instr,
XINST_CREATE_load_int(
dcontext, opnd_create_reg(scratch_reg1),
opnd_add_flags(
opnd_create_immed_int(opnd_get_size(instr_get_src(instr, 0)), OPSZ_12b),
DR_OPND_IMM_PRINT_DECIMAL)));
opnd_create_immed_int(opnd_get_size(instr_get_src(instr, 0)), OPSZ_12b)));
PRE(ilist, next_instr,
instr_create_save_to_tls(dcontext, scratch_reg1, TLS_LRSC_SIZE_SLOT));

Expand Down Expand Up @@ -830,8 +809,7 @@ mangle_exclusive_store(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
instr_create_restore_from_tls(dcontext, scratch_reg1, TLS_LRSC_SIZE_SLOT));
PRE(ilist, instr,
XINST_CREATE_load_int(dcontext, opnd_create_reg(scratch_reg2),
opnd_add_flags(opnd_create_immed_int(opsz, OPSZ_12b),
DR_OPND_IMM_PRINT_DECIMAL)));
opnd_create_immed_int(opsz, OPSZ_12b)));
PRE(ilist, instr,
INSTR_CREATE_bne(dcontext, opnd_create_instr(fail), opnd_create_reg(scratch_reg1),
opnd_create_reg(scratch_reg2)));
Expand Down Expand Up @@ -863,9 +841,7 @@ mangle_exclusive_store(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
/* Write a non-zero value to dst on fail. */
PRE(ilist, next_instr, fail);
PRE(ilist, next_instr,
XINST_CREATE_load_int(dcontext, dst,
opnd_add_flags(opnd_create_immed_int(1, OPSZ_12b),
DR_OPND_IMM_PRINT_DECIMAL)));
XINST_CREATE_load_int(dcontext, dst, opnd_create_immed_int(1, OPSZ_12b)));

PRE(ilist, next_instr, final);

Expand All @@ -874,8 +850,7 @@ mangle_exclusive_store(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr,
*/
PRE(ilist, next_instr,
XINST_CREATE_load_int(dcontext, opnd_create_reg(scratch_reg1),
opnd_add_flags(opnd_create_immed_int(-1, OPSZ_12b),
DR_OPND_IMM_PRINT_DECIMAL)));
opnd_create_immed_int(-1, OPSZ_12b)));
PRE(ilist, next_instr,
instr_create_save_to_tls(dcontext, scratch_reg1, TLS_LRSC_ADDR_SLOT));

Expand Down
3 changes: 2 additions & 1 deletion core/ir/riscv64/codec.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1159,7 +1159,8 @@ decode_iimm_0_opnd(dcontext_t *dc, uint32_t inst, int op_sz, byte *pc, byte *ori
int idx, instr_t *out)
{
ASSERT(idx == 1);
opnd_t opnd = opnd_create_immed_int(0, op_sz);
opnd_t opnd =
opnd_add_flags(opnd_create_immed_int(0, op_sz), DR_OPND_IMM_PRINT_DECIMAL);
instr_set_src(out, idx, opnd);
return true;
}
Expand Down
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