Fix building errors for aarch64 and riscv64.

DynamoRIO · Mar 26, 2024 · 70f6942 · 70f6942
1 parent 2856ab0
commit 70f6942
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Showing 2 changed files with 1 addition and 10 deletions.
diff --git a/core/ir/aarch64/decode.c b/core/ir/aarch64/decode.c
@@ -90,15 +90,6 @@ byte *
 decode(void *drcontext, byte *pc, instr_t *instr)
 {
     dcontext_t *dcontext = (dcontext_t *)drcontext;
-
-    /* Synthetic ISA has its own decoder.
-     * XXX i#1684: when DR can be built with full dynamic architecture selection we won't
-     * need to pollute the decoding of other architectures with this synthetic ISA special
-     * case.
-     */
-    if (dr_get_isa_mode(drcontext) == DR_ISA_SYNTHETIC)
-        return decode_from_synth(dcontext, pc, instr);
-
     return decode_common(dcontext, pc, pc, instr);
 }
 

diff --git a/core/ir/riscv64/codec.c b/core/ir/riscv64/codec.c
@@ -1491,7 +1491,7 @@ decode_common(dcontext_t *dcontext, byte *pc, byte *orig_pc, instr_t *instr)
      * case.
      */
     if (dr_get_isa_mode((void *)dcontext) == DR_ISA_SYNTHETIC)
-        return decode_from_synth(drcontext, pc, instr);
+        return decode_from_synth(dcontext, pc, instr);
 
     /* Decode instruction width from the opcode. */
     int width = instruction_width(*(uint16_t *)pc);