i#3544 RV64: Add support for XTheadCmo and XTheadSync extensions (#6477)

Some of these instructions are suddenly used in newer OS release of my SBC LicheePi 4A, so added them to make it happy. Issue: #3544
DynamoRIO · Nov 30, 2023 · 2093cd1 · 2093cd1
1 parent 0254f5b
commit 2093cd1
Show file tree

Hide file tree

Showing 6 changed files with 79 additions and 0 deletions.
diff --git a/core/ir/riscv64/codec.h b/core/ir/riscv64/codec.h
@@ -81,6 +81,8 @@ typedef enum {
     RISCV64_ISA_EXT_ZICBOZ,
     RISCV64_ISA_EXT_ZICSR,
     RISCV64_ISA_EXT_ZIFENCEI,
+    RISCV64_ISA_EXT_XTHEADCMO,
+    RISCV64_ISA_EXT_XTHEADSYNC,
     RISCV64_ISA_EXT_CNT, /* Keep this last */
 } riscv64_isa_ext_t;
 

diff --git a/core/ir/riscv64/isl/xtheadcmo.txt b/core/ir/riscv64/isl/xtheadcmo.txt
@@ -0,0 +1,16 @@
+# XTheadCmo (Cache Management Operations)
+# Version 1.0
+# https://github.com/T-head-Semi/thead-extension-spec
+
+# TODO i#3544: Only list instructions that are valid in usermode for now, but we
+# would like to cover privileged instructions as well for something like standalone
+# drdecode library to work for arbitrary bits.
+
+# Clean and invalidate D-cache at virtual address
+th.dcache.civa  | i | rs1 | 000000100111.....000000000001011
+
+# Clean L1 D-cache at virtual address
+th.dcache.cval1 | i | rs1 | 000000100100.....000000000001011
+
+# Invalidate I-cache at virtual address
+th.icache.iva   | i | rs1 | 000000110000.....000000000001011
diff --git a/core/ir/riscv64/isl/xtheadsync.txt b/core/ir/riscv64/isl/xtheadsync.txt
@@ -0,0 +1,18 @@
+# XTheadSync (Multi-core synchronization instructions)
+# Version 1.0
+# https://github.com/T-head-Semi/thead-extension-spec
+
+# TODO i#3544: Only list instructions that are valid in usermode for now, but we
+# would like to cover privileged instructions as well for something like standalone
+# drdecode library to work for arbitrary bits.
+
+# Ensures that all preceding instructions retire earlier than this instruction
+# and all subsequent instructions retire later than this instruction.
+th.sync    | i | | 00000001100000000000000000001011
+th.sync.s  | i | | 00000001100100000000000000001011
+
+# Ensures that all preceding instructions retire earlier than this instruction
+# and all subsequent instructions retire later than this instruction and clears
+# the pipeline when this instruction retires.
+th.sync.i  | i | | 00000001101000000000000000001011
+th.sync.is | i | | 00000001101100000000000000001011
diff --git a/make/CMake_riscv64_gen_codec.cmake b/make/CMake_riscv64_gen_codec.cmake
@@ -72,6 +72,8 @@ add_custom_command(
           ${PROJECT_SOURCE_DIR}/core/ir/${ARCH_NAME}/isl/rvc.txt
           ${PROJECT_SOURCE_DIR}/core/ir/${ARCH_NAME}/isl/svinval.txt
           ${PROJECT_SOURCE_DIR}/core/ir/${ARCH_NAME}/isl/system.txt
+          ${PROJECT_SOURCE_DIR}/core/ir/${ARCH_NAME}/isl/xtheadcmo.txt
+          ${PROJECT_SOURCE_DIR}/core/ir/${ARCH_NAME}/isl/xtheadsync.txt
           ${PROJECT_SOURCE_DIR}/core/ir/${ARCH_NAME}/isl/zicbom.txt
           ${PROJECT_SOURCE_DIR}/core/ir/${ARCH_NAME}/isl/zicbop.txt
           ${PROJECT_SOURCE_DIR}/core/ir/${ARCH_NAME}/isl/zicboz.txt

diff --git a/suite/tests/api/ir_riscv64.c b/suite/tests/api/ir_riscv64.c
@@ -1895,6 +1895,32 @@ test_decode_bad_data(void *dc)
     test_instr_decoding_failure(dc, 0xb);
 }
 
+static void
+test_decode_xtheadcmo(void *dc)
+{
+    instr_t *instr;
+    instr = INSTR_CREATE_th_icache_iva(dc, opnd_create_reg(DR_REG_A0));
+    test_instr_encoding(dc, OP_th_icache_iva, instr);
+    instr = INSTR_CREATE_th_dcache_civa(dc, opnd_create_reg(DR_REG_A0));
+    test_instr_encoding(dc, OP_th_dcache_civa, instr);
+    instr = INSTR_CREATE_th_dcache_cval1(dc, opnd_create_reg(DR_REG_A0));
+    test_instr_encoding(dc, OP_th_dcache_cval1, instr);
+}
+
+static void
+test_decode_xtheadsync(void *dc)
+{
+    instr_t *instr;
+    instr = INSTR_CREATE_th_sync(dc);
+    test_instr_encoding(dc, OP_th_sync, instr);
+    instr = INSTR_CREATE_th_sync_s(dc);
+    test_instr_encoding(dc, OP_th_sync_s, instr);
+    instr = INSTR_CREATE_th_sync_i(dc);
+    test_instr_encoding(dc, OP_th_sync_i, instr);
+    instr = INSTR_CREATE_th_sync_is(dc);
+    test_instr_encoding(dc, OP_th_sync_is, instr);
+}
+
 int
 main(int argc, char *argv[])
 {
@@ -1956,6 +1982,12 @@ main(int argc, char *argv[])
     test_decode_bad_data(dcontext);
     print("test_decode_bad_data complete\n");
 
+    test_decode_xtheadcmo(dcontext);
+    print("test_decode_xtheadcmo complete\n");
+
+    test_decode_xtheadsync(dcontext);
+    print("test_decode_xtheadsync complete\n");
+
     print("All tests complete\n");
     return 0;
 }
diff --git a/suite/tests/api/ir_riscv64.expect b/suite/tests/api/ir_riscv64.expect
@@ -322,4 +322,13 @@ addi   a0 0xffffffd6 -> a0
 jalr   a0 0x0 -> ra
 test_xinst complete
 test_decode_bad_data complete
+th.icache.iva a0
+th.dcache.civa a0
+th.dcache.cval1 a0
+test_decode_xtheadcmo complete
+th.sync
+th.sync.s
+th.sync.i
+th.sync.is
+test_decode_xtheadsync complete
 All tests complete