i#3544 RV64: Preserve vtype and vl vector registers

Renamed VL and VTYPE to CSR_VL and CSR_VTYPE Issue: #3544
DynamoRIO · Dec 18, 2024 · 1a5e921 · 1a5e921
1 parent 549fb3d
commit 1a5e921
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Showing 2 changed files with 8 additions and 8 deletions.
diff --git a/core/arch/riscv64/emit_utils.c b/core/arch/riscv64/emit_utils.c
@@ -55,8 +55,8 @@
 #define FCSR 0x003
 #define VSTART 0x008
 #define VCSR 0x00F
-#define VL 0xC20
-#define VTYPE 0xC21
+#define CSR_VL 0xC20
+#define CSR_VTYPE 0xC21
 
 /* Instruction fixed bits constants. */
 
@@ -890,12 +890,12 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute
         APP(ilist,
             INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1),
                                opnd_create_reg(DR_REG_ZERO),
-                               opnd_create_immed_int(VL, OPSZ_12b)));
+                               opnd_create_immed_int(CSR_VL, OPSZ_12b)));
         APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VL_OFFSET));
         APP(ilist,
             INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1),
                                opnd_create_reg(DR_REG_ZERO),
-                               opnd_create_immed_int(VTYPE, OPSZ_12b)));
+                               opnd_create_immed_int(CSR_VTYPE, OPSZ_12b)));
         APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VTYPE_OFFSET));
     }
 }

diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c
@@ -46,8 +46,8 @@
 #define FCSR 0x003
 #define VSTART 0x008
 #define VCSR 0x00F
-#define VL 0xC20
-#define VTYPE 0xC21
+#define CSR_VL 0xC20
+#define CSR_VTYPE 0xC21
 
 /* TODO i#3544: Think of a better way to represent these fields in the IR. */
 /* Volume I: RISC-V Unprivileged ISA V20191213.
@@ -199,7 +199,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
         PRE(ilist, instr,
             INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0),
                                opnd_create_reg(DR_REG_ZERO),
-                               opnd_create_immed_int(VL, OPSZ_12b)));
+                               opnd_create_immed_int(CSR_VL, OPSZ_12b)));
 
         PRE(ilist, instr,
             INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs),
@@ -212,7 +212,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
         PRE(ilist, instr,
             INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0),
                                opnd_create_reg(DR_REG_ZERO),
-                               opnd_create_immed_int(VTYPE, OPSZ_12b)));
+                               opnd_create_immed_int(CSR_VTYPE, OPSZ_12b)));
 
         PRE(ilist, instr,
             INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs),