Skip to content

Commit

Permalink
i#6662 regdeps ISA: virtual registers (#6783)
Browse files Browse the repository at this point in the history 
Containing-register IDs can be >=256, hence their value does not fit
in the allotted 8 bits per register operand of regdeps encoding.
This was causing a memory corruption in instr_convert_to_isa_regdeps()
where src_reg_used and dst_reg_used have only 256 elements and are
laid out next to each other in memory. Writing to index >=256 into one
was
overwriting the other. Fix: remap containing-register IDs to
virtual-register
IDs starting from 0 for all architectures. We still have only up to 198
unique
containing registers (max number of containing registers for AARCH64),
so remapping allows to fit them in 8 bits.

In the re-mapping (from DR_REG_ to DR_REG_V) we exclude DR_REG_INVALID
and DR_REG_NULL to avoid issues with opnd_t operations for registers.

We introduce a private routine dr_reg_to_virtual() to do the mapping
from real ISA
to virtual register. We use it in instr_convert_to_isa_regdeps() to
avoid the issue
mentioned above.

We modified the get_register_name() public API to use the global
dcontext and its
ISA mode to determine whether to return a real register name or a
virtual one.
The signature of the API remained the same, but we document the use of
the global
dcontext in doxygen.

We also re-introduce setting the size for register operands in
instr_convert_to_isa_reg_deps() and decode_isa_regdeps() as
instr_t.operation_size because not all DR_REG_V have a predefined size
based on their enum value (e.g., reserved DR_REG_XMM enum values).

We added tests to check that DR_REG_ with IDs >=256 don't cause
problems.

Issue: #6662
  • Loading branch information
@edeiana
edeiana authored Apr 24, 2024
1 parent a1674fb commit 092b4f2
Show file tree
Hide file tree
Showing 14 changed files with 1,560 additions and 12 deletions.
1 change: 0 additions & 1 deletion api/docs/release.dox
View file
Original file line number Diff line number Diff line change
Expand Up @@ -227,7 +227,6 @@ Further non-compatibility-affecting changes include:
- Added instr_convert_to_isa_regdeps() API that converts an #instr_t from a real ISA
(e.g., #DR_ISA_AMD64) to the #DR_ISA_REGDEPS synthetic ISA.


**************************************************
<hr>

Expand Down
1 change: 1 addition & 0 deletions core/CMakeLists.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -279,6 +279,7 @@ set(DECODER_SRCS
ir/${ARCH_NAME}/decode.c
ir/encode_shared.c
ir/${ARCH_NAME}/encode.c
ir/isa_regdeps/encoding_common.c
ir/isa_regdeps/encode.c
ir/isa_regdeps/decode.c
ir/disassemble_shared.c
Expand Down
171 changes: 171 additions & 0 deletions core/ir/aarch64/encode.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -196,6 +196,177 @@ const reg_id_t dr_reg_fixer[] = { REG_NULL,

DR_REG_CNTVCT_EL0,
};

/* Maps real ISA registers to their corresponding virtual DR_ISA_REGDEPS register.
* Note that we map real sub-registers to their corresponding containing virtual register.
* Same size as dr_reg_fixer[], keep them synched.
*/
const reg_id_t d_r_reg_id_to_virtual[] = {
DR_REG_NULL, /* DR_REG_NULL */
DR_REG_NULL, /* DR_REG_NULL */

#define VIRTUAL_XREGS
DR_REG_V0, DR_REG_V1, DR_REG_V2, DR_REG_V3, DR_REG_V4, DR_REG_V5, DR_REG_V6, \
DR_REG_V7, DR_REG_V8, DR_REG_V9, DR_REG_V10, DR_REG_V11, DR_REG_V12, DR_REG_V13, \
DR_REG_V14, DR_REG_V15, DR_REG_V16, DR_REG_V17, DR_REG_V18, DR_REG_V19, \
DR_REG_V20, DR_REG_V21, DR_REG_V22, DR_REG_V23, DR_REG_V24, DR_REG_V25, \
DR_REG_V26, DR_REG_V27, DR_REG_V28, DR_REG_V29, DR_REG_V30, DR_REG_V31, \
DR_REG_V32,

VIRTUAL_XREGS /* from DR_REG_X0 to DR_REG_XZR */
VIRTUAL_XREGS /* from DR_REG_W0 to DR_REG_WZR */
#undef VIRTUAL_XREGS

#define VIRTUAL_ZREGS
DR_REG_V33, DR_REG_V34, DR_REG_V35, DR_REG_V36, DR_REG_V37, DR_REG_V38, DR_REG_V39, \
DR_REG_V40, DR_REG_V41, DR_REG_V42, DR_REG_V43, DR_REG_V44, DR_REG_V45, DR_REG_V46, \
DR_REG_V47, DR_REG_V48, DR_REG_V49, DR_REG_V50, DR_REG_V51, DR_REG_V52, \
DR_REG_V53, DR_REG_V54, DR_REG_V55, DR_REG_V56, DR_REG_V57, DR_REG_V58, \
DR_REG_V59, DR_REG_V60, DR_REG_V61, DR_REG_V62, DR_REG_V63, DR_REG_V64,

VIRTUAL_ZREGS /* from DR_REG_Z0 to DR_REG_Z31 */
VIRTUAL_ZREGS /* from DR_REG_Q0 to DR_REG_Q31 */
VIRTUAL_ZREGS /* from DR_REG_D0 to DR_REG_D31 */
VIRTUAL_ZREGS /* from DR_REG_S0 to DR_REG_S31 */
VIRTUAL_ZREGS /* from DR_REG_H0 to DR_REG_H31 */
VIRTUAL_ZREGS /* from DR_REG_B0 to DR_REG_B31 */
#undef VIRTUAL_ZREGS

DR_REG_V65, /* DR_REG_NZCV */
DR_REG_V66, /* DR_REG_FPCR */
DR_REG_V67, /* DR_REG_FPSR */
DR_REG_V68, /* DR_REG_MDCCSR_EL0 */
DR_REG_V69, /* DR_REG_DBGDTR_EL0 */
DR_REG_V70, /* DR_REG_DBGDTRRX_EL0 */
DR_REG_V71, /* DR_REG_SP_EL0 */
DR_REG_V72, /* DR_REG_SPSEL */
DR_REG_V73, /* DR_REG_DAIFSET */
DR_REG_V74, /* DR_REG_DAIFCLR */
DR_REG_V75, /* DR_REG_CURRENTEL */
DR_REG_V76, /* DR_REG_PAN */
DR_REG_V77, /* DR_REG_UAO */
DR_REG_V78, /* DR_REG_CTR_EL0 */
DR_REG_V79, /* DR_REG_DCZID_EL0 */
DR_REG_V80, /* DR_REG_RNDR */
DR_REG_V81, /* DR_REG_RNDRRS */
DR_REG_V82, /* DR_REG_DAIF */
DR_REG_V83, /* DR_REG_DIT */
DR_REG_V84, /* DR_REG_SSBS */
DR_REG_V85, /* DR_REG_TCO */
DR_REG_V86, /* DR_REG_DSPSR_EL0 */
DR_REG_V87, /* DR_REG_DLR_EL0 */
DR_REG_V88, /* DR_REG_PMCR_EL0 */
DR_REG_V89, /* DR_REG_PMCNTENSET_EL0 */
DR_REG_V90, /* DR_REG_PMCNTENCLR_EL0 */
DR_REG_V91, /* DR_REG_PMOVSCLR_EL0 */
DR_REG_V92, /* DR_REG_PMSWINC_EL0 */
DR_REG_V93, /* DR_REG_PMSELR_EL0 */
DR_REG_V94, /* DR_REG_PMCEID0_EL0 */
DR_REG_V95, /* DR_REG_PMCEID1_EL0 */
DR_REG_V96, /* DR_REG_PMCCNTR_EL0 */
DR_REG_V97, /* DR_REG_PMXEVTYPER_EL0 */
DR_REG_V98, /* DR_REG_PMXEVCNTR_EL0 */
DR_REG_V99, /* DR_REG_PMUSERENR_EL0 */
DR_REG_V100, /* DR_REG_PMOVSSET_EL0 */
DR_REG_V101, /* DR_REG_SCXTNUM_EL0 */
DR_REG_V102, /* DR_REG_CNTFRQ_EL0 */
DR_REG_V103, /* DR_REG_CNTPCT_EL0 */
DR_REG_V104, /* DR_REG_CNTP_TVAL_EL0 */
DR_REG_V105, /* DR_REG_CNTP_CTL_EL0 */
DR_REG_V106, /* DR_REG_CNTP_CVAL_EL0 */
DR_REG_V107, /* DR_REG_CNTV_TVAL_EL0 */
DR_REG_V108, /* DR_REG_CNTV_CTL_EL0 */
DR_REG_V109, /* DR_REG_CNTV_CVAL_EL0 */
DR_REG_V110, /* DR_REG_PMEVCNTR0_EL0 */
DR_REG_V111, /* DR_REG_PMEVCNTR1_EL0 */
DR_REG_V112, /* DR_REG_PMEVCNTR2_EL0 */
DR_REG_V113, /* DR_REG_PMEVCNTR3_EL0 */
DR_REG_V114, /* DR_REG_PMEVCNTR4_EL0 */
DR_REG_V115, /* DR_REG_PMEVCNTR5_EL0 */
DR_REG_V116, /* DR_REG_PMEVCNTR6_EL0 */
DR_REG_V117, /* DR_REG_PMEVCNTR7_EL0 */
DR_REG_V118, /* DR_REG_PMEVCNTR8_EL0 */
DR_REG_V119, /* DR_REG_PMEVCNTR9_EL0 */
DR_REG_V120, /* DR_REG_PMEVCNTR10_EL0 */
DR_REG_V121, /* DR_REG_PMEVCNTR11_EL0 */
DR_REG_V122, /* DR_REG_PMEVCNTR12_EL0 */
DR_REG_V123, /* DR_REG_PMEVCNTR13_EL0 */
DR_REG_V124, /* DR_REG_PMEVCNTR14_EL0 */
DR_REG_V125, /* DR_REG_PMEVCNTR15_EL0 */
DR_REG_V126, /* DR_REG_PMEVCNTR16_EL0 */
DR_REG_V127, /* DR_REG_PMEVCNTR17_EL0 */
DR_REG_V128, /* DR_REG_PMEVCNTR18_EL0 */
DR_REG_V129, /* DR_REG_PMEVCNTR19_EL0 */
DR_REG_V130, /* DR_REG_PMEVCNTR20_EL0 */
DR_REG_V131, /* DR_REG_PMEVCNTR21_EL0 */
DR_REG_V132, /* DR_REG_PMEVCNTR22_EL0 */
DR_REG_V133, /* DR_REG_PMEVCNTR23_EL0 */
DR_REG_V134, /* DR_REG_PMEVCNTR24_EL0 */
DR_REG_V135, /* DR_REG_PMEVCNTR25_EL0 */
DR_REG_V136, /* DR_REG_PMEVCNTR26_EL0 */
DR_REG_V137, /* DR_REG_PMEVCNTR27_EL0 */
DR_REG_V138, /* DR_REG_PMEVCNTR28_EL0 */
DR_REG_V139, /* DR_REG_PMEVCNTR29_EL0 */
DR_REG_V140, /* DR_REG_PMEVCNTR30_EL0 */
DR_REG_V141, /* DR_REG_PMEVTYPER0_EL0 */
DR_REG_V142, /* DR_REG_PMEVTYPER1_EL0 */
DR_REG_V143, /* DR_REG_PMEVTYPER2_EL0 */
DR_REG_V144, /* DR_REG_PMEVTYPER3_EL0 */
DR_REG_V145, /* DR_REG_PMEVTYPER4_EL0 */
DR_REG_V146, /* DR_REG_PMEVTYPER5_EL0 */
DR_REG_V147, /* DR_REG_PMEVTYPER6_EL0 */
DR_REG_V148, /* DR_REG_PMEVTYPER7_EL0 */
DR_REG_V149, /* DR_REG_PMEVTYPER8_EL0 */
DR_REG_V150, /* DR_REG_PMEVTYPER9_EL0 */
DR_REG_V151, /* DR_REG_PMEVTYPER10_EL0 */
DR_REG_V152, /* DR_REG_PMEVTYPER11_EL0 */
DR_REG_V153, /* DR_REG_PMEVTYPER12_EL0 */
DR_REG_V154, /* DR_REG_PMEVTYPER13_EL0 */
DR_REG_V155, /* DR_REG_PMEVTYPER14_EL0 */
DR_REG_V156, /* DR_REG_PMEVTYPER15_EL0 */
DR_REG_V157, /* DR_REG_PMEVTYPER16_EL0 */
DR_REG_V158, /* DR_REG_PMEVTYPER17_EL0 */
DR_REG_V159, /* DR_REG_PMEVTYPER18_EL0 */
DR_REG_V160, /* DR_REG_PMEVTYPER19_EL0 */
DR_REG_V161, /* DR_REG_PMEVTYPER20_EL0 */
DR_REG_V162, /* DR_REG_PMEVTYPER21_EL0 */
DR_REG_V163, /* DR_REG_PMEVTYPER22_EL0 */
DR_REG_V164, /* DR_REG_PMEVTYPER23_EL0 */
DR_REG_V165, /* DR_REG_PMEVTYPER24_EL0 */
DR_REG_V166, /* DR_REG_PMEVTYPER25_EL0 */
DR_REG_V167, /* DR_REG_PMEVTYPER26_EL0 */
DR_REG_V168, /* DR_REG_PMEVTYPER27_EL0 */
DR_REG_V169, /* DR_REG_PMEVTYPER28_EL0 */
DR_REG_V170, /* DR_REG_PMEVTYPER29_EL0 */
DR_REG_V171, /* DR_REG_PMEVTYPER30_EL0 */
DR_REG_V172, /* DR_REG_PMCCFILTR_EL0 */
DR_REG_V173, /* DR_REG_SPSR_IRQ */
DR_REG_V174, /* DR_REG_SPSR_ABT */
DR_REG_V175, /* DR_REG_SPSR_UND */
DR_REG_V176, /* DR_REG_SPSR_FIQ */
DR_REG_V177, /* DR_REG_TPIDR_EL0 */
DR_REG_V178, /* DR_REG_TPIDRRO_EL0 */

DR_REG_V179, /* DR_REG_P0 */
DR_REG_V180, /* DR_REG_P1 */
DR_REG_V181, /* DR_REG_P2 */
DR_REG_V182, /* DR_REG_P3 */
DR_REG_V183, /* DR_REG_P4 */
DR_REG_V184, /* DR_REG_P5 */
DR_REG_V185, /* DR_REG_P6 */
DR_REG_V186, /* DR_REG_P7 */
DR_REG_V187, /* DR_REG_P8 */
DR_REG_V188, /* DR_REG_P9 */
DR_REG_V189, /* DR_REG_P10 */
DR_REG_V190, /* DR_REG_P11 */
DR_REG_V191, /* DR_REG_P12 */
DR_REG_V192, /* DR_REG_P13 */
DR_REG_V193, /* DR_REG_P14 */
DR_REG_V194, /* DR_REG_P15 */
DR_REG_V195, /* DR_REG_FFR */

DR_REG_V196, /* DR_REG_CNTVCT_EL0 */
};
/* clang-format on */

#ifdef DEBUG
Expand Down
Loading

0 comments on commit 092b4f2

Please sign in to comment.