This processor is designed using Verilog HDL language in Quartus IDE. Also, to make sure it works properly in the hardware (Altera DE1 Development board), Modelsim IDE is used to create a testbench ot test code to eliminate any bugs or potential error.
This processor is broken down into 2 sections, which are Datapath and Control Unit. Datapath is responsible for processing data input from user and generates corrrect output. Control Unit gives commands or directions for datapath to ensure specific operation is executed properly.
- Quartus IDE
- Modelsim IDE
- Altera DE1 Development board (FPGA)
This is the instruction set of the processor. Each instruction is comes with a specific operation which deals with memory address.
Here, state machine is implemented to show how the processor works. Each instruction is a state and before executes them, processor needs to fetch instructions stored in the memory and decode it.
To have a clearer view on the processor architecture, the circuit below shows the I/O of both control unit and datapath.
For specific instruction, control unit need to send sepecific signal/data bits on the data line to datapath or receive data from datapath. Therefore a control unit truth table is needed to implement the code. Our verilog code will be depending on this truth table.
We have truth table for control unit to implement the I/O signal of the control unit. Now, take a look at the datapath circuit, datapath will be more complex than control unit. Before implementing the code, we need to justify what is the components we need to use, for this datapath, we need 1 memory, 3 registers, 3 multiplexers and 2 adders. Then, we have a clearer picture of the codings.
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This processor will be finding Greatest Common Decimal of the 2 input numbers. This is the result of the testbench in modelsim below, the testbench verilog file has a _tb to indicates that is the testbench file.
