MLK-25952: drm/imx/mhdp: fix random SError when running modetest on 8QM

When running the following test on an 8QM using HDMI:

systemctl stop weston; dmesg -n 1; while true; do (sleep 5; echo) |
modetest -M imx-drm -s 148:1024x768-60.00@XR24; sleep 2; done

the following synchronous external abort will be randomly thrown,
resulting in the board freezing up:

---
SError Interrupt on CPU4, code 0xbf000002 -- SError
CPU: 4 PID: 287 Comm: cdns-mhdp-cec Tainted: G C 5.15.32-lts-next+ge8a7b095be1b #1
Hardware name: Freescale i.MX8QM MEK (DT)
pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : mhdp_cec_read+0x90/0xd0
lr : mhdp_cec_read+0x20/0xd0
sp : ffff80000c4fbde0
x29: ffff80000c4fbde0 x28: 0000000000000000 x27: 0000000000000000
x26: 0000000000000000 x25: ffff0008144d96c0 x24: ffff0008142bcdb0
x23: 0000000000033850 x22: ffff800009eab858 x21: ffff000811e98dc0
x20: ffff0008142bcdb0 x19: 0000000000000000 x18: 0000000000000001
x17: 0000000000000000 x16: 00000000000000a6 x15: 00000000000000a0
x14: 000000000000001e x13: 0000000000000001 x12: 0000000000000000
x11: 0000000000000000 x10: 0000000000000960 x9 : ffff80000c4fbcf0
x8 : ffff000811e99780 x7 : ffff0008f95e0e80 x6 : 0000000000000000
x5 : 00000000410fd080 x4 : 0000000000000000 x3 : ffff0008142bcd88
x2 : ffff000811e98dc0 x1 : 0000000000000033 x0 : ffff80000afa594c
Kernel panic - not syncing: Asynchronous SError Interrupt
CPU: 4 PID: 287 Comm: cdns-mhdp-cec Tainted: G C 5.15.32-lts-next+ge8a7b095be1b #1
Hardware name: Freescale i.MX8QM MEK (DT)
Call trace:
 dump_backtrace+0x0/0x1a0
 show_stack+0x1c/0x70
 dump_stack_lvl+0x68/0x84
 dump_stack+0x1c/0x38
 panic+0x15c/0x31c
 add_taint+0x0/0xb0
 arm64_serror_panic+0x70/0x80
 do_serror+0x5c/0x60
 el1h_64_error_handler+0x34/0x50
 el1h_64_error+0x78/0x7c
 mhdp_cec_read+0x90/0xd0
 mhdp_cec_poll_worker+0x64/0x27c
 kthread+0x154/0x160
 ret_from_fork+0x10/0x20
SMP: stopping secondary CPUs
Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP
---

The reason for the SError is because we're trying to read/write from
MHDP controller, in the HDMI CEC worker thread, while clocks are off in
the middle of a mode set pixel clock change.  The simplest solution is
to guard the pixel clock changes with the iolock mutex and all
read/writes from MHDP controller will then have to wait until the clocks
are back on.

Signed-off-by: Laurentiu Palcu <[email protected]>
Reviewed-by: Sandor Yu <[email protected]>
Acked-by: Robert Chiras <[email protected]>

drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2019-2021 NXP
+ * Copyright 2019-2022 NXP
  *
  * this program is free software; you can redistribute it and/or modify
  * it under the terms of the gnu general public license version 2 as
@@ -512,13 +512,17 @@ void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp)
 	struct imx_mhdp_device *imx_mhdp =
 				container_of(mhdp, struct imx_mhdp_device, mhdp);
 
+	mutex_lock(&mhdp->iolock);
+
 	/* set pixel clock before video mode setup */
 	imx8qm_pixel_clk_disable(imx_mhdp);
 
 	imx8qm_pixel_clk_set_rate(imx_mhdp, imx_mhdp->mhdp.mode.clock * 1000);
 
 	imx8qm_pixel_clk_enable(imx_mhdp);
 
+	mutex_unlock(&mhdp->iolock);
+
 	/* Config pixel link mux */
 	imx8qm_pixel_link_mux(imx_mhdp);
 }