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MIPS simulator, which implements reordering of DRAM requests during runtime to reduce the clock cycles during execution

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COL216 Assignment 4

Sayam Sethi 2019CS10399
Mallika Prabhakar 2019CS50440

Contents:

Files:

main.tex makefile Assignment-4.pdf MIPS_interpreter_DRAM.cpp

Test cases:

  1. lw.asm single load word operation
  2. sw.asm single store word operation
  3. lwLocate.asm multiple load words at same location
  4. swLocate.asm multiple store words at the same location
  5. size.asm a large number of commands to show max size of data structure
  6. unsafeAddress testcase with address register unsafe
  7. random.asm initial testing of overwrite
  8. random2.asm rejected DRAM testing
  9. random3.asm just a random testcase
  10. rand.asm to test reordering

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MIPS simulator, which implements reordering of DRAM requests during runtime to reduce the clock cycles during execution

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