Mechanism for general interface connections in subnetworks

[sgherbst]

Issue reported by @azaidy.

When running a subnetwork in a single RTL simulation, it should be possible to make connections between signals that are not part of standard interfaces like UMI or AXI. For distributed simulation, this is not generally possible since these signals may not be latency-insensitive, but when running in a single Verilog simulation, that is not an issue.