From 98cc556b4ebe91e4d3756314696547a1ee9fb52e Mon Sep 17 00:00:00 2001
From: Noah Moroze <noah@zeroasic.com>
Date: Sun, 9 Jul 2023 00:32:17 -0400
Subject: [PATCH] Specify FST for Verilator dump

---
 examples/umiram/test.py      | 3 ++-
 examples/umiram/testbench.sv | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/examples/umiram/test.py b/examples/umiram/test.py
index 54d0f32d..33a04c56 100755
--- a/examples/umiram/test.py
+++ b/examples/umiram/test.py
@@ -101,7 +101,8 @@ def build_testbench(fast=False):
         dut.add('option', option, EX_DIR / 'deps' / 'umi' / 'umi' / 'rtl')
 
     # Settings
-    dut.set('option', 'trace', True)  # enable VCD (TODO: FST option)
+    dut.set('option', 'trace', True)
+    dut.set('tool', 'verilator', 'task', 'compile', 'var', 'trace_type', 'fst')
 
     result = None
 
diff --git a/examples/umiram/testbench.sv b/examples/umiram/testbench.sv
index 5f5c06e0..e8d80d90 100644
--- a/examples/umiram/testbench.sv
+++ b/examples/umiram/testbench.sv
@@ -66,7 +66,7 @@ module testbench (
 
     initial begin
         if ($test$plusargs("trace")) begin
-            $dumpfile("testbench.vcd");
+            $dumpfile("testbench.fst");
             $dumpvars(0, testbench);
         end
     end