diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index da31472d87f992..f5a76bbb57937c 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -3524,6 +3524,26 @@ Silabs SiM3U Platforms: description: >- SiM3U SoCs, dts files, and related drivers. Boards based on SiM3U SoCs. +SOPHGO Platforms: + status: maintained + maintainers: + - xingrz + collaborators: + - lenghonglin + files: + - boards/common/cvi-fiptool.board.cmake + - boards/milkv/duo/ + - boards/milkv/duo256m/ + - boards/milkv/duos/ + - dts/riscv/sophgo/ + - dts/bindings/*/sophgo,* + - drivers/*/*.sophgo + - drivers/*/*_sophgo_*.c + - scripts/west_commands/runners/cvi_fiptool.py + - soc/sophgo/ + labels: + - "platform: SOPHGO" + Intel Platforms (X86): status: maintained maintainers: diff --git a/boards/common/cvi-fiptool.board.cmake b/boards/common/cvi-fiptool.board.cmake new file mode 100644 index 00000000000000..2e6a7cb568c304 --- /dev/null +++ b/boards/common/cvi-fiptool.board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(cvi-fiptool) +board_finalize_runner_args(cvi-fiptool) diff --git a/boards/milkv/duo/Kconfig.milkv_duo b/boards/milkv/duo/Kconfig.milkv_duo new file mode 100644 index 00000000000000..49741c15cde9e1 --- /dev/null +++ b/boards/milkv/duo/Kconfig.milkv_duo @@ -0,0 +1,5 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MILKV_DUO + select SOC_CV1800B diff --git a/boards/milkv/duo/board.cmake b/boards/milkv/duo/board.cmake new file mode 100644 index 00000000000000..edc7e1f1db97c4 --- /dev/null +++ b/boards/milkv/duo/board.cmake @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/cvi-fiptool.board.cmake) diff --git a/boards/milkv/duo/board.yml b/boards/milkv/duo/board.yml new file mode 100644 index 00000000000000..053ad4341dac91 --- /dev/null +++ b/boards/milkv/duo/board.yml @@ -0,0 +1,5 @@ +board: + name: milkv_duo + vendor: milkv + socs: + - name: cv1800b diff --git a/boards/milkv/duo/doc/index.rst b/boards/milkv/duo/doc/index.rst new file mode 100644 index 00000000000000..087d000c57f00a --- /dev/null +++ b/boards/milkv/duo/doc/index.rst @@ -0,0 +1,89 @@ +.. _duo: + +Milk-V Duo +########## + +Overview +******** + +See https://milkv.io/duo + +Supported Features +================== +The Milk-V Duo board configuration supports the following hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - Mailbox + - :kconfig:option:`CONFIG_MBOX` + - :dtcompatible:`sophgo,cvi-mailbox` + * - Pin controller + - :kconfig:option:`CONFIG_PINCTRL` + - :dtcompatible:`sophgo,cvi-pinctrl` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`snps,designware-gpio` + * - PWM + - :kconfig:option:`CONFIG_PWM` + - :dtcompatible:`sophgo,cvi-pwm` + * - UART + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`ns16550` + * - PLIC + - N/A + - :dtcompatible:`sifive,plic-1.0.0` + * - SysTick + - N/A + - :dtcompatible:`thead,machine-timer` + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/milkv/duo/milkv_duo_defconfig`. + +Programming and Debugging +************************* + +Prepare a TF card and follow the instructions in the `official SDK`_ to build +and flash the image. + +After that, you will get a ``fip.bin`` file at the root of the TF card, where +the RTOS image is packed. + +The following steps demonstrate how to build the blinky sample and update the +``fip.bin`` file on the TF card. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: milkv_duo + :goals: build flash + :flash-args: --fiptool /path/to/duo-buildroot-sdk/fsbl/plat/cv180x/fiptool.py --fip-bin /path/to/tfcard/fip.bin + +Eject the TF card and insert it into the board. Power on the board and you will +see the LED blinking. + +.. note:: + + Notes for the official buildroot SDK + + 1. The Linux running on the big core uses UART0 (GP12/GP13) for the console, + while to avoid conflict, the Zephyr application (in the default board + configuration) uses UART1 (GP0/GP1). + 2. Pin multiplexing can be handled either by U-Boot or Zephyr. To utilize + Zephyr's pin multiplexing, enable :kconfig:option:`CONFIG_PINCTRL` and + recompile U-Boot without the `PINMUX configs`_. Note that U-Boot boots + several seconds after Zephyr. + 3. By default, the Linux running on the big core will blink the LED on the + board. To demonstrate Zephyr (specifically, the ``samples/basic/blinky`` + sample), you should remove the script from the Linux filesystem located at + ``/mnt/system/blink.sh``. + +.. _official SDK: + https://github.com/milkv-duo/duo-buildroot-sdk + +.. _PINMUX configs: + https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv180x/cv1800b_milkv_duo_sd/u-boot/cvi_board_init.c diff --git a/boards/milkv/duo/milkv_duo-pinctrl.dtsi b/boards/milkv/duo/milkv_duo-pinctrl.dtsi new file mode 100644 index 00000000000000..20974fa7cc44f4 --- /dev/null +++ b/boards/milkv/duo/milkv_duo-pinctrl.dtsi @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2023-2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart1_default: uart1_default { + group1 { + pinmux = , /* GP0 */ + ; /* GP1 */ + }; + }; +}; diff --git a/boards/milkv/duo/milkv_duo.dts b/boards/milkv/duo/milkv_duo.dts new file mode 100644 index 00000000000000..27c6bc7059d7cc --- /dev/null +++ b/boards/milkv/duo/milkv_duo.dts @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2023-2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "milkv_duo-pinctrl.dtsi" + +/ { + model = "Milk-V Duo"; + compatible = "milkv,duo"; + + chosen { + zephyr,sram = &sram; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; + + aliases { + led0 = &led; + }; + + leds { + compatible = "gpio-leds"; + + led: led { + gpios = <&gpioc 24 GPIO_ACTIVE_HIGH>; + }; + }; + + soc { + /* + * Memory region reserved for the RTOS core. + * + * Keep in sync with FREERTOS_ADDR and FREERTOS_SIZE in + * build/boards/cv180x/cv1800b_milkv_duo_sd/memmap.py + * + * see: https://github.com/milkv-duo/duo-buildroot-sdk + */ + sram: memory@83f40000 { + compatible = "mmio-sram"; + reg = <0x83f40000 DT_SIZE_K(768)>; + }; + }; +}; + +&gpioc { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + current-speed = <115200>; +}; diff --git a/boards/milkv/duo/milkv_duo.yaml b/boards/milkv/duo/milkv_duo.yaml new file mode 100644 index 00000000000000..2164f1a46ea0b8 --- /dev/null +++ b/boards/milkv/duo/milkv_duo.yaml @@ -0,0 +1,14 @@ +identifier: milkv_duo +name: Milk-V Duo +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - clock + - gpio + - interrupt-controller + - mailbox + - pinctrl + - pwm + - serial diff --git a/boards/milkv/duo/milkv_duo_defconfig b/boards/milkv/duo/milkv_duo_defconfig new file mode 100644 index 00000000000000..96484b35364655 --- /dev/null +++ b/boards/milkv/duo/milkv_duo_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/milkv/duo256m/Kconfig.milkv_duo256m b/boards/milkv/duo256m/Kconfig.milkv_duo256m new file mode 100644 index 00000000000000..2f330cd926a4a2 --- /dev/null +++ b/boards/milkv/duo256m/Kconfig.milkv_duo256m @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MILKV_DUO256M + select SOC_SG2002 diff --git a/boards/milkv/duo256m/board.cmake b/boards/milkv/duo256m/board.cmake new file mode 100644 index 00000000000000..edc7e1f1db97c4 --- /dev/null +++ b/boards/milkv/duo256m/board.cmake @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/cvi-fiptool.board.cmake) diff --git a/boards/milkv/duo256m/board.yml b/boards/milkv/duo256m/board.yml new file mode 100644 index 00000000000000..5edb5586ad45e7 --- /dev/null +++ b/boards/milkv/duo256m/board.yml @@ -0,0 +1,5 @@ +board: + name: milkv_duo256m + vendor: milkv + socs: + - name: sg2002 diff --git a/boards/milkv/duo256m/doc/index.rst b/boards/milkv/duo256m/doc/index.rst new file mode 100644 index 00000000000000..2dc1dd88c1193b --- /dev/null +++ b/boards/milkv/duo256m/doc/index.rst @@ -0,0 +1,89 @@ +.. _duo256m: + +Milk-V Duo 256M +############### + +Overview +******** + +See https://milkv.io/duo + +Supported Features +================== +The Milk-V Duo 256M board configuration supports the following hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - Mailbox + - :kconfig:option:`CONFIG_MBOX` + - :dtcompatible:`sophgo,cvi-mailbox` + * - Pin controller + - :kconfig:option:`CONFIG_PINCTRL` + - :dtcompatible:`sophgo,cvi-pinctrl` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`snps,designware-gpio` + * - PWM + - :kconfig:option:`CONFIG_PWM` + - :dtcompatible:`sophgo,cvi-pwm` + * - UART + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`ns16550` + * - PLIC + - N/A + - :dtcompatible:`sifive,plic-1.0.0` + * - SysTick + - N/A + - :dtcompatible:`thead,machine-timer` + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/milkv/duo256m/milkv_duo256m_defconfig`. + +Programming and Debugging +************************* + +Prepare a TF card and follow the instructions in the `official SDK`_ to build +and flash the image. + +After that, you will get a ``fip.bin`` file at the root of the TF card, where +the RTOS image is packed. + +The following steps demonstrate how to build the blinky sample and update the +``fip.bin`` file on the TF card. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: milkv_duo256m + :goals: build flash + :flash-args: --fiptool /path/to/duo-buildroot-sdk/fsbl/plat/cv181x/fiptool.py --fip-bin /path/to/tfcard/fip.bin + +Eject the TF card and insert it into the board. Power on the board and you will +see the LED blinking. + +.. note:: + + Notes for the official buildroot SDK + + 1. The Linux running on the big core uses UART0 (GP12/GP13) for the console, + while to avoid conflict, the Zephyr application (in the default board + configuration) uses UART1 (GP0/GP1). + 2. Pin multiplexing can be handled either by U-Boot or Zephyr. To utilize + Zephyr's pin multiplexing, enable :kconfig:option:`CONFIG_PINCTRL` and + recompile U-Boot without the `PINMUX configs`_. Note that U-Boot boots + several seconds after Zephyr. + 3. By default, the Linux running on the big core will blink the LED on the + board. To demonstrate Zephyr (specifically, the ``samples/basic/blinky`` + sample), you should remove the script from the Linux filesystem located at + ``/mnt/system/blink.sh``. + +.. _official SDK: + https://github.com/milkv-duo/duo-buildroot-sdk + +.. _PINMUX configs: + https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv181x/cv1812cp_milkv_duo256m_sd/u-boot/cvi_board_init.c diff --git a/boards/milkv/duo256m/milkv_duo256m-pinctrl.dtsi b/boards/milkv/duo256m/milkv_duo256m-pinctrl.dtsi new file mode 100644 index 00000000000000..ff9e012917ce2f --- /dev/null +++ b/boards/milkv/duo256m/milkv_duo256m-pinctrl.dtsi @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart1_default: uart1_default { + group1 { + pinmux = , /* GP0 */ + ; /* GP1 */ + }; + }; +}; diff --git a/boards/milkv/duo256m/milkv_duo256m.dts b/boards/milkv/duo256m/milkv_duo256m.dts new file mode 100644 index 00000000000000..6e9d34df97d91f --- /dev/null +++ b/boards/milkv/duo256m/milkv_duo256m.dts @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "milkv_duo256m-pinctrl.dtsi" + +/ { + model = "Milk-V Duo 256M"; + compatible = "milkv,duo-256m"; + + chosen { + zephyr,sram = &sram; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; + + aliases { + led0 = &led; + }; + + leds { + compatible = "gpio-leds"; + + led: led { + gpios = <&pwr_gpio 2 GPIO_ACTIVE_HIGH>; + }; + }; + + soc { + /* + * Memory region reserved for the RTOS core. + * + * Keep in sync with FREERTOS_ADDR and FREERTOS_SIZE in + * build/boards/cv181x/cv1812cp_milkv_duo256m_sd/memmap.py + * + * see: https://github.com/milkv-duo/duo-buildroot-sdk + */ + sram: memory@8fe00000 { + compatible = "mmio-sram"; + reg = <0x8fe00000 DT_SIZE_M(2)>; + }; + }; +}; + +&pwr_gpio { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + current-speed = <115200>; +}; diff --git a/boards/milkv/duo256m/milkv_duo256m.yaml b/boards/milkv/duo256m/milkv_duo256m.yaml new file mode 100644 index 00000000000000..1d9822387a81e4 --- /dev/null +++ b/boards/milkv/duo256m/milkv_duo256m.yaml @@ -0,0 +1,14 @@ +identifier: milkv_duo256m +name: Milk-V Duo 256M +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - clock + - gpio + - interrupt-controller + - mailbox + - pinctrl + - pwm + - serial diff --git a/boards/milkv/duo256m/milkv_duo256m_defconfig b/boards/milkv/duo256m/milkv_duo256m_defconfig new file mode 100644 index 00000000000000..32cc568d8f7e07 --- /dev/null +++ b/boards/milkv/duo256m/milkv_duo256m_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/milkv/duos/Kconfig.milkv_duos b/boards/milkv/duos/Kconfig.milkv_duos new file mode 100644 index 00000000000000..1821efb2caf793 --- /dev/null +++ b/boards/milkv/duos/Kconfig.milkv_duos @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MILKV_DUOS + select SOC_SG2000 diff --git a/boards/milkv/duos/board.cmake b/boards/milkv/duos/board.cmake new file mode 100644 index 00000000000000..edc7e1f1db97c4 --- /dev/null +++ b/boards/milkv/duos/board.cmake @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/cvi-fiptool.board.cmake) diff --git a/boards/milkv/duos/board.yml b/boards/milkv/duos/board.yml new file mode 100644 index 00000000000000..7870f9ec82f182 --- /dev/null +++ b/boards/milkv/duos/board.yml @@ -0,0 +1,5 @@ +board: + name: milkv_duos + vendor: milkv + socs: + - name: sg2000 diff --git a/boards/milkv/duos/doc/index.rst b/boards/milkv/duos/doc/index.rst new file mode 100644 index 00000000000000..c4d4a9c309100d --- /dev/null +++ b/boards/milkv/duos/doc/index.rst @@ -0,0 +1,85 @@ +.. _duos: + +Milk-V Duo S +############ + +Overview +******** + +See https://milkv.io/duo-s + +Supported Features +================== +The Milk-V Duo S board configuration supports the following hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - Mailbox + - :kconfig:option:`CONFIG_MBOX` + - :dtcompatible:`sophgo,cvi-mailbox` + * - Pin controller + - :kconfig:option:`CONFIG_PINCTRL` + - :dtcompatible:`sophgo,cvi-pinctrl` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`snps,designware-gpio` + * - PWM + - :kconfig:option:`CONFIG_PWM` + - :dtcompatible:`sophgo,cvi-pwm` + * - UART + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`ns16550` + * - PLIC + - N/A + - :dtcompatible:`sifive,plic-1.0.0` + * - SysTick + - N/A + - :dtcompatible:`thead,machine-timer` + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/milkv/duos/milkv_duos_defconfig`. + +Programming and Debugging +************************* + +Prepare a TF card and follow the instructions in the `official SDK`_ to build +and flash the image. + +After that, you will get a ``fip.bin`` file at the root of the TF card, where +the RTOS image is packed. + +The following steps demonstrate how to build the blinky sample and update the +``fip.bin`` file on the TF card. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: milkv_duos + :goals: build flash + :flash-args: --fiptool /path/to/duo-buildroot-sdk/fsbl/plat/cv181x/fiptool.py --fip-bin /path/to/tfcard/fip.bin + +Eject the TF card and insert it into the board. Power on the board and you will +see the LED blinking. + +.. note:: + + Notes for the official buildroot SDK + + 1. The Linux running on the big core uses UART0 (A16/A17) for the console, + while to avoid conflict, the Zephyr application (in the default board + configuration) uses UART2 (A19/A18). + 2. Pin multiplexing can be handled either by U-Boot or Zephyr. To utilize + Zephyr's pin multiplexing, enable :kconfig:option:`CONFIG_PINCTRL` and + recompile U-Boot without the `PINMUX configs`_. Note that U-Boot boots + several seconds after Zephyr. + +.. _official SDK: + https://github.com/milkv-duo/duo-buildroot-sdk + +.. _PINMUX configs: + https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv181x/cv1813h_milkv_duos_sd/u-boot/cvi_board_init.c diff --git a/boards/milkv/duos/milkv_duos-pinctrl.dtsi b/boards/milkv/duos/milkv_duos-pinctrl.dtsi new file mode 100644 index 00000000000000..250b21f795bf15 --- /dev/null +++ b/boards/milkv/duos/milkv_duos-pinctrl.dtsi @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart1_default: uart1_default { + group1 { + pinmux = , /* A19 */ + ; /* A18 */ + }; + }; +}; diff --git a/boards/milkv/duos/milkv_duos.dts b/boards/milkv/duos/milkv_duos.dts new file mode 100644 index 00000000000000..b55d26f63e98dc --- /dev/null +++ b/boards/milkv/duos/milkv_duos.dts @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include + +#include "milkv_duos-pinctrl.dtsi" + +/ { + model = "Milk-V Duo S"; + compatible = "milkv,duo-s"; + + chosen { + zephyr,sram = &sram; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; + + aliases { + led0 = &led; + sw0 = &button; + }; + + leds { + compatible = "gpio-leds"; + + led: led { + gpios = <&gpioa 29 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + button: button { + label = "RECOVERY"; + gpios = <&gpiob 4 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + soc { + /* + * Memory region reserved for the RTOS core. + * + * Keep in sync with FREERTOS_ADDR and FREERTOS_SIZE in + * build/boards/cv181x/cv1813h_milkv_duos_sd/memmap.py + * + * see: https://github.com/milkv-duo/duo-buildroot-sdk + */ + sram: memory@9fe00000 { + compatible = "mmio-sram"; + reg = <0x9fe00000 DT_SIZE_M(2)>; + }; + }; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + current-speed = <115200>; +}; diff --git a/boards/milkv/duos/milkv_duos.yaml b/boards/milkv/duos/milkv_duos.yaml new file mode 100644 index 00000000000000..05fb38f1803f66 --- /dev/null +++ b/boards/milkv/duos/milkv_duos.yaml @@ -0,0 +1,14 @@ +identifier: milkv_duos +name: Milk-V Duo S +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - clock + - gpio + - interrupt-controller + - mailbox + - pinctrl + - pwm + - serial diff --git a/boards/milkv/duos/milkv_duos_defconfig b/boards/milkv/duos/milkv_duos_defconfig new file mode 100644 index 00000000000000..32cc568d8f7e07 --- /dev/null +++ b/boards/milkv/duos/milkv_duos_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +CONFIG_GPIO=y +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/milkv/index.rst b/boards/milkv/index.rst new file mode 100644 index 00000000000000..6fc792313db2a7 --- /dev/null +++ b/boards/milkv/index.rst @@ -0,0 +1,10 @@ +.. _boards-milkv: + +Milk-V +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/drivers/mbox/CMakeLists.txt b/drivers/mbox/CMakeLists.txt index 4b594da6bfaf96..09bd22813b8243 100644 --- a/drivers/mbox/CMakeLists.txt +++ b/drivers/mbox/CMakeLists.txt @@ -18,3 +18,4 @@ zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_VEVIF_EVENT_TX mbox_nrf_vevif_event zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_BELLBOARD_RX mbox_nrf_bellboard_rx.c) zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_BELLBOARD_TX mbox_nrf_bellboard_tx.c) zephyr_library_sources_ifdef(CONFIG_MBOX_STM32_HSEM mbox_stm32_hsem.c) +zephyr_library_sources_ifdef(CONFIG_MBOX_SOPHGO_CVI mbox_sophgo_cvi.c) diff --git a/drivers/mbox/Kconfig b/drivers/mbox/Kconfig index 2e598b4a019066..111e3166dfce6e 100644 --- a/drivers/mbox/Kconfig +++ b/drivers/mbox/Kconfig @@ -22,6 +22,7 @@ source "drivers/mbox/Kconfig.nrf_vevif_event" source "drivers/mbox/Kconfig.nrf_bellboard" source "drivers/mbox/Kconfig.stm32_hsem" source "drivers/mbox/Kconfig.esp32" +source "drivers/mbox/Kconfig.sophgo" config MBOX_INIT_PRIORITY diff --git a/drivers/mbox/Kconfig.sophgo b/drivers/mbox/Kconfig.sophgo new file mode 100644 index 00000000000000..ade1e085fd8e72 --- /dev/null +++ b/drivers/mbox/Kconfig.sophgo @@ -0,0 +1,9 @@ +# Copyright (c) 2024 honglin leng +# SPDX-License-Identifier: Apache-2.0 + +config MBOX_SOPHGO_CVI + bool "SOPHGO CVI series Mailbox controller" + default y + depends on DT_HAS_SOPHGO_CVI_MAILBOX_ENABLED + help + Enable driver for the SOPHGO CVI series Mailbox. diff --git a/drivers/mbox/mbox_sophgo_cvi.c b/drivers/mbox/mbox_sophgo_cvi.c new file mode 100644 index 00000000000000..942e062d8a9276 --- /dev/null +++ b/drivers/mbox/mbox_sophgo_cvi.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2024 honglin leng + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#define DT_DRV_COMPAT sophgo_cvi_mailbox + +#define MBOX_BASE DT_INST_REG_ADDR(0) +#define MBOX_TX_CPU DT_INST_PROP(0, tx_cpu) +#define MBOX_RX_CPU DT_INST_PROP(0, rx_cpu) + +#define MBOX_INT_ENABLE(cpu) (MBOX_BASE + 0x00 + (0x04 * cpu)) +#define MBOX_INT_CLEAR(cpu) (MBOX_BASE + 0x10 + (0x10 * cpu)) +#define MBOX_INT_DONE(cpu) (MBOX_BASE + 0x18 + (0x10 * cpu)) +#define MBOX_INT_TRIGER (MBOX_BASE + 0x60) +#define MBOX_BUFFER (MBOX_BASE + 0x400) + +#define MBOX_MAX_NUM 8 + +struct mbox_cvi_data { + mbox_callback_t cb[MBOX_MAX_NUM]; + void *user_data[MBOX_MAX_NUM]; +}; + +static struct mbox_cvi_data mbox_data; + +static void mbox_isr(const struct device *dev) +{ + ARG_UNUSED(dev); + + uint8_t set_val; + uint8_t valid_val; + uint8_t tmp_valid_val; + struct mbox_msg msg; + + set_val = sys_read8(MBOX_INT_DONE(MBOX_RX_CPU)); + if (set_val) { + for (int i = 0; i < MBOX_MAX_NUM; i++) { + valid_val = set_val & BIT(i); + if (valid_val) { + msg.data = (const unsigned long *)MBOX_BUFFER + i; + sys_write8(valid_val, MBOX_INT_CLEAR(MBOX_RX_CPU)); + tmp_valid_val = sys_read8(MBOX_INT_ENABLE(MBOX_RX_CPU)); + tmp_valid_val &= ~valid_val; + sys_write8(tmp_valid_val, MBOX_INT_ENABLE(MBOX_RX_CPU)); + if (mbox_data.cb[i] != NULL) { + mbox_data.cb[i](dev, i, mbox_data.user_data[i], &msg); + *(unsigned long *)msg.data = 0x0; + } + } + } + } +} + +static int mbox_cvi_send(const struct device *dev, uint32_t channel, const struct mbox_msg *msg) +{ + uint8_t tmp_mbox_info; + + ARG_UNUSED(dev); + + memcpy((unsigned long *)MBOX_BUFFER + channel, msg->data, msg->size); + sys_write8(BIT(channel), MBOX_INT_CLEAR(MBOX_TX_CPU)); + tmp_mbox_info = sys_read8(MBOX_INT_ENABLE(MBOX_TX_CPU)); + tmp_mbox_info |= BIT(channel); + sys_write8(tmp_mbox_info, MBOX_INT_ENABLE(MBOX_TX_CPU)); + sys_write8(BIT(channel), MBOX_INT_TRIGER); + + return 0; +} + +static int mbox_cvi_register_callback(const struct device *dev, uint32_t channel, + mbox_callback_t cb, void *user_data) +{ + ARG_UNUSED(dev); + + if (channel >= MBOX_MAX_NUM) { + return -EINVAL; + } + + mbox_data.cb[channel] = cb; + mbox_data.user_data[channel] = user_data; + + return 0; +} + +static int mbox_cvi_mtu_get(const struct device *dev) +{ + ARG_UNUSED(dev); + + /* We only support signalling */ + return 0; +} + +static uint32_t mbox_cvi_max_channels_get(const struct device *dev) +{ + ARG_UNUSED(dev); + + return MBOX_MAX_NUM; +} + +static int mbox_cvi_set_enabled(const struct device *dev, uint32_t channel, bool enable) +{ + ARG_UNUSED(dev); + ARG_UNUSED(channel); + ARG_UNUSED(enable); + + return 0; +} + +static int mbox_cvi_init(const struct device *dev) +{ + ARG_UNUSED(dev); + + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), mbox_isr, DEVICE_DT_INST_GET(0), 0); + irq_enable(DT_INST_IRQN(0)); + + return 0; +} + +static const struct mbox_driver_api mbox_cvi_driver_api = { + .send = mbox_cvi_send, + .register_callback = mbox_cvi_register_callback, + .mtu_get = mbox_cvi_mtu_get, + .max_channels_get = mbox_cvi_max_channels_get, + .set_enabled = mbox_cvi_set_enabled, +}; + +DEVICE_DT_INST_DEFINE(0, mbox_cvi_init, NULL, NULL, NULL, POST_KERNEL, CONFIG_MBOX_INIT_PRIORITY, + &mbox_cvi_driver_api); diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 5c99dd82e8fcc7..8b6b8c51f38868 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -39,5 +39,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_ENE_KB1200 pinctrl_ene_kb1200.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCU pinctrl_imx_scu.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_MAX32 pinctrl_max32.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCMI pinctrl_imx_scmi.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_SOPHGO_CVI pinctrl_sophgo_cvi.c) add_subdirectory(renesas) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b919fa0f169b00..d4d9b05310d9ad 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -66,6 +66,7 @@ source "drivers/pinctrl/Kconfig.mci_io_mux" source "drivers/pinctrl/Kconfig.ene" source "drivers/pinctrl/Kconfig.zynqmp" source "drivers/pinctrl/Kconfig.max32" +source "drivers/pinctrl/Kconfig.sophgo" rsource "renesas/Kconfig" diff --git a/drivers/pinctrl/Kconfig.sophgo b/drivers/pinctrl/Kconfig.sophgo new file mode 100644 index 00000000000000..96a4205642f3b5 --- /dev/null +++ b/drivers/pinctrl/Kconfig.sophgo @@ -0,0 +1,9 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_SOPHGO_CVI + bool "SOPHGO CVI series pin controller driver" + default y + depends on DT_HAS_SOPHGO_CVI_PINCTRL_ENABLED + help + Enables support for the SOPHGO CVI series pin controller. diff --git a/drivers/pinctrl/pinctrl_sophgo_cvi.c b/drivers/pinctrl/pinctrl_sophgo_cvi.c new file mode 100644 index 00000000000000..80365071bb48bf --- /dev/null +++ b/drivers/pinctrl/pinctrl_sophgo_cvi.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2023-2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT sophgo_cvi_pinctrl + +#include +#include +#include + +#define PINCTRL_BASE DT_INST_REG_ADDR(0) + +#define PINCTRL_FMUX(n) (0x00 + (n) * 4) + +#define FMUX_MASK BIT_MASK(3) + +static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) +{ + uint32_t regval; + + regval = sys_read32(PINCTRL_BASE + PINCTRL_FMUX(pin->fmux_idx)); + regval &= ~FMUX_MASK; + regval |= pin->fmux_sel; + sys_write32(regval, PINCTRL_BASE + PINCTRL_FMUX(pin->fmux_idx)); +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + ARG_UNUSED(reg); + + for (uint8_t i = 0; i < pin_cnt; i++) { + pinctrl_configure_pin(&pins[i]); + } + + return 0; +} diff --git a/drivers/pwm/CMakeLists.txt b/drivers/pwm/CMakeLists.txt index 3a6eef01236213..c376056a27e413 100644 --- a/drivers/pwm/CMakeLists.txt +++ b/drivers/pwm/CMakeLists.txt @@ -43,6 +43,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_NUMAKER pwm_numaker.c) zephyr_library_sources_ifdef(CONFIG_PWM_NXP_FLEXIO pwm_nxp_flexio.c) zephyr_library_sources_ifdef(CONFIG_PWM_NXP_S32_EMIOS pwm_nxp_s32_emios.c) zephyr_library_sources_ifdef(CONFIG_PWM_ENE_KB1200 pwm_ene_kb1200.c) +zephyr_library_sources_ifdef(CONFIG_PWM_SOPHGO_CVI pwm_sophgo_cvi.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE pwm_handlers.c) zephyr_library_sources_ifdef(CONFIG_PWM_CAPTURE pwm_capture.c) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 002ff4dd2dbeb5..b196475e8add61 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -106,4 +106,6 @@ source "drivers/pwm/Kconfig.nxp_flexio" source "drivers/pwm/Kconfig.ene" +source "drivers/pwm/Kconfig.sophgo" + endif # PWM diff --git a/drivers/pwm/Kconfig.sophgo b/drivers/pwm/Kconfig.sophgo new file mode 100644 index 00000000000000..57f31135deffec --- /dev/null +++ b/drivers/pwm/Kconfig.sophgo @@ -0,0 +1,9 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +config PWM_SOPHGO_CVI + bool "SOPHGO CVI series PWM driver" + default y + depends on DT_HAS_SOPHGO_CVI_PWM_ENABLED + help + Enables support for the SOPHGO CVI series PWM. diff --git a/drivers/pwm/pwm_sophgo_cvi.c b/drivers/pwm/pwm_sophgo_cvi.c new file mode 100644 index 00000000000000..99c44cbeca9100 --- /dev/null +++ b/drivers/pwm/pwm_sophgo_cvi.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023-2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT sophgo_cvi_pwm + +#include +#include +#include +#if defined(CONFIG_PINCTRL) +#include +#endif /* CONFIG_PINCTRL */ + +#define HLPERIOD(base, n) (base + 0x000 + (n) * 8) +#define PERIOD(base, n) (base + 0x004 + (n) * 8) +#define PWMCONFIG(base) (base + 0x040) +#define PWMSTART(base) (base + 0x044) +#define PWMDONE(base) (base + 0x048) +#define PWMUPDATE(base) (base + 0x04c) +#define PCOUNT(base, n) (base + 0x050 + (n) * 4) +#define PULSECOUNT(base, n) (base + 0x060 + (n) * 4) +#define SHIFTCOUNT(base, n) (base + 0x080 + (n) * 4) +#define SHIFTSTART(base) (base + 0x090) +#define PWM_OE(base) (base + 0x0d0) + +/* PWMCONFIG */ +#define CFG_POLARITY(n) BIT(n + 0) +#define CFG_PWMMODE(n) BIT(n + 8) +#define CFG_SHIFTMODE BIT(16) + +#define PWM_CH_MAX 4 + +struct pwm_cvi_config { + mm_reg_t base; + uint32_t clk_pwm; +#if defined(CONFIG_PINCTRL) + const struct pinctrl_dev_config *pcfg; +#endif /* CONFIG_PINCTRL */ +}; + +static int pwm_cvi_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles, + uint32_t pulse_cycles, pwm_flags_t flags) +{ + const struct pwm_cvi_config *cfg = dev->config; + uint32_t regval; + + if (channel > PWM_CH_MAX) { + return -EINVAL; + } + + if (period_cycles > cfg->clk_pwm) { + return -EINVAL; + } + + if (pulse_cycles >= period_cycles) { + pulse_cycles = period_cycles - 1; + } + + /* Configure output */ + regval = sys_read32(PWM_OE(cfg->base)); + regval |= BIT(channel); + sys_write32(regval, PWM_OE(cfg->base)); + + /* Set polarity and mode */ + regval = sys_read32(PWMCONFIG(cfg->base)); + if (flags & PWM_POLARITY_INVERTED) { + regval &= ~CFG_POLARITY(channel); /* active low */ + } else { + regval |= CFG_POLARITY(channel); /* active high */ + } + regval &= ~CFG_PWMMODE(channel); /* continuous mode */ + sys_write32(regval, PWMCONFIG(cfg->base)); + + /* Set period and pulse */ + sys_write32(period_cycles, PERIOD(cfg->base, channel)); + sys_write32(pulse_cycles, HLPERIOD(cfg->base, channel)); + + if (sys_read32(PWMSTART(cfg->base)) & BIT(channel)) { + /* Update channel */ + regval = sys_read32(PWMUPDATE(cfg->base)); + regval |= BIT(channel); + sys_write32(regval, PWMUPDATE(cfg->base)); + regval &= ~BIT(channel); + sys_write32(regval, PWMUPDATE(cfg->base)); + } else { + /* Start channel */ + regval = sys_read32(PWMSTART(cfg->base)); + regval &= ~BIT(channel); + sys_write32(regval, PWMSTART(cfg->base)); + regval |= BIT(channel); + sys_write32(regval, PWMSTART(cfg->base)); + } + + return 0; +} + +static int pwm_cvi_get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles) +{ + const struct pwm_cvi_config *cfg = dev->config; + + if (channel > PWM_CH_MAX) { + return -EINVAL; + } + + *cycles = cfg->clk_pwm; + + return 0; +} + +static int pwm_cvi_init(const struct device *dev) +{ +#if defined(CONFIG_PINCTRL) + const struct pwm_cvi_config *cfg = dev->config; + int ret; + + ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); + if (ret < 0) { + return ret; + } +#endif /* CONFIG_PINCTRL */ + + return 0; +} + +static const struct pwm_driver_api pwm_cvi_api = { + .set_cycles = pwm_cvi_set_cycles, + .get_cycles_per_sec = pwm_cvi_get_cycles_per_sec, +}; + +#define PWM_CVI_INST(n) \ + IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_INST_DEFINE(n);)) \ + \ + static const struct pwm_cvi_config pwm_cvi_cfg_##n = { \ + .base = DT_INST_REG_ADDR(n), \ + .clk_pwm = DT_INST_PROP(n, clock_frequency), \ + IF_ENABLED(CONFIG_PINCTRL, (.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),)) \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, &pwm_cvi_init, NULL, NULL, &pwm_cvi_cfg_##n, PRE_KERNEL_1, \ + CONFIG_PWM_INIT_PRIORITY, &pwm_cvi_api); + +DT_INST_FOREACH_STATUS_OKAY(PWM_CVI_INST) diff --git a/drivers/timer/Kconfig.riscv_machine b/drivers/timer/Kconfig.riscv_machine index efbd4d322f731c..47157d300b157a 100644 --- a/drivers/timer/Kconfig.riscv_machine +++ b/drivers/timer/Kconfig.riscv_machine @@ -12,7 +12,8 @@ config RISCV_MACHINE_TIMER DT_HAS_SIFIVE_CLINT0_ENABLED || \ DT_HAS_TELINK_MACHINE_TIMER_ENABLED || \ DT_HAS_LOWRISC_MACHINE_TIMER_ENABLED || \ - DT_HAS_NIOSV_MACHINE_TIMER_ENABLED + DT_HAS_NIOSV_MACHINE_TIMER_ENABLED || \ + DT_HAS_THEAD_MACHINE_TIMER_ENABLED select TICKLESS_CAPABLE select TIMER_HAS_64BIT_CYCLE_COUNTER help diff --git a/drivers/timer/riscv_machine_timer.c b/drivers/timer/riscv_machine_timer.c index 36e29c6aadb318..84e6ac577fff09 100644 --- a/drivers/timer/riscv_machine_timer.c +++ b/drivers/timer/riscv_machine_timer.c @@ -71,11 +71,23 @@ #define MTIME_REG (DT_INST_REG_ADDR_U64(0) + 8) #define MTIMECMP_REG (DT_INST_REG_ADDR_U64(0) + 16) #define TIMER_IRQN DT_INST_IRQN(0) +/* thead,machine-timer */ +#elif DT_HAS_COMPAT_STATUS_OKAY(thead_machine_timer) +#define DT_DRV_COMPAT thead_machine_timer +#define MTIMER_REQUIRES_32BIT_ACCESS +#define MTIMER_READ_TIME_CSR + +#define MTIMECMP_REG (DT_INST_REG_ADDR(0) + 0x4000U) +#define TIMER_IRQN DT_INST_IRQN(0) #endif #define CYC_PER_TICK (uint32_t)(sys_clock_hw_cycles_per_sec() \ / CONFIG_SYS_CLOCK_TICKS_PER_SEC) +#if defined(CONFIG_64BIT) && !defined(MTIMER_REQUIRES_32BIT_ACCESS) +#define MTIMER_64BIT +#endif + /* the unsigned long cast limits divisions to native CPU register width */ #define cycle_diff_t unsigned long #define CYCLE_DIFF_MAX (~(cycle_diff_t)0) @@ -121,7 +133,7 @@ static uintptr_t get_hart_mtimecmp(void) static void set_mtimecmp(uint64_t time) { -#ifdef CONFIG_64BIT +#ifdef MTIMER_64BIT *(volatile uint64_t *)get_hart_mtimecmp() = time; #else volatile uint32_t *r = (uint32_t *)get_hart_mtimecmp(); @@ -148,7 +160,9 @@ static void set_divider(void) static uint64_t mtime(void) { -#ifdef CONFIG_64BIT +#if defined(MTIMER_READ_TIME_CSR) + return csr_read(time); +#elif defined(MTIMER_64BIT) return *(volatile uint64_t *)MTIME_REG; #else volatile uint32_t *r = (uint32_t *)MTIME_REG; diff --git a/dts/bindings/cpu/thead,c906.yaml b/dts/bindings/cpu/thead,c906.yaml new file mode 100644 index 00000000000000..02464bd89dca26 --- /dev/null +++ b/dts/bindings/cpu/thead,c906.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +description: T-Head C906 RISC-V CPU + +compatible: "thead,c906" + +include: riscv,cpus.yaml diff --git a/dts/bindings/mbox/sophgo,cvi-mailbox.yaml b/dts/bindings/mbox/sophgo,cvi-mailbox.yaml new file mode 100644 index 00000000000000..d8e74a3498ae67 --- /dev/null +++ b/dts/bindings/mbox/sophgo,cvi-mailbox.yaml @@ -0,0 +1,38 @@ +# Copyright (c) 2024 honglin leng +# SPDX-License-Identifier: Apache-2.0 + +description: SOPHGO CVI series Mailbox controller + +compatible: "sophgo,cvi-mailbox" + +include: [base.yaml, mailbox-controller.yaml] + +properties: + reg: + required: true + + interrupts: + required: true + + channel-max: + type: int + required: true + description: Supported channels max + + rx-cpu: + type: int + enum: [1, 2, 3, 4] + description: | + Receiver CPU Index. + + tx-cpu: + type: int + enum: [1, 2, 3, 4] + description: | + Sender CPU Index.The CVI platform has a total of 4 CPUs, each with its own + mailbox. + + The mailbox controller can be used to send messages between CPUs. + +mbox-cells: + - channel diff --git a/dts/bindings/pinctrl/sophgo,cvi-pinctrl.yaml b/dts/bindings/pinctrl/sophgo,cvi-pinctrl.yaml new file mode 100644 index 00000000000000..2cc8cf9b801003 --- /dev/null +++ b/dts/bindings/pinctrl/sophgo,cvi-pinctrl.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +description: SOPHGO CVI series pin controller driver + +compatible: "sophgo,cvi-pinctrl" + +include: base.yaml + +child-binding: + description: CVI pinmux group + + child-binding: + properties: + pinmux: + required: true + type: array diff --git a/dts/bindings/pwm/sophgo,cvi-pwm.yaml b/dts/bindings/pwm/sophgo,cvi-pwm.yaml new file mode 100644 index 00000000000000..a4d38acefcd52d --- /dev/null +++ b/dts/bindings/pwm/sophgo,cvi-pwm.yaml @@ -0,0 +1,27 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +description: SOPHGO CVI series PWM + +compatible: "sophgo,cvi-pwm" + +include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml] + +properties: + clock-frequency: + type: int + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true + + "#pwm-cells": + const: 3 + +pwm-cells: +- channel +- period +- flags diff --git a/dts/bindings/timer/thead,machine-timer.yaml b/dts/bindings/timer/thead,machine-timer.yaml new file mode 100644 index 00000000000000..f3099ed7e54387 --- /dev/null +++ b/dts/bindings/timer/thead,machine-timer.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +description: T-Head Machine Timer + +compatible: "thead,machine-timer" + +include: base.yaml + +properties: + reg: + required: true + + interrupts-extended: + required: true diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index f5d378cf6ee596..39bbdb0266607f 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -425,6 +425,7 @@ microsoft Microsoft Corporation microsys MicroSys Electronics GmbH mikroe MikroElektronika d.o.o. mikrotik MikroTik +milkv Shenzhen MilkV Technology Co., Ltd miniand Miniand Tech minix MINIX Technology Ltd. miramems MiraMEMS Sensing Technology Co., Ltd. @@ -628,6 +629,7 @@ solderparty Solder Party AB solidrun SolidRun solomon Solomon Systech Limited sony Sony Corporation +sophgo SOPHGO Technologies spacecubics Space Cubics, LLC spansion Spansion Inc. sparkfun SparkFun Electronics @@ -664,6 +666,7 @@ telit Telit Cinterion tempo Tempo Semiconductor terasic Terasic Inc. tfc Three Five Corp +thead T-Head Semiconductor Co., Ltd. thine THine Electronics, Inc. thingyjp thingy.jp ti Texas Instruments diff --git a/dts/riscv/sophgo/cv180x.dtsi b/dts/riscv/sophgo/cv180x.dtsi new file mode 100644 index 00000000000000..bd76a2f7211bf6 --- /dev/null +++ b/dts/riscv/sophgo/cv180x.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2023-2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include +#include + +/ { + soc { + compatible = "sophgo,cv180x", "simple-bus"; + + mbox: mailbox@1900000 { + compatible = "sophgo,cvi-mailbox"; + reg = <0x1900000 DT_SIZE_K(4)>; + interrupts = <61 1>; + channel-max = <8>; + tx-cpu = <1>; + rx-cpu = <2>; + #mbox-cells = <1>; + status = "disabled"; + }; + + pinctrl: pin-controller@3001000 { + compatible = "sophgo,cvi-pinctrl"; + reg = <0x3001000 DT_SIZE_K(4)>; + }; + + gpioa: gpio@3020000 { + compatible = "snps,designware-gpio"; + reg = <0x3020000 DT_SIZE_K(4)>; + interrupts = <41 1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpiob: gpio@3021000 { + compatible = "snps,designware-gpio"; + reg = <0x3021000 DT_SIZE_K(4)>; + interrupts = <42 1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpioc: gpio@3022000 { + compatible = "snps,designware-gpio"; + reg = <0x3022000 DT_SIZE_K(4)>; + interrupts = <43 1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpiod: gpio@3023000 { + compatible = "snps,designware-gpio"; + reg = <0x3023000 DT_SIZE_K(4)>; + interrupts = <44 1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + pwm0: pwm@3060000 { + compatible = "sophgo,cvi-pwm"; + reg = <0x3060000 DT_SIZE_K(4)>; + clock-frequency = ; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@3061000 { + compatible = "sophgo,cvi-pwm"; + reg = <0x3061000 DT_SIZE_K(4)>; + clock-frequency = ; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@3062000 { + compatible = "sophgo,cvi-pwm"; + reg = <0x3062000 DT_SIZE_K(4)>; + clock-frequency = ; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@3063000 { + compatible = "sophgo,cvi-pwm"; + reg = <0x3063000 DT_SIZE_K(4)>; + clock-frequency = ; + #pwm-cells = <3>; + status = "disabled"; + }; + + uart0: uart@4140000 { + compatible = "ns16550"; + reg = <0x4140000 DT_SIZE_K(64)>; + interrupts = <30 1>; + reg-shift = <2>; + clock-frequency = ; + status = "disabled"; + }; + + uart1: uart@4150000 { + compatible = "ns16550"; + reg = <0x4150000 DT_SIZE_K(64)>; + interrupts = <31 1>; + reg-shift = <2>; + clock-frequency = ; + status = "disabled"; + }; + + uart2: uart@4160000 { + compatible = "ns16550"; + reg = <0x4160000 DT_SIZE_K(64)>; + /* interrupt is not supported */ + reg-shift = <2>; + clock-frequency = ; + status = "disabled"; + }; + + uart3: uart@4170000 { + compatible = "ns16550"; + reg = <0x4170000 DT_SIZE_K(64)>; + /* interrupt is not supported */ + reg-shift = <2>; + clock-frequency = ; + status = "disabled"; + }; + + uart4: uart@41c0000 { + compatible = "ns16550"; + reg = <0x41c0000 DT_SIZE_K(64)>; + /* interrupt is not supported */ + reg-shift = <2>; + clock-frequency = ; + status = "disabled"; + }; + }; +}; diff --git a/dts/riscv/sophgo/cv181x.dtsi b/dts/riscv/sophgo/cv181x.dtsi new file mode 100644 index 00000000000000..7813032b49f9fb --- /dev/null +++ b/dts/riscv/sophgo/cv181x.dtsi @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include +#include + +/ { + soc { + compatible = "sophgo,cv181x", "simple-bus"; + + mbox: mailbox@1900000 { + compatible = "sophgo,cvi-mailbox"; + reg = <0x1900000 DT_SIZE_K(4)>; + interrupts = <61 1>; + channel-max = <8>; + tx-cpu = <1>; + rx-cpu = <2>; + #mbox-cells = <1>; + status = "disabled"; + }; + + pinctrl: pin-controller@3001000 { + compatible = "sophgo,cvi-pinctrl"; + reg = <0x3001000 DT_SIZE_K(4)>; + }; + + gpioa: gpio@3020000 { + compatible = "snps,designware-gpio"; + reg = <0x3020000 DT_SIZE_K(4)>; + interrupts = <41 1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpiob: gpio@3021000 { + compatible = "snps,designware-gpio"; + reg = <0x3021000 DT_SIZE_K(4)>; + interrupts = <42 1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpioc: gpio@3022000 { + compatible = "snps,designware-gpio"; + reg = <0x3022000 DT_SIZE_K(4)>; + interrupts = <43 1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpiod: gpio@3023000 { + compatible = "snps,designware-gpio"; + reg = <0x3023000 DT_SIZE_K(4)>; + interrupts = <44 1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + pwm0: pwm@3060000 { + compatible = "sophgo,cvi-pwm"; + reg = <0x3060000 DT_SIZE_K(4)>; + clock-frequency = ; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@3061000 { + compatible = "sophgo,cvi-pwm"; + reg = <0x3061000 DT_SIZE_K(4)>; + clock-frequency = ; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@3062000 { + compatible = "sophgo,cvi-pwm"; + reg = <0x3062000 DT_SIZE_K(4)>; + clock-frequency = ; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@3063000 { + compatible = "sophgo,cvi-pwm"; + reg = <0x3063000 DT_SIZE_K(4)>; + clock-frequency = ; + #pwm-cells = <3>; + status = "disabled"; + }; + + uart0: uart@4140000 { + compatible = "ns16550"; + reg = <0x4140000 DT_SIZE_K(64)>; + interrupts = <30 1>; + reg-shift = <2>; + clock-frequency = ; + status = "disabled"; + }; + + uart1: uart@4150000 { + compatible = "ns16550"; + reg = <0x4150000 DT_SIZE_K(64)>; + interrupts = <31 1>; + reg-shift = <2>; + clock-frequency = ; + status = "disabled"; + }; + + uart2: uart@4160000 { + compatible = "ns16550"; + reg = <0x4160000 DT_SIZE_K(64)>; + /* interrupt is not supported */ + reg-shift = <2>; + clock-frequency = ; + status = "disabled"; + }; + + uart3: uart@4170000 { + compatible = "ns16550"; + reg = <0x4170000 DT_SIZE_K(64)>; + /* interrupt is not supported */ + reg-shift = <2>; + clock-frequency = ; + status = "disabled"; + }; + + uart4: uart@41c0000 { + compatible = "ns16550"; + reg = <0x41c0000 DT_SIZE_K(64)>; + /* interrupt is not supported */ + reg-shift = <2>; + clock-frequency = ; + status = "disabled"; + }; + + pwr_gpio: gpio@5021000 { + compatible = "snps,designware-gpio"; + reg = <0x5021000 DT_SIZE_K(4)>; + interrupts = <48 1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; +}; diff --git a/dts/riscv/sophgo/cv18xx-c906-common.dtsi b/dts/riscv/sophgo/cv18xx-c906-common.dtsi new file mode 100644 index 00000000000000..7d12603755cee4 --- /dev/null +++ b/dts/riscv/sophgo/cv18xx-c906-common.dtsi @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023-2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "thead,c906"; + reg = <0>; + clock-frequency = ; + mmu-type = "riscv,none"; + riscv,isa = "rv64imafdc_zicsr_zifencei"; + + hlic: interrupt-controller { + compatible = "riscv,cpu-intc"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&plic0>; + + plic0: interrupt-controller@70000000 { + compatible = "sifive,plic-1.0.0"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&hlic 11>; + interrupt-controller; + riscv,max-priority = <7>; + riscv,ndev = <101>; + #address-cells = <0>; + #interrupt-cells = <2>; + }; + + systick: systick@74000000 { + compatible = "thead,machine-timer"; + reg = <0x74000000 DT_SIZE_K(64)>; + interrupts-extended = <&hlic 7>; + }; + }; +}; diff --git a/include/zephyr/dt-bindings/pinctrl/sophgo-cv180x-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/sophgo-cv180x-pinctrl.h new file mode 100644 index 00000000000000..768926a1cddd10 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/sophgo-cv180x-pinctrl.h @@ -0,0 +1,486 @@ +/* + * Copyright (c) 2023 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DT_SOPHGO_CV180X_PINCTRL_H_ +#define ZEPHYR_DT_SOPHGO_CV180X_PINCTRL_H_ + +#include + +#define FMUX_IDX_SD0_CLK 0 +#define FMUX_IDX_SD0_CMD 1 +#define FMUX_IDX_SD0_D0 2 +#define FMUX_IDX_SD0_D1 3 +#define FMUX_IDX_SD0_D2 4 +#define FMUX_IDX_SD0_D3 5 +#define FMUX_IDX_SD0_CD 6 +#define FMUX_IDX_SD0_PWR_EN 7 +#define FMUX_IDX_SPK_EN 8 +#define FMUX_IDX_UART0_TX 9 +#define FMUX_IDX_UART0_RX 10 +#define FMUX_IDX_SPINOR_HOLD_X 11 +#define FMUX_IDX_SPINOR_SCK 12 +#define FMUX_IDX_SPINOR_MOSI 13 +#define FMUX_IDX_SPINOR_WP_X 14 +#define FMUX_IDX_SPINOR_MISO 15 +#define FMUX_IDX_SPINOR_CS_X 16 +#define FMUX_IDX_JTAG_CPU_TMS 17 +#define FMUX_IDX_JTAG_CPU_TCK 18 +#define FMUX_IDX_IIC0_SCL 19 +#define FMUX_IDX_IIC0_SDA 20 +#define FMUX_IDX_AUX0 21 +#define FMUX_IDX_GPIO_ZQ 22 +#define FMUX_IDX_PWR_VBAT_DET 23 +#define FMUX_IDX_PWR_RSTN 24 +#define FMUX_IDX_PWR_SEQ1 25 +#define FMUX_IDX_PWR_SEQ2 26 +#define FMUX_IDX_PWR_WAKEUP0 27 +#define FMUX_IDX_PWR_BUTTON1 28 +#define FMUX_IDX_XTAL_XIN 29 +#define FMUX_IDX_PWR_GPIO0 30 +#define FMUX_IDX_PWR_GPIO1 31 +#define FMUX_IDX_PWR_GPIO2 32 +#define FMUX_IDX_SD1_GPIO1 33 +#define FMUX_IDX_SD1_GPIO0 34 +#define FMUX_IDX_SD1_D3 35 +#define FMUX_IDX_SD1_D2 36 +#define FMUX_IDX_SD1_D1 37 +#define FMUX_IDX_SD1_D0 38 +#define FMUX_IDX_SD1_CMD 39 +#define FMUX_IDX_SD1_CLK 40 +#define FMUX_IDX_PWM0_BUCK 41 +#define FMUX_IDX_ADC1 42 +#define FMUX_IDX_USB_VBUS_DET 43 +#define FMUX_IDX_MUX_SPI1_MISO 44 +#define FMUX_IDX_MUX_SPI1_MOSI 45 +#define FMUX_IDX_MUX_SPI1_CS 46 +#define FMUX_IDX_MUX_SPI1_SCK 47 +#define FMUX_IDX_PAD_ETH_TXP 48 +#define FMUX_IDX_PAD_ETH_TXM 49 +#define FMUX_IDX_PAD_ETH_RXP 50 +#define FMUX_IDX_PAD_ETH_RXM 51 +#define FMUX_IDX_GPIO_RTX 52 +#define FMUX_IDX_PAD_MIPIRX4N 53 +#define FMUX_IDX_PAD_MIPIRX4P 54 +#define FMUX_IDX_PAD_MIPIRX3N 55 +#define FMUX_IDX_PAD_MIPIRX3P 56 +#define FMUX_IDX_PAD_MIPIRX2N 57 +#define FMUX_IDX_PAD_MIPIRX2P 58 +#define FMUX_IDX_PAD_MIPIRX1N 59 +#define FMUX_IDX_PAD_MIPIRX1P 60 +#define FMUX_IDX_PAD_MIPIRX0N 61 +#define FMUX_IDX_PAD_MIPIRX0P 62 +#define FMUX_IDX_PAD_MIPI_TXM2 63 +#define FMUX_IDX_PAD_MIPI_TXP2 64 +#define FMUX_IDX_PAD_MIPI_TXM1 65 +#define FMUX_IDX_PAD_MIPI_TXP1 66 +#define FMUX_IDX_PAD_MIPI_TXM0 67 +#define FMUX_IDX_PAD_MIPI_TXP0 68 +#define FMUX_IDX_PKG_TYPE0 69 +#define FMUX_IDX_PKG_TYPE1 70 +#define FMUX_IDX_PKG_TYPE2 71 +#define FMUX_IDX_PAD_AUD_AINL_MIC 72 +#define FMUX_IDX_PAD_AUD_AINR_MIC 73 +#define FMUX_IDX_PAD_AUD_AOUTL 74 +#define FMUX_IDX_PAD_AUD_AOUTR 75 + +#define FMUX_SEL_SD0_CLK__SDIO0_CLK 0 +#define FMUX_SEL_SD0_CLK__IIC1_SDA 1 +#define FMUX_SEL_SD0_CLK__SPI0_SCK 2 +#define FMUX_SEL_SD0_CLK__XGPIOA_7 3 +#define FMUX_SEL_SD0_CLK__PWM_15 5 +#define FMUX_SEL_SD0_CLK__EPHY_LNK_LED 6 +#define FMUX_SEL_SD0_CLK__DBG_0 7 +#define FMUX_SEL_SD0_CMD__SDIO0_CMD 0 +#define FMUX_SEL_SD0_CMD__IIC1_SCL 1 +#define FMUX_SEL_SD0_CMD__SPI0_SDO 2 +#define FMUX_SEL_SD0_CMD__XGPIOA_8 3 +#define FMUX_SEL_SD0_CMD__PWM_14 5 +#define FMUX_SEL_SD0_CMD__EPHY_SPD_LED 6 +#define FMUX_SEL_SD0_CMD__DBG_1 7 +#define FMUX_SEL_SD0_D0__SDIO0_D_0 0 +#define FMUX_SEL_SD0_D0__CAM_MCLK1 1 +#define FMUX_SEL_SD0_D0__SPI0_SDI 2 +#define FMUX_SEL_SD0_D0__XGPIOA_9 3 +#define FMUX_SEL_SD0_D0__UART3_TX 4 +#define FMUX_SEL_SD0_D0__PWM_13 5 +#define FMUX_SEL_SD0_D0__WG0_D0 6 +#define FMUX_SEL_SD0_D0__DBG_2 7 +#define FMUX_SEL_SD0_D1__SDIO0_D_1 0 +#define FMUX_SEL_SD0_D1__IIC1_SDA 1 +#define FMUX_SEL_SD0_D1__AUX0 2 +#define FMUX_SEL_SD0_D1__XGPIOA_10 3 +#define FMUX_SEL_SD0_D1__UART1_TX 4 +#define FMUX_SEL_SD0_D1__PWM_12 5 +#define FMUX_SEL_SD0_D1__WG0_D1 6 +#define FMUX_SEL_SD0_D1__DBG_3 7 +#define FMUX_SEL_SD0_D2__SDIO0_D_2 0 +#define FMUX_SEL_SD0_D2__IIC1_SCL 1 +#define FMUX_SEL_SD0_D2__AUX1 2 +#define FMUX_SEL_SD0_D2__XGPIOA_11 3 +#define FMUX_SEL_SD0_D2__UART1_RX 4 +#define FMUX_SEL_SD0_D2__PWM_11 5 +#define FMUX_SEL_SD0_D2__WG1_D0 6 +#define FMUX_SEL_SD0_D2__DBG_4 7 +#define FMUX_SEL_SD0_D3__SDIO0_D_3 0 +#define FMUX_SEL_SD0_D3__CAM_MCLK0 1 +#define FMUX_SEL_SD0_D3__SPI0_CS_X 2 +#define FMUX_SEL_SD0_D3__XGPIOA_12 3 +#define FMUX_SEL_SD0_D3__UART3_RX 4 +#define FMUX_SEL_SD0_D3__PWM_10 5 +#define FMUX_SEL_SD0_D3__WG1_D1 6 +#define FMUX_SEL_SD0_D3__DBG_5 7 +#define FMUX_SEL_SD0_CD__SDIO0_CD 0 +#define FMUX_SEL_SD0_CD__XGPIOA_13 3 +#define FMUX_SEL_SD0_PWR_EN__SDIO0_PWR_EN 0 +#define FMUX_SEL_SD0_PWR_EN__XGPIOA_14 3 +#define FMUX_SEL_SPK_EN__XGPIOA_15 3 +#define FMUX_SEL_UART0_TX__UART0_TX 0 +#define FMUX_SEL_UART0_TX__CAM_MCLK1 1 +#define FMUX_SEL_UART0_TX__PWM_4 2 +#define FMUX_SEL_UART0_TX__XGPIOA_16 3 +#define FMUX_SEL_UART0_TX__UART1_TX 4 +#define FMUX_SEL_UART0_TX__AUX1 5 +#define FMUX_SEL_UART0_TX__JTAG_TMS 6 +#define FMUX_SEL_UART0_TX__DBG_6 7 +#define FMUX_SEL_UART0_RX__UART0_RX 0 +#define FMUX_SEL_UART0_RX__CAM_MCLK0 1 +#define FMUX_SEL_UART0_RX__PWM_5 2 +#define FMUX_SEL_UART0_RX__XGPIOA_17 3 +#define FMUX_SEL_UART0_RX__UART1_RX 4 +#define FMUX_SEL_UART0_RX__AUX0 5 +#define FMUX_SEL_UART0_RX__JTAG_TCK 6 +#define FMUX_SEL_UART0_RX__DBG_7 7 +#define FMUX_SEL_SPINOR_HOLD_X__SPINOR_HOLD_X 1 +#define FMUX_SEL_SPINOR_HOLD_X__SPINAND_HOLD 2 +#define FMUX_SEL_SPINOR_HOLD_X__XGPIOA_26 3 +#define FMUX_SEL_SPINOR_SCK__SPINOR_SCK 1 +#define FMUX_SEL_SPINOR_SCK__SPINAND_CLK 2 +#define FMUX_SEL_SPINOR_SCK__XGPIOA_22 3 +#define FMUX_SEL_SPINOR_MOSI__SPINOR_MOSI 1 +#define FMUX_SEL_SPINOR_MOSI__SPINAND_MOSI 2 +#define FMUX_SEL_SPINOR_MOSI__XGPIOA_25 3 +#define FMUX_SEL_SPINOR_WP_X__SPINOR_WP_X 1 +#define FMUX_SEL_SPINOR_WP_X__SPINAND_WP 2 +#define FMUX_SEL_SPINOR_WP_X__XGPIOA_27 3 +#define FMUX_SEL_SPINOR_MISO__SPINOR_MISO 1 +#define FMUX_SEL_SPINOR_MISO__SPINAND_MISO 2 +#define FMUX_SEL_SPINOR_MISO__XGPIOA_23 3 +#define FMUX_SEL_SPINOR_CS_X__SPINOR_CS_X 1 +#define FMUX_SEL_SPINOR_CS_X__SPINAND_CS 2 +#define FMUX_SEL_SPINOR_CS_X__XGPIOA_24 3 +#define FMUX_SEL_JTAG_CPU_TMS__JTAG_TMS 0 +#define FMUX_SEL_JTAG_CPU_TMS__CAM_MCLK0 1 +#define FMUX_SEL_JTAG_CPU_TMS__PWM_7 2 +#define FMUX_SEL_JTAG_CPU_TMS__XGPIOA_19 3 +#define FMUX_SEL_JTAG_CPU_TMS__UART1_RTS 4 +#define FMUX_SEL_JTAG_CPU_TMS__AUX0 5 +#define FMUX_SEL_JTAG_CPU_TMS__UART1_TX 6 +#define FMUX_SEL_JTAG_CPU_TCK__JTAG_TCK 0 +#define FMUX_SEL_JTAG_CPU_TCK__CAM_MCLK1 1 +#define FMUX_SEL_JTAG_CPU_TCK__PWM_6 2 +#define FMUX_SEL_JTAG_CPU_TCK__XGPIOA_18 3 +#define FMUX_SEL_JTAG_CPU_TCK__UART1_CTS 4 +#define FMUX_SEL_JTAG_CPU_TCK__AUX1 5 +#define FMUX_SEL_JTAG_CPU_TCK__UART1_RX 6 +#define FMUX_SEL_IIC0_SCL__CV_SCL0__CR_4WTDI 0 +#define FMUX_SEL_IIC0_SDA__CV_SDA0__CR_4WTDO 0 +#define FMUX_SEL_IIC0_SCL__JTAG_TDI 0 +#define FMUX_SEL_IIC0_SCL__UART1_TX 1 +#define FMUX_SEL_IIC0_SCL__UART2_TX 2 +#define FMUX_SEL_IIC0_SCL__XGPIOA_28 3 +#define FMUX_SEL_IIC0_SCL__IIC0_SCL 4 +#define FMUX_SEL_IIC0_SCL__WG0_D0 5 +#define FMUX_SEL_IIC0_SCL__DBG_10 7 +#define FMUX_SEL_IIC0_SDA__JTAG_TDO 0 +#define FMUX_SEL_IIC0_SDA__UART1_RX 1 +#define FMUX_SEL_IIC0_SDA__UART2_RX 2 +#define FMUX_SEL_IIC0_SDA__XGPIOA_29 3 +#define FMUX_SEL_IIC0_SDA__IIC0_SDA 4 +#define FMUX_SEL_IIC0_SDA__WG0_D1 5 +#define FMUX_SEL_IIC0_SDA__WG1_D0 6 +#define FMUX_SEL_IIC0_SDA__DBG_11 7 +#define FMUX_SEL_AUX0__AUX0 0 +#define FMUX_SEL_AUX0__XGPIOA_30 3 +#define FMUX_SEL_AUX0__IIS1_MCLK 4 +#define FMUX_SEL_AUX0__WG1_D1 6 +#define FMUX_SEL_AUX0__DBG_12 7 +#define FMUX_SEL_GPIO_ZQ__PWR_GPIO_24 3 +#define FMUX_SEL_GPIO_ZQ__PWM_2 4 +#define FMUX_SEL_PWR_VBAT_DET__PWR_VBAT_DET 0 +#define FMUX_SEL_PWR_RSTN__PWR_RSTN 0 +#define FMUX_SEL_PWR_SEQ1__PWR_SEQ1 0 +#define FMUX_SEL_PWR_SEQ1__PWR_GPIO_3 3 +#define FMUX_SEL_PWR_SEQ2__PWR_SEQ2 0 +#define FMUX_SEL_PWR_SEQ2__PWR_GPIO_4 3 +#define FMUX_SEL_PTEST__PWR_PTEST 0 +#define FMUX_SEL_PWR_WAKEUP0__PWR_WAKEUP0 0 +#define FMUX_SEL_PWR_WAKEUP0__PWR_IR0 1 +#define FMUX_SEL_PWR_WAKEUP0__PWR_UART0_TX 2 +#define FMUX_SEL_PWR_WAKEUP0__PWR_GPIO_6 3 +#define FMUX_SEL_PWR_WAKEUP0__UART1_TX 4 +#define FMUX_SEL_PWR_WAKEUP0__IIC4_SCL 5 +#define FMUX_SEL_PWR_WAKEUP0__EPHY_LNK_LED 6 +#define FMUX_SEL_PWR_WAKEUP0__WG2_D0 7 +#define FMUX_SEL_PWR_BUTTON1__PWR_BUTTON1 0 +#define FMUX_SEL_PWR_BUTTON1__PWR_GPIO_8 3 +#define FMUX_SEL_PWR_BUTTON1__UART1_RX 4 +#define FMUX_SEL_PWR_BUTTON1__IIC4_SDA 5 +#define FMUX_SEL_PWR_BUTTON1__EPHY_SPD_LED 6 +#define FMUX_SEL_PWR_BUTTON1__WG2_D1 7 +#define FMUX_SEL_XTAL_XIN__PWR_XTAL_CLKIN 0 +#define FMUX_SEL_PWR_GPIO0__PWR_GPIO_0 0 +#define FMUX_SEL_PWR_GPIO0__UART2_TX 1 +#define FMUX_SEL_PWR_GPIO0__PWR_UART0_RX 2 +#define FMUX_SEL_PWR_GPIO0__PWM_8 4 +#define FMUX_SEL_PWR_GPIO1__PWR_GPIO_1 0 +#define FMUX_SEL_PWR_GPIO1__UART2_RX 1 +#define FMUX_SEL_PWR_GPIO1__EPHY_LNK_LED 3 +#define FMUX_SEL_PWR_GPIO1__PWM_9 4 +#define FMUX_SEL_PWR_GPIO1__PWR_IIC_SCL 5 +#define FMUX_SEL_PWR_GPIO1__IIC2_SCL 6 +#define FMUX_SEL_PWR_GPIO1__IIC0_SDA 7 +#define FMUX_SEL_PWR_GPIO2__PWR_GPIO_2 0 +#define FMUX_SEL_PWR_GPIO2__PWR_SECTICK 2 +#define FMUX_SEL_PWR_GPIO2__EPHY_SPD_LED 3 +#define FMUX_SEL_PWR_GPIO2__PWM_10 4 +#define FMUX_SEL_PWR_GPIO2__PWR_IIC_SDA 5 +#define FMUX_SEL_PWR_GPIO2__IIC2_SDA 6 +#define FMUX_SEL_PWR_GPIO2__IIC0_SCL 7 +#define FMUX_SEL_SD1_GPIO1__UART4_TX 1 +#define FMUX_SEL_SD1_GPIO1__PWR_GPIO_26 3 +#define FMUX_SEL_SD1_GPIO1__PWM_10 7 +#define FMUX_SEL_SD1_GPIO0__UART4_RX 1 +#define FMUX_SEL_SD1_GPIO0__PWR_GPIO_25 3 +#define FMUX_SEL_SD1_GPIO0__PWM_11 7 +#define FMUX_SEL_SD1_D3__PWR_SD1_D3 0 +#define FMUX_SEL_SD1_D3__SPI2_CS_X 1 +#define FMUX_SEL_SD1_D3__IIC1_SCL 2 +#define FMUX_SEL_SD1_D3__PWR_GPIO_18 3 +#define FMUX_SEL_SD1_D3__CAM_MCLK0 4 +#define FMUX_SEL_SD1_D3__UART3_CTS 5 +#define FMUX_SEL_SD1_D3__PWR_SPINOR1_CS_X 6 +#define FMUX_SEL_SD1_D3__PWM_4 7 +#define FMUX_SEL_SD1_D2__PWR_SD1_D2 0 +#define FMUX_SEL_SD1_D2__IIC1_SCL 1 +#define FMUX_SEL_SD1_D2__UART2_TX 2 +#define FMUX_SEL_SD1_D2__PWR_GPIO_19 3 +#define FMUX_SEL_SD1_D2__CAM_MCLK0 4 +#define FMUX_SEL_SD1_D2__UART3_TX 5 +#define FMUX_SEL_SD1_D2__PWR_SPINOR1_HOLD_X 6 +#define FMUX_SEL_SD1_D2__PWM_5 7 +#define FMUX_SEL_SD1_D1__PWR_SD1_D1 0 +#define FMUX_SEL_SD1_D1__IIC1_SDA 1 +#define FMUX_SEL_SD1_D1__UART2_RX 2 +#define FMUX_SEL_SD1_D1__PWR_GPIO_20 3 +#define FMUX_SEL_SD1_D1__CAM_MCLK1 4 +#define FMUX_SEL_SD1_D1__UART3_RX 5 +#define FMUX_SEL_SD1_D1__PWR_SPINOR1_WP_X 6 +#define FMUX_SEL_SD1_D1__PWM_6 7 +#define FMUX_SEL_SD1_D0__PWR_SD1_D0 0 +#define FMUX_SEL_SD1_D0__SPI2_SDI 1 +#define FMUX_SEL_SD1_D0__IIC1_SDA 2 +#define FMUX_SEL_SD1_D0__PWR_GPIO_21 3 +#define FMUX_SEL_SD1_D0__CAM_MCLK1 4 +#define FMUX_SEL_SD1_D0__UART3_RTS 5 +#define FMUX_SEL_SD1_D0__PWR_SPINOR1_MISO 6 +#define FMUX_SEL_SD1_D0__PWM_7 7 +#define FMUX_SEL_SD1_CMD__PWR_SD1_CMD 0 +#define FMUX_SEL_SD1_CMD__SPI2_SDO 1 +#define FMUX_SEL_SD1_CMD__IIC3_SCL 2 +#define FMUX_SEL_SD1_CMD__PWR_GPIO_22 3 +#define FMUX_SEL_SD1_CMD__CAM_VS0 4 +#define FMUX_SEL_SD1_CMD__EPHY_LNK_LED 5 +#define FMUX_SEL_SD1_CMD__PWR_SPINOR1_MOSI 6 +#define FMUX_SEL_SD1_CMD__PWM_8 7 +#define FMUX_SEL_SD1_CLK__PWR_SD1_CLK 0 +#define FMUX_SEL_SD1_CLK__SPI2_SCK 1 +#define FMUX_SEL_SD1_CLK__IIC3_SDA 2 +#define FMUX_SEL_SD1_CLK__PWR_GPIO_23 3 +#define FMUX_SEL_SD1_CLK__CAM_HS0 4 +#define FMUX_SEL_SD1_CLK__EPHY_SPD_LED 5 +#define FMUX_SEL_SD1_CLK__PWR_SPINOR1_SCK 6 +#define FMUX_SEL_SD1_CLK__PWM_9 7 +#define FMUX_SEL_PWM0_BUCK__PWM_0 0 +#define FMUX_SEL_PWM0_BUCK__XGPIOB_0 3 +#define FMUX_SEL_ADC1__XGPIOB_3 3 +#define FMUX_SEL_ADC1__KEY_COL2 4 +#define FMUX_SEL_ADC1__PWM_3 6 +#define FMUX_SEL_USB_VBUS_DET__USB_VBUS_DET 0 +#define FMUX_SEL_USB_VBUS_DET__XGPIOB_6 3 +#define FMUX_SEL_USB_VBUS_DET__CAM_MCLK0 4 +#define FMUX_SEL_USB_VBUS_DET__CAM_MCLK1 5 +#define FMUX_SEL_USB_VBUS_DET__PWM_4 6 +#define FMUX_SEL_MUX_SPI1_MISO__UART3_RTS 1 +#define FMUX_SEL_MUX_SPI1_MISO__IIC1_SDA 2 +#define FMUX_SEL_MUX_SPI1_MISO__XGPIOB_8 3 +#define FMUX_SEL_MUX_SPI1_MISO__PWM_9 4 +#define FMUX_SEL_MUX_SPI1_MISO__KEY_COL1 5 +#define FMUX_SEL_MUX_SPI1_MISO__SPI1_SDI 6 +#define FMUX_SEL_MUX_SPI1_MISO__DBG_14 7 +#define FMUX_SEL_MUX_SPI1_MOSI__UART3_RX 1 +#define FMUX_SEL_MUX_SPI1_MOSI__IIC1_SCL 2 +#define FMUX_SEL_MUX_SPI1_MOSI__XGPIOB_7 3 +#define FMUX_SEL_MUX_SPI1_MOSI__PWM_8 4 +#define FMUX_SEL_MUX_SPI1_MOSI__KEY_COL0 5 +#define FMUX_SEL_MUX_SPI1_MOSI__SPI1_SDO 6 +#define FMUX_SEL_MUX_SPI1_MOSI__DBG_13 7 +#define FMUX_SEL_MUX_SPI1_CS__UART3_CTS 1 +#define FMUX_SEL_MUX_SPI1_CS__CAM_MCLK0 2 +#define FMUX_SEL_MUX_SPI1_CS__XGPIOB_10 3 +#define FMUX_SEL_MUX_SPI1_CS__PWM_11 4 +#define FMUX_SEL_MUX_SPI1_CS__KEY_ROW3 5 +#define FMUX_SEL_MUX_SPI1_CS__SPI1_CS_X 6 +#define FMUX_SEL_MUX_SPI1_CS__DBG_16 7 +#define FMUX_SEL_MUX_SPI1_SCK__UART3_TX 1 +#define FMUX_SEL_MUX_SPI1_SCK__CAM_MCLK1 2 +#define FMUX_SEL_MUX_SPI1_SCK__XGPIOB_9 3 +#define FMUX_SEL_MUX_SPI1_SCK__PWM_10 4 +#define FMUX_SEL_MUX_SPI1_SCK__KEY_ROW2 5 +#define FMUX_SEL_MUX_SPI1_SCK__SPI1_SCK 6 +#define FMUX_SEL_MUX_SPI1_SCK__DBG_15 7 +#define FMUX_SEL_PAD_ETH_TXP__UART3_RX 1 +#define FMUX_SEL_PAD_ETH_TXP__IIC1_SCL 2 +#define FMUX_SEL_PAD_ETH_TXP__XGPIOB_25 3 +#define FMUX_SEL_PAD_ETH_TXP__PWM_13 4 +#define FMUX_SEL_PAD_ETH_TXP__CAM_MCLK0 5 +#define FMUX_SEL_PAD_ETH_TXP__SPI1_SDO 6 +#define FMUX_SEL_PAD_ETH_TXP__IIS2_LRCK 7 +#define FMUX_SEL_PAD_ETH_TXM__UART3_RTS 1 +#define FMUX_SEL_PAD_ETH_TXM__IIC1_SDA 2 +#define FMUX_SEL_PAD_ETH_TXM__XGPIOB_24 3 +#define FMUX_SEL_PAD_ETH_TXM__PWM_12 4 +#define FMUX_SEL_PAD_ETH_TXM__CAM_MCLK1 5 +#define FMUX_SEL_PAD_ETH_TXM__SPI1_SDI 6 +#define FMUX_SEL_PAD_ETH_TXM__IIS2_BCLK 7 +#define FMUX_SEL_PAD_ETH_RXP__UART3_TX 1 +#define FMUX_SEL_PAD_ETH_RXP__CAM_MCLK1 2 +#define FMUX_SEL_PAD_ETH_RXP__XGPIOB_27 3 +#define FMUX_SEL_PAD_ETH_RXP__PWM_15 4 +#define FMUX_SEL_PAD_ETH_RXP__CAM_HS0 5 +#define FMUX_SEL_PAD_ETH_RXP__SPI1_SCK 6 +#define FMUX_SEL_PAD_ETH_RXP__IIS2_DO 7 +#define FMUX_SEL_PAD_ETH_RXM__UART3_CTS 1 +#define FMUX_SEL_PAD_ETH_RXM__CAM_MCLK0 2 +#define FMUX_SEL_PAD_ETH_RXM__XGPIOB_26 3 +#define FMUX_SEL_PAD_ETH_RXM__PWM_14 4 +#define FMUX_SEL_PAD_ETH_RXM__CAM_VS0 5 +#define FMUX_SEL_PAD_ETH_RXM__SPI1_CS_X 6 +#define FMUX_SEL_PAD_ETH_RXM__IIS2_DI 7 +#define FMUX_SEL_GPIO_RTX__VI0_D_15 1 +#define FMUX_SEL_GPIO_RTX__XGPIOB_23 3 +#define FMUX_SEL_GPIO_RTX__PWM_1 4 +#define FMUX_SEL_GPIO_RTX__CAM_MCLK0 5 +#define FMUX_SEL_GPIO_RTX__IIS2_MCLK 7 +#define FMUX_SEL_PAD_MIPIRX4N__VI0_CLK 1 +#define FMUX_SEL_PAD_MIPIRX4N__IIC0_SCL 2 +#define FMUX_SEL_PAD_MIPIRX4N__XGPIOC_2 3 +#define FMUX_SEL_PAD_MIPIRX4N__IIC1_SDA 4 +#define FMUX_SEL_PAD_MIPIRX4N__CAM_MCLK0 5 +#define FMUX_SEL_PAD_MIPIRX4N__KEY_ROW0 6 +#define FMUX_SEL_PAD_MIPIRX4N__MUX_SPI1_SCK 7 +#define FMUX_SEL_PAD_MIPIRX4P__VI0_D_0 1 +#define FMUX_SEL_PAD_MIPIRX4P__IIC0_SDA 2 +#define FMUX_SEL_PAD_MIPIRX4P__XGPIOC_3 3 +#define FMUX_SEL_PAD_MIPIRX4P__IIC1_SCL 4 +#define FMUX_SEL_PAD_MIPIRX4P__CAM_MCLK1 5 +#define FMUX_SEL_PAD_MIPIRX4P__KEY_ROW1 6 +#define FMUX_SEL_PAD_MIPIRX4P__MUX_SPI1_CS 7 +#define FMUX_SEL_PAD_MIPIRX3N__VI0_D_1 1 +#define FMUX_SEL_PAD_MIPIRX3N__XGPIOC_4 3 +#define FMUX_SEL_PAD_MIPIRX3N__CAM_MCLK0 4 +#define FMUX_SEL_PAD_MIPIRX3N__MUX_SPI1_MISO 7 +#define FMUX_SEL_PAD_MIPIRX3P__VI0_D_2 1 +#define FMUX_SEL_PAD_MIPIRX3P__XGPIOC_5 3 +#define FMUX_SEL_PAD_MIPIRX3P__MUX_SPI1_MOSI 7 +#define FMUX_SEL_PAD_MIPIRX2N__VI0_D_3 1 +#define FMUX_SEL_PAD_MIPIRX2N__XGPIOC_6 3 +#define FMUX_SEL_PAD_MIPIRX2N__IIC4_SCL 5 +#define FMUX_SEL_PAD_MIPIRX2N__DBG_6 7 +#define FMUX_SEL_PAD_MIPIRX2P__VI0_D_4 1 +#define FMUX_SEL_PAD_MIPIRX2P__XGPIOC_7 3 +#define FMUX_SEL_PAD_MIPIRX2P__IIC4_SDA 5 +#define FMUX_SEL_PAD_MIPIRX2P__DBG_7 7 +#define FMUX_SEL_PAD_MIPIRX1N__VI0_D_5 1 +#define FMUX_SEL_PAD_MIPIRX1N__XGPIOC_8 3 +#define FMUX_SEL_PAD_MIPIRX1N__KEY_ROW3 6 +#define FMUX_SEL_PAD_MIPIRX1N__DBG_8 7 +#define FMUX_SEL_PAD_MIPIRX1P__VI0_D_6 1 +#define FMUX_SEL_PAD_MIPIRX1P__XGPIOC_9 3 +#define FMUX_SEL_PAD_MIPIRX1P__IIC1_SDA 4 +#define FMUX_SEL_PAD_MIPIRX1P__KEY_ROW2 6 +#define FMUX_SEL_PAD_MIPIRX1P__DBG_9 7 +#define FMUX_SEL_PAD_MIPIRX0N__VI0_D_7 1 +#define FMUX_SEL_PAD_MIPIRX0N__XGPIOC_10 3 +#define FMUX_SEL_PAD_MIPIRX0N__IIC1_SCL 4 +#define FMUX_SEL_PAD_MIPIRX0N__CAM_MCLK1 5 +#define FMUX_SEL_PAD_MIPIRX0N__DBG_10 7 +#define FMUX_SEL_PAD_MIPIRX0P__VI0_D_8 1 +#define FMUX_SEL_PAD_MIPIRX0P__XGPIOC_11 3 +#define FMUX_SEL_PAD_MIPIRX0P__CAM_MCLK0 4 +#define FMUX_SEL_PAD_MIPIRX0P__DBG_11 7 +#define FMUX_SEL_PAD_MIPI_TXM2__VI0_D_13 1 +#define FMUX_SEL_PAD_MIPI_TXM2__IIC0_SDA 2 +#define FMUX_SEL_PAD_MIPI_TXM2__XGPIOC_16 3 +#define FMUX_SEL_PAD_MIPI_TXM2__IIC1_SDA 4 +#define FMUX_SEL_PAD_MIPI_TXM2__PWM_8 5 +#define FMUX_SEL_PAD_MIPI_TXM2__SPI0_SCK 6 +#define FMUX_SEL_PAD_MIPI_TXP2__VI0_D_14 1 +#define FMUX_SEL_PAD_MIPI_TXP2__IIC0_SCL 2 +#define FMUX_SEL_PAD_MIPI_TXP2__XGPIOC_17 3 +#define FMUX_SEL_PAD_MIPI_TXP2__IIC1_SCL 4 +#define FMUX_SEL_PAD_MIPI_TXP2__PWM_9 5 +#define FMUX_SEL_PAD_MIPI_TXP2__SPI0_CS_X 6 +#define FMUX_SEL_PAD_MIPI_TXP2__IIS1_MCLK 7 +#define FMUX_SEL_PAD_MIPI_TXM1__SPI3_SDO 0 +#define FMUX_SEL_PAD_MIPI_TXM1__VI0_D_11 1 +#define FMUX_SEL_PAD_MIPI_TXM1__IIS1_LRCK 2 +#define FMUX_SEL_PAD_MIPI_TXM1__XGPIOC_14 3 +#define FMUX_SEL_PAD_MIPI_TXM1__IIC2_SDA 4 +#define FMUX_SEL_PAD_MIPI_TXM1__PWM_10 5 +#define FMUX_SEL_PAD_MIPI_TXM1__SPI0_SDO 6 +#define FMUX_SEL_PAD_MIPI_TXM1__DBG_14 7 +#define FMUX_SEL_PAD_MIPI_TXP1__SPI3_SDI 0 +#define FMUX_SEL_PAD_MIPI_TXP1__VI0_D_12 1 +#define FMUX_SEL_PAD_MIPI_TXP1__IIS1_DO 2 +#define FMUX_SEL_PAD_MIPI_TXP1__XGPIOC_15 3 +#define FMUX_SEL_PAD_MIPI_TXP1__IIC2_SCL 4 +#define FMUX_SEL_PAD_MIPI_TXP1__PWM_11 5 +#define FMUX_SEL_PAD_MIPI_TXP1__SPI0_SDI 6 +#define FMUX_SEL_PAD_MIPI_TXP1__DBG_15 7 +#define FMUX_SEL_PAD_MIPI_TXM0__SPI3_SCK 0 +#define FMUX_SEL_PAD_MIPI_TXM0__VI0_D_9 1 +#define FMUX_SEL_PAD_MIPI_TXM0__IIS1_DI 2 +#define FMUX_SEL_PAD_MIPI_TXM0__XGPIOC_12 3 +#define FMUX_SEL_PAD_MIPI_TXM0__CAM_MCLK1 4 +#define FMUX_SEL_PAD_MIPI_TXM0__PWM_14 5 +#define FMUX_SEL_PAD_MIPI_TXM0__CAM_VS0 6 +#define FMUX_SEL_PAD_MIPI_TXM0__DBG_12 7 +#define FMUX_SEL_PAD_MIPI_TXP0__SPI3_CS_X 0 +#define FMUX_SEL_PAD_MIPI_TXP0__VI0_D_10 1 +#define FMUX_SEL_PAD_MIPI_TXP0__IIS1_BCLK 2 +#define FMUX_SEL_PAD_MIPI_TXP0__XGPIOC_13 3 +#define FMUX_SEL_PAD_MIPI_TXP0__CAM_MCLK0 4 +#define FMUX_SEL_PAD_MIPI_TXP0__PWM_15 5 +#define FMUX_SEL_PAD_MIPI_TXP0__CAM_HS0 6 +#define FMUX_SEL_PAD_MIPI_TXP0__DBG_13 7 +#define FMUX_SEL_PKG_TYPE0__PKG_TYPE0 0 +#define FMUX_SEL_PKG_TYPE1__PKG_TYPE1 0 +#define FMUX_SEL_PKG_TYPE2__PKG_TYPE2 0 +#define FMUX_SEL_PAD_AUD_AINL_MIC__XGPIOC_23 3 +#define FMUX_SEL_PAD_AUD_AINL_MIC__IIS1_BCLK 4 +#define FMUX_SEL_PAD_AUD_AINL_MIC__IIS2_BCLK 5 +#define FMUX_SEL_PAD_AUD_AINR_MIC__XGPIOC_22 3 +#define FMUX_SEL_PAD_AUD_AINR_MIC__IIS1_DO 4 +#define FMUX_SEL_PAD_AUD_AINR_MIC__IIS2_DI 5 +#define FMUX_SEL_PAD_AUD_AINR_MIC__IIS1_DI 6 +#define FMUX_SEL_PAD_AUD_AOUTL__XGPIOC_25 3 +#define FMUX_SEL_PAD_AUD_AOUTL__IIS1_LRCK 4 +#define FMUX_SEL_PAD_AUD_AOUTL__IIS2_LRCK 5 +#define FMUX_SEL_PAD_AUD_AOUTR__XGPIOC_24 3 +#define FMUX_SEL_PAD_AUD_AOUTR__IIS1_DI 4 +#define FMUX_SEL_PAD_AUD_AOUTR__IIS2_DO 5 +#define FMUX_SEL_PAD_AUD_AOUTR__IIS1_DO 6 + +#endif /* ZEPHYR_DT_SOPHGO_CV180X_PINCTRL_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/sophgo-cv181x-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/sophgo-cv181x-pinctrl.h new file mode 100644 index 00000000000000..c589dd258eda21 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/sophgo-cv181x-pinctrl.h @@ -0,0 +1,782 @@ +/* + * Copyright (c) 2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DT_SOPHGO_CV181X_PINCTRL_H_ +#define ZEPHYR_DT_SOPHGO_CV181X_PINCTRL_H_ + +#include + +#define FMUX_IDX_CAM_MCLK0 0 +#define FMUX_IDX_CAM_PD0 1 +#define FMUX_IDX_CAM_RST0 2 +#define FMUX_IDX_CAM_MCLK1 3 +#define FMUX_IDX_CAM_PD1 4 +#define FMUX_IDX_IIC3_SCL 5 +#define FMUX_IDX_IIC3_SDA 6 +#define FMUX_IDX_SD0_CLK 7 +#define FMUX_IDX_SD0_CMD 8 +#define FMUX_IDX_SD0_D0 9 +#define FMUX_IDX_SD0_D1 10 +#define FMUX_IDX_SD0_D2 11 +#define FMUX_IDX_SD0_D3 12 +#define FMUX_IDX_SD0_CD 13 +#define FMUX_IDX_SD0_PWR_EN 14 +#define FMUX_IDX_SPK_EN 15 +#define FMUX_IDX_UART0_TX 16 +#define FMUX_IDX_UART0_RX 17 +#define FMUX_IDX_EMMC_RSTN 18 +#define FMUX_IDX_EMMC_DAT2 19 +#define FMUX_IDX_EMMC_CLK 20 +#define FMUX_IDX_EMMC_DAT0 21 +#define FMUX_IDX_EMMC_DAT3 22 +#define FMUX_IDX_EMMC_CMD 23 +#define FMUX_IDX_EMMC_DAT1 24 +#define FMUX_IDX_JTAG_CPU_TMS 25 +#define FMUX_IDX_JTAG_CPU_TCK 26 +#define FMUX_IDX_JTAG_CPU_TRST 27 +#define FMUX_IDX_IIC0_SCL 28 +#define FMUX_IDX_IIC0_SDA 29 +#define FMUX_IDX_AUX0 30 +#define FMUX_IDX_PWR_VBAT_DET 31 +#define FMUX_IDX_PWR_RSTN 32 +#define FMUX_IDX_PWR_SEQ1 33 +#define FMUX_IDX_PWR_SEQ2 34 +#define FMUX_IDX_PWR_SEQ3 35 +#define FMUX_IDX_PWR_WAKEUP0 36 +#define FMUX_IDX_PWR_WAKEUP1 37 +#define FMUX_IDX_PWR_BUTTON1 38 +#define FMUX_IDX_PWR_ON 39 +#define FMUX_IDX_XTAL_XIN 40 +#define FMUX_IDX_PWR_GPIO0 41 +#define FMUX_IDX_PWR_GPIO1 42 +#define FMUX_IDX_PWR_GPIO2 43 +#define FMUX_IDX_CLK32K 44 +#define FMUX_IDX_CLK25M 45 +#define FMUX_IDX_IIC2_SCL 46 +#define FMUX_IDX_IIC2_SDA 47 +#define FMUX_IDX_UART2_TX 48 +#define FMUX_IDX_UART2_RTS 49 +#define FMUX_IDX_UART2_RX 50 +#define FMUX_IDX_UART2_CTS 51 +#define FMUX_IDX_SD1_D3 52 +#define FMUX_IDX_SD1_D2 53 +#define FMUX_IDX_SD1_D1 54 +#define FMUX_IDX_SD1_D0 55 +#define FMUX_IDX_SD1_CMD 56 +#define FMUX_IDX_SD1_CLK 57 +#define FMUX_IDX_RSTN 58 +#define FMUX_IDX_PWM0_BUCK 59 +#define FMUX_IDX_ADC3 60 +#define FMUX_IDX_ADC2 61 +#define FMUX_IDX_ADC1 62 +#define FMUX_IDX_USB_ID 63 +#define FMUX_IDX_USB_VBUS_EN 64 +#define FMUX_IDX_PKG_TYPE0 65 +#define FMUX_IDX_USB_VBUS_DET 66 +#define FMUX_IDX_PKG_TYPE1 67 +#define FMUX_IDX_PKG_TYPE2 68 +#define FMUX_IDX_MUX_SPI1_MISO 69 +#define FMUX_IDX_MUX_SPI1_MOSI 70 +#define FMUX_IDX_MUX_SPI1_CS 71 +#define FMUX_IDX_MUX_SPI1_SCK 72 +#define FMUX_IDX_PAD_ETH_TXM 73 +#define FMUX_IDX_PAD_ETH_TXP 74 +#define FMUX_IDX_PAD_ETH_RXM 75 +#define FMUX_IDX_PAD_ETH_RXP 76 +#define FMUX_IDX_VIVO_D10 77 +#define FMUX_IDX_VIVO_D9 78 +#define FMUX_IDX_VIVO_D8 79 +#define FMUX_IDX_VIVO_D7 80 +#define FMUX_IDX_VIVO_D6 81 +#define FMUX_IDX_VIVO_D5 82 +#define FMUX_IDX_VIVO_D4 83 +#define FMUX_IDX_VIVO_D3 84 +#define FMUX_IDX_VIVO_D2 85 +#define FMUX_IDX_VIVO_D1 86 +#define FMUX_IDX_VIVO_D0 87 +#define FMUX_IDX_VIVO_CLK 88 +#define FMUX_IDX_PAD_MIPIRX5N 89 +#define FMUX_IDX_PAD_MIPIRX5P 90 +#define FMUX_IDX_PAD_MIPIRX4N 91 +#define FMUX_IDX_PAD_MIPIRX4P 92 +#define FMUX_IDX_PAD_MIPIRX3N 93 +#define FMUX_IDX_PAD_MIPIRX3P 94 +#define FMUX_IDX_PAD_MIPIRX2N 95 +#define FMUX_IDX_PAD_MIPIRX2P 96 +#define FMUX_IDX_PAD_MIPIRX1N 97 +#define FMUX_IDX_PAD_MIPIRX1P 98 +#define FMUX_IDX_PAD_MIPIRX0N 99 +#define FMUX_IDX_PAD_MIPIRX0P 100 +#define FMUX_IDX_PAD_MIPI_TXM4 101 +#define FMUX_IDX_PAD_MIPI_TXP4 102 +#define FMUX_IDX_PAD_MIPI_TXM3 103 +#define FMUX_IDX_PAD_MIPI_TXP3 104 +#define FMUX_IDX_PAD_MIPI_TXM2 105 +#define FMUX_IDX_PAD_MIPI_TXP2 106 +#define FMUX_IDX_PAD_MIPI_TXM1 107 +#define FMUX_IDX_PAD_MIPI_TXP1 108 +#define FMUX_IDX_PAD_MIPI_TXM0 109 +#define FMUX_IDX_PAD_MIPI_TXP0 110 +#define FMUX_IDX_PAD_AUD_AINL_MIC 111 +#define FMUX_IDX_PAD_AUD_AINR_MIC 112 +#define FMUX_IDX_PAD_AUD_AOUTL 113 +#define FMUX_IDX_PAD_AUD_AOUTR 114 +#define FMUX_IDX_GPIO_RTX 115 +#define FMUX_IDX_GPIO_ZQ 116 + +#define FMUX_SEL_CAM_MCLK0__CAM_MCLK0 0 +#define FMUX_SEL_CAM_MCLK0__AUX1 2 +#define FMUX_SEL_CAM_MCLK0__XGPIOA_0 3 +#define FMUX_SEL_CAM_PD0__IIS1_MCLK 1 +#define FMUX_SEL_CAM_PD0__XGPIOA_1 3 +#define FMUX_SEL_CAM_PD0__CAM_HS0 4 +#define FMUX_SEL_CAM_RST0__XGPIOA_2 3 +#define FMUX_SEL_CAM_RST0__CAM_VS0 4 +#define FMUX_SEL_CAM_RST0__IIC4_SCL 6 +#define FMUX_SEL_CAM_MCLK1__CAM_MCLK1 0 +#define FMUX_SEL_CAM_MCLK1__AUX2 2 +#define FMUX_SEL_CAM_MCLK1__XGPIOA_3 3 +#define FMUX_SEL_CAM_MCLK1__CAM_HS0 4 +#define FMUX_SEL_CAM_PD1__IIS1_MCLK 1 +#define FMUX_SEL_CAM_PD1__XGPIOA_4 3 +#define FMUX_SEL_CAM_PD1__CAM_VS0 4 +#define FMUX_SEL_CAM_PD1__IIC4_SDA 6 +#define FMUX_SEL_IIC3_SCL__IIC3_SCL 0 +#define FMUX_SEL_IIC3_SCL__XGPIOA_5 3 +#define FMUX_SEL_IIC3_SDA__IIC3_SDA 0 +#define FMUX_SEL_IIC3_SDA__XGPIOA_6 3 +#define FMUX_SEL_SD0_CLK__SDIO0_CLK 0 +#define FMUX_SEL_SD0_CLK__IIC1_SDA 1 +#define FMUX_SEL_SD0_CLK__SPI0_SCK 2 +#define FMUX_SEL_SD0_CLK__XGPIOA_7 3 +#define FMUX_SEL_SD0_CLK__PWM_15 5 +#define FMUX_SEL_SD0_CLK__EPHY_LNK_LED 6 +#define FMUX_SEL_SD0_CLK__DBG_0 7 +#define FMUX_SEL_SD0_CMD__SDIO0_CMD 0 +#define FMUX_SEL_SD0_CMD__IIC1_SCL 1 +#define FMUX_SEL_SD0_CMD__SPI0_SDO 2 +#define FMUX_SEL_SD0_CMD__XGPIOA_8 3 +#define FMUX_SEL_SD0_CMD__PWM_14 5 +#define FMUX_SEL_SD0_CMD__EPHY_SPD_LED 6 +#define FMUX_SEL_SD0_CMD__DBG_1 7 +#define FMUX_SEL_SD0_D0__SDIO0_D_0 0 +#define FMUX_SEL_SD0_D0__CAM_MCLK1 1 +#define FMUX_SEL_SD0_D0__SPI0_SDI 2 +#define FMUX_SEL_SD0_D0__XGPIOA_9 3 +#define FMUX_SEL_SD0_D0__UART3_TX 4 +#define FMUX_SEL_SD0_D0__PWM_13 5 +#define FMUX_SEL_SD0_D0__WG0_D0 6 +#define FMUX_SEL_SD0_D0__DBG_2 7 +#define FMUX_SEL_SD0_D1__SDIO0_D_1 0 +#define FMUX_SEL_SD0_D1__IIC1_SDA 1 +#define FMUX_SEL_SD0_D1__AUX0 2 +#define FMUX_SEL_SD0_D1__XGPIOA_10 3 +#define FMUX_SEL_SD0_D1__UART1_TX 4 +#define FMUX_SEL_SD0_D1__PWM_12 5 +#define FMUX_SEL_SD0_D1__WG0_D1 6 +#define FMUX_SEL_SD0_D1__DBG_3 7 +#define FMUX_SEL_SD0_D2__SDIO0_D_2 0 +#define FMUX_SEL_SD0_D2__IIC1_SCL 1 +#define FMUX_SEL_SD0_D2__AUX1 2 +#define FMUX_SEL_SD0_D2__XGPIOA_11 3 +#define FMUX_SEL_SD0_D2__UART1_RX 4 +#define FMUX_SEL_SD0_D2__PWM_11 5 +#define FMUX_SEL_SD0_D2__WG1_D0 6 +#define FMUX_SEL_SD0_D2__DBG_4 7 +#define FMUX_SEL_SD0_D3__SDIO0_D_3 0 +#define FMUX_SEL_SD0_D3__CAM_MCLK0 1 +#define FMUX_SEL_SD0_D3__SPI0_CS_X 2 +#define FMUX_SEL_SD0_D3__XGPIOA_12 3 +#define FMUX_SEL_SD0_D3__UART3_RX 4 +#define FMUX_SEL_SD0_D3__PWM_10 5 +#define FMUX_SEL_SD0_D3__WG1_D1 6 +#define FMUX_SEL_SD0_D3__DBG_5 7 +#define FMUX_SEL_SD0_CD__SDIO0_CD 0 +#define FMUX_SEL_SD0_CD__XGPIOA_13 3 +#define FMUX_SEL_SD0_PWR_EN__SDIO0_PWR_EN 0 +#define FMUX_SEL_SD0_PWR_EN__XGPIOA_14 3 +#define FMUX_SEL_SPK_EN__XGPIOA_15 3 +#define FMUX_SEL_UART0_TX__UART0_TX 0 +#define FMUX_SEL_UART0_TX__CAM_MCLK1 1 +#define FMUX_SEL_UART0_TX__PWM_4 2 +#define FMUX_SEL_UART0_TX__XGPIOA_16 3 +#define FMUX_SEL_UART0_TX__UART1_TX 4 +#define FMUX_SEL_UART0_TX__AUX1 5 +#define FMUX_SEL_UART0_TX__DBG_6 7 +#define FMUX_SEL_UART0_RX__UART0_RX 0 +#define FMUX_SEL_UART0_RX__CAM_MCLK0 1 +#define FMUX_SEL_UART0_RX__PWM_5 2 +#define FMUX_SEL_UART0_RX__XGPIOA_17 3 +#define FMUX_SEL_UART0_RX__UART1_RX 4 +#define FMUX_SEL_UART0_RX__AUX0 5 +#define FMUX_SEL_UART0_RX__DBG_7 7 +#define FMUX_SEL_EMMC_RSTN__EMMC_RSTN 0 +#define FMUX_SEL_EMMC_RSTN__XGPIOA_21 3 +#define FMUX_SEL_EMMC_RSTN__AUX2 4 +#define FMUX_SEL_EMMC_DAT2__EMMC_DAT_2 0 +#define FMUX_SEL_EMMC_DAT2__SPINOR_HOLD_X 1 +#define FMUX_SEL_EMMC_DAT2__SPINAND_HOLD 2 +#define FMUX_SEL_EMMC_DAT2__XGPIOA_26 3 +#define FMUX_SEL_EMMC_CLK__EMMC_CLK 0 +#define FMUX_SEL_EMMC_CLK__SPINOR_SCK 1 +#define FMUX_SEL_EMMC_CLK__SPINAND_CLK 2 +#define FMUX_SEL_EMMC_CLK__XGPIOA_22 3 +#define FMUX_SEL_EMMC_DAT0__EMMC_DAT_0 0 +#define FMUX_SEL_EMMC_DAT0__SPINOR_MOSI 1 +#define FMUX_SEL_EMMC_DAT0__SPINAND_MOSI 2 +#define FMUX_SEL_EMMC_DAT0__XGPIOA_25 3 +#define FMUX_SEL_EMMC_DAT3__EMMC_DAT_3 0 +#define FMUX_SEL_EMMC_DAT3__SPINOR_WP_X 1 +#define FMUX_SEL_EMMC_DAT3__SPINAND_WP 2 +#define FMUX_SEL_EMMC_DAT3__XGPIOA_27 3 +#define FMUX_SEL_EMMC_CMD__EMMC_CMD 0 +#define FMUX_SEL_EMMC_CMD__SPINOR_MISO 1 +#define FMUX_SEL_EMMC_CMD__SPINAND_MISO 2 +#define FMUX_SEL_EMMC_CMD__XGPIOA_23 3 +#define FMUX_SEL_EMMC_DAT1__EMMC_DAT_1 0 +#define FMUX_SEL_EMMC_DAT1__SPINOR_CS_X 1 +#define FMUX_SEL_EMMC_DAT1__SPINAND_CS 2 +#define FMUX_SEL_EMMC_DAT1__XGPIOA_24 3 +#define FMUX_SEL_JTAG_CPU_TMS__JTAG_CPU_TMS 0 +#define FMUX_SEL_JTAG_CPU_TMS__CAM_MCLK0 1 +#define FMUX_SEL_JTAG_CPU_TMS__PWM_7 2 +#define FMUX_SEL_JTAG_CPU_TMS__XGPIOA_19 3 +#define FMUX_SEL_JTAG_CPU_TMS__UART1_RTS 4 +#define FMUX_SEL_JTAG_CPU_TMS__AUX0 5 +#define FMUX_SEL_JTAG_CPU_TMS__UART1_TX 6 +#define FMUX_SEL_JTAG_CPU_TMS__VO_D_28 7 +#define FMUX_SEL_JTAG_CPU_TCK__JTAG_CPU_TCK 0 +#define FMUX_SEL_JTAG_CPU_TCK__CAM_MCLK1 1 +#define FMUX_SEL_JTAG_CPU_TCK__PWM_6 2 +#define FMUX_SEL_JTAG_CPU_TCK__XGPIOA_18 3 +#define FMUX_SEL_JTAG_CPU_TCK__UART1_CTS 4 +#define FMUX_SEL_JTAG_CPU_TCK__AUX1 5 +#define FMUX_SEL_JTAG_CPU_TCK__UART1_RX 6 +#define FMUX_SEL_JTAG_CPU_TCK__VO_D_29 7 +#define FMUX_SEL_JTAG_CPU_TRST__JTAG_CPU_TRST 0 +#define FMUX_SEL_JTAG_CPU_TRST__XGPIOA_20 3 +#define FMUX_SEL_JTAG_CPU_TRST__VO_D_30 6 +#define FMUX_SEL_IIC0_SCL__IIC0_SCL 0 +#define FMUX_SEL_IIC0_SCL__UART1_TX 1 +#define FMUX_SEL_IIC0_SCL__UART2_TX 2 +#define FMUX_SEL_IIC0_SCL__XGPIOA_28 3 +#define FMUX_SEL_IIC0_SCL__WG0_D0 5 +#define FMUX_SEL_IIC0_SCL__DBG_10 7 +#define FMUX_SEL_IIC0_SDA__IIC0_SDA 0 +#define FMUX_SEL_IIC0_SDA__UART1_RX 1 +#define FMUX_SEL_IIC0_SDA__UART2_RX 2 +#define FMUX_SEL_IIC0_SDA__XGPIOA_29 3 +#define FMUX_SEL_IIC0_SDA__WG0_D1 5 +#define FMUX_SEL_IIC0_SDA__WG1_D0 6 +#define FMUX_SEL_IIC0_SDA__DBG_11 7 +#define FMUX_SEL_AUX0__AUX0 0 +#define FMUX_SEL_AUX0__XGPIOA_30 3 +#define FMUX_SEL_AUX0__IIS1_MCLK 4 +#define FMUX_SEL_AUX0__VO_D_31 5 +#define FMUX_SEL_AUX0__WG1_D1 6 +#define FMUX_SEL_AUX0__DBG_12 7 +#define FMUX_SEL_PWR_VBAT_DET__PWR_VBAT_DET 0 +#define FMUX_SEL_PWR_RSTN__PWR_RSTN 0 +#define FMUX_SEL_PWR_SEQ1__PWR_SEQ1 0 +#define FMUX_SEL_PWR_SEQ1__PWR_GPIO_3 3 +#define FMUX_SEL_PWR_SEQ2__PWR_SEQ2 0 +#define FMUX_SEL_PWR_SEQ2__PWR_GPIO_4 3 +#define FMUX_SEL_PWR_SEQ3__PWR_SEQ3 0 +#define FMUX_SEL_PWR_SEQ3__PWR_GPIO_5 3 +#define FMUX_SEL_PTEST__PWR_PTEST 0 +#define FMUX_SEL_PWR_WAKEUP0__PWR_WAKEUP0 0 +#define FMUX_SEL_PWR_WAKEUP0__PWR_IR0 1 +#define FMUX_SEL_PWR_WAKEUP0__PWR_UART0_TX 2 +#define FMUX_SEL_PWR_WAKEUP0__PWR_GPIO_6 3 +#define FMUX_SEL_PWR_WAKEUP0__UART1_TX 4 +#define FMUX_SEL_PWR_WAKEUP0__IIC4_SCL 5 +#define FMUX_SEL_PWR_WAKEUP0__EPHY_LNK_LED 6 +#define FMUX_SEL_PWR_WAKEUP0__WG2_D0 7 +#define FMUX_SEL_PWR_WAKEUP1__PWR_WAKEUP1 0 +#define FMUX_SEL_PWR_WAKEUP1__PWR_IR1 1 +#define FMUX_SEL_PWR_WAKEUP1__PWR_GPIO_7 3 +#define FMUX_SEL_PWR_WAKEUP1__UART1_TX 4 +#define FMUX_SEL_PWR_WAKEUP1__IIC4_SCL 5 +#define FMUX_SEL_PWR_WAKEUP1__EPHY_LNK_LED 6 +#define FMUX_SEL_PWR_WAKEUP1__WG0_D0 7 +#define FMUX_SEL_PWR_BUTTON1__PWR_BUTTON1 0 +#define FMUX_SEL_PWR_BUTTON1__PWR_GPIO_8 3 +#define FMUX_SEL_PWR_BUTTON1__UART1_RX 4 +#define FMUX_SEL_PWR_BUTTON1__IIC4_SDA 5 +#define FMUX_SEL_PWR_BUTTON1__EPHY_SPD_LED 6 +#define FMUX_SEL_PWR_BUTTON1__WG2_D1 7 +#define FMUX_SEL_PWR_ON__PWR_ON 0 +#define FMUX_SEL_PWR_ON__PWR_GPIO_9 3 +#define FMUX_SEL_PWR_ON__UART1_RX 4 +#define FMUX_SEL_PWR_ON__IIC4_SDA 5 +#define FMUX_SEL_PWR_ON__EPHY_SPD_LED 6 +#define FMUX_SEL_PWR_ON__WG0_D1 7 +#define FMUX_SEL_XTAL_XIN__PWR_XTAL_CLKIN 0 +#define FMUX_SEL_PWR_GPIO0__PWR_GPIO_0 0 +#define FMUX_SEL_PWR_GPIO0__UART2_TX 1 +#define FMUX_SEL_PWR_GPIO0__PWR_UART0_RX 2 +#define FMUX_SEL_PWR_GPIO0__PWM_8 4 +#define FMUX_SEL_PWR_GPIO1__PWR_GPIO_1 0 +#define FMUX_SEL_PWR_GPIO1__UART2_RX 1 +#define FMUX_SEL_PWR_GPIO1__EPHY_LNK_LED 3 +#define FMUX_SEL_PWR_GPIO1__PWM_9 4 +#define FMUX_SEL_PWR_GPIO1__PWR_IIC_SCL 5 +#define FMUX_SEL_PWR_GPIO1__IIC2_SCL 6 +#define FMUX_SEL_PWR_GPIO1__PWR_MCU_JTAG_TMS 7 +#define FMUX_SEL_PWR_GPIO2__PWR_GPIO_2 0 +#define FMUX_SEL_PWR_GPIO2__PWR_SECTICK 2 +#define FMUX_SEL_PWR_GPIO2__EPHY_SPD_LED 3 +#define FMUX_SEL_PWR_GPIO2__PWM_10 4 +#define FMUX_SEL_PWR_GPIO2__PWR_IIC_SDA 5 +#define FMUX_SEL_PWR_GPIO2__IIC2_SDA 6 +#define FMUX_SEL_PWR_GPIO2__PWR_MCU_JTAG_TCK 7 +#define FMUX_SEL_CLK32K__CLK32K 0 +#define FMUX_SEL_CLK32K__AUX0 1 +#define FMUX_SEL_CLK32K__PWR_MCU_JTAG_TDI 2 +#define FMUX_SEL_CLK32K__PWR_GPIO_10 3 +#define FMUX_SEL_CLK32K__PWM_2 4 +#define FMUX_SEL_CLK32K__KEY_COL0 5 +#define FMUX_SEL_CLK32K__CAM_MCLK0 6 +#define FMUX_SEL_CLK32K__DBG_0 7 +#define FMUX_SEL_CLK25M__CLK25M 0 +#define FMUX_SEL_CLK25M__AUX1 1 +#define FMUX_SEL_CLK25M__PWR_MCU_JTAG_TDO 2 +#define FMUX_SEL_CLK25M__PWR_GPIO_11 3 +#define FMUX_SEL_CLK25M__PWM_3 4 +#define FMUX_SEL_CLK25M__KEY_COL1 5 +#define FMUX_SEL_CLK25M__CAM_MCLK1 6 +#define FMUX_SEL_CLK25M__DBG_1 7 +#define FMUX_SEL_IIC2_SCL__IIC2_SCL 0 +#define FMUX_SEL_IIC2_SCL__PWM_14 1 +#define FMUX_SEL_IIC2_SCL__PWR_GPIO_12 3 +#define FMUX_SEL_IIC2_SCL__UART2_RX 4 +#define FMUX_SEL_IIC2_SCL__KEY_COL2 7 +#define FMUX_SEL_IIC2_SDA__IIC2_SDA 0 +#define FMUX_SEL_IIC2_SDA__PWM_15 1 +#define FMUX_SEL_IIC2_SDA__PWR_GPIO_13 3 +#define FMUX_SEL_IIC2_SDA__UART2_TX 4 +#define FMUX_SEL_IIC2_SDA__IIS1_MCLK 5 +#define FMUX_SEL_IIC2_SDA__IIS2_MCLK 6 +#define FMUX_SEL_IIC2_SDA__KEY_COL3 7 +#define FMUX_SEL_UART2_TX__UART2_TX 0 +#define FMUX_SEL_UART2_TX__PWM_11 1 +#define FMUX_SEL_UART2_TX__PWR_UART1_TX 2 +#define FMUX_SEL_UART2_TX__PWR_GPIO_14 3 +#define FMUX_SEL_UART2_TX__KEY_ROW3 4 +#define FMUX_SEL_UART2_TX__UART4_TX 5 +#define FMUX_SEL_UART2_TX__IIS2_BCLK 6 +#define FMUX_SEL_UART2_TX__WG2_D0 7 +#define FMUX_SEL_UART2_RTS__UART2_RTS 0 +#define FMUX_SEL_UART2_RTS__PWM_8 1 +#define FMUX_SEL_UART2_RTS__PWR_GPIO_15 3 +#define FMUX_SEL_UART2_RTS__KEY_ROW0 4 +#define FMUX_SEL_UART2_RTS__UART4_RTS 5 +#define FMUX_SEL_UART2_RTS__IIS2_DO 6 +#define FMUX_SEL_UART2_RTS__WG1_D0 7 +#define FMUX_SEL_UART2_RX__UART2_RX 0 +#define FMUX_SEL_UART2_RX__PWM_10 1 +#define FMUX_SEL_UART2_RX__PWR_UART1_RX 2 +#define FMUX_SEL_UART2_RX__PWR_GPIO_16 3 +#define FMUX_SEL_UART2_RX__KEY_COL3 4 +#define FMUX_SEL_UART2_RX__UART4_RX 5 +#define FMUX_SEL_UART2_RX__IIS2_DI 6 +#define FMUX_SEL_UART2_RX__WG2_D1 7 +#define FMUX_SEL_UART2_CTS__UART2_CTS 0 +#define FMUX_SEL_UART2_CTS__PWM_9 1 +#define FMUX_SEL_UART2_CTS__PWR_GPIO_17 3 +#define FMUX_SEL_UART2_CTS__KEY_ROW1 4 +#define FMUX_SEL_UART2_CTS__UART4_CTS 5 +#define FMUX_SEL_UART2_CTS__IIS2_LRCK 6 +#define FMUX_SEL_UART2_CTS__WG1_D1 7 +#define FMUX_SEL_SD1_D3__PWR_SD1_D3_VO32 0 +#define FMUX_SEL_SD1_D3__SPI2_CS_X 1 +#define FMUX_SEL_SD1_D3__IIC1_SCL 2 +#define FMUX_SEL_SD1_D3__PWR_GPIO_18 3 +#define FMUX_SEL_SD1_D3__CAM_MCLK0 4 +#define FMUX_SEL_SD1_D3__UART3_CTS 5 +#define FMUX_SEL_SD1_D3__PWR_SPINOR1_CS_X 6 +#define FMUX_SEL_SD1_D3__PWM_4 7 +#define FMUX_SEL_SD1_D2__PWR_SD1_D2_VO33 0 +#define FMUX_SEL_SD1_D2__IIC1_SCL 1 +#define FMUX_SEL_SD1_D2__UART2_TX 2 +#define FMUX_SEL_SD1_D2__PWR_GPIO_19 3 +#define FMUX_SEL_SD1_D2__CAM_MCLK0 4 +#define FMUX_SEL_SD1_D2__UART3_TX 5 +#define FMUX_SEL_SD1_D2__PWR_SPINOR1_HOLD_X 6 +#define FMUX_SEL_SD1_D2__PWM_5 7 +#define FMUX_SEL_SD1_D1__PWR_SD1_D1_VO34 0 +#define FMUX_SEL_SD1_D1__IIC1_SDA 1 +#define FMUX_SEL_SD1_D1__UART2_RX 2 +#define FMUX_SEL_SD1_D1__PWR_GPIO_20 3 +#define FMUX_SEL_SD1_D1__CAM_MCLK1 4 +#define FMUX_SEL_SD1_D1__UART3_RX 5 +#define FMUX_SEL_SD1_D1__PWR_SPINOR1_WP_X 6 +#define FMUX_SEL_SD1_D1__PWM_6 7 +#define FMUX_SEL_SD1_D0__PWR_SD1_D0_VO35 0 +#define FMUX_SEL_SD1_D0__SPI2_SDI 1 +#define FMUX_SEL_SD1_D0__IIC1_SDA 2 +#define FMUX_SEL_SD1_D0__PWR_GPIO_21 3 +#define FMUX_SEL_SD1_D0__CAM_MCLK1 4 +#define FMUX_SEL_SD1_D0__UART3_RTS 5 +#define FMUX_SEL_SD1_D0__PWR_SPINOR1_MISO 6 +#define FMUX_SEL_SD1_D0__PWM_7 7 +#define FMUX_SEL_SD1_CMD__PWR_SD1_CMD_VO36 0 +#define FMUX_SEL_SD1_CMD__SPI2_SDO 1 +#define FMUX_SEL_SD1_CMD__IIC3_SCL 2 +#define FMUX_SEL_SD1_CMD__PWR_GPIO_22 3 +#define FMUX_SEL_SD1_CMD__CAM_VS0 4 +#define FMUX_SEL_SD1_CMD__EPHY_LNK_LED 5 +#define FMUX_SEL_SD1_CMD__PWR_SPINOR1_MOSI 6 +#define FMUX_SEL_SD1_CMD__PWM_8 7 +#define FMUX_SEL_SD1_CLK__PWR_SD1_CLK_VO37 0 +#define FMUX_SEL_SD1_CLK__SPI2_SCK 1 +#define FMUX_SEL_SD1_CLK__IIC3_SDA 2 +#define FMUX_SEL_SD1_CLK__PWR_GPIO_23 3 +#define FMUX_SEL_SD1_CLK__CAM_HS0 4 +#define FMUX_SEL_SD1_CLK__EPHY_SPD_LED 5 +#define FMUX_SEL_SD1_CLK__PWR_SPINOR1_SCK 6 +#define FMUX_SEL_SD1_CLK__PWM_9 7 +#define FMUX_SEL_RSTN__RSTN 0 +#define FMUX_SEL_PWM0_BUCK__PWM_0 0 +#define FMUX_SEL_PWM0_BUCK__XGPIOB_0 3 +#define FMUX_SEL_ADC3__CAM_MCLK0 1 +#define FMUX_SEL_ADC3__IIC4_SCL 2 +#define FMUX_SEL_ADC3__XGPIOB_1 3 +#define FMUX_SEL_ADC3__PWM_12 4 +#define FMUX_SEL_ADC3__EPHY_LNK_LED 5 +#define FMUX_SEL_ADC3__WG2_D0 6 +#define FMUX_SEL_ADC3__UART3_TX 7 +#define FMUX_SEL_ADC2__CAM_MCLK1 1 +#define FMUX_SEL_ADC2__IIC4_SDA 2 +#define FMUX_SEL_ADC2__XGPIOB_2 3 +#define FMUX_SEL_ADC2__PWM_13 4 +#define FMUX_SEL_ADC2__EPHY_SPD_LED 5 +#define FMUX_SEL_ADC2__WG2_D1 6 +#define FMUX_SEL_ADC2__UART3_RX 7 +#define FMUX_SEL_ADC1__XGPIOB_3 3 +#define FMUX_SEL_ADC1__KEY_COL2 4 +#define FMUX_SEL_USB_ID__USB_ID 0 +#define FMUX_SEL_USB_ID__XGPIOB_4 3 +#define FMUX_SEL_USB_VBUS_EN__USB_VBUS_EN 0 +#define FMUX_SEL_USB_VBUS_EN__XGPIOB_5 3 +#define FMUX_SEL_PKG_TYPE0__PKG_TYPE0 0 +#define FMUX_SEL_USB_VBUS_DET__USB_VBUS_DET 0 +#define FMUX_SEL_USB_VBUS_DET__XGPIOB_6 3 +#define FMUX_SEL_USB_VBUS_DET__CAM_MCLK0 4 +#define FMUX_SEL_USB_VBUS_DET__CAM_MCLK1 5 +#define FMUX_SEL_PKG_TYPE1__PKG_TYPE1 0 +#define FMUX_SEL_PKG_TYPE2__PKG_TYPE2 0 +#define FMUX_SEL_MUX_SPI1_MISO__UART3_RTS 1 +#define FMUX_SEL_MUX_SPI1_MISO__IIC1_SDA 2 +#define FMUX_SEL_MUX_SPI1_MISO__XGPIOB_8 3 +#define FMUX_SEL_MUX_SPI1_MISO__PWM_9 4 +#define FMUX_SEL_MUX_SPI1_MISO__KEY_COL1 5 +#define FMUX_SEL_MUX_SPI1_MISO__SPI1_SDI 6 +#define FMUX_SEL_MUX_SPI1_MISO__DBG_14 7 +#define FMUX_SEL_MUX_SPI1_MOSI__UART3_RX 1 +#define FMUX_SEL_MUX_SPI1_MOSI__IIC1_SCL 2 +#define FMUX_SEL_MUX_SPI1_MOSI__XGPIOB_7 3 +#define FMUX_SEL_MUX_SPI1_MOSI__PWM_8 4 +#define FMUX_SEL_MUX_SPI1_MOSI__KEY_COL0 5 +#define FMUX_SEL_MUX_SPI1_MOSI__SPI1_SDO 6 +#define FMUX_SEL_MUX_SPI1_MOSI__DBG_13 7 +#define FMUX_SEL_MUX_SPI1_CS__UART3_CTS 1 +#define FMUX_SEL_MUX_SPI1_CS__CAM_MCLK0 2 +#define FMUX_SEL_MUX_SPI1_CS__XGPIOB_10 3 +#define FMUX_SEL_MUX_SPI1_CS__PWM_11 4 +#define FMUX_SEL_MUX_SPI1_CS__KEY_ROW3 5 +#define FMUX_SEL_MUX_SPI1_CS__SPI1_CS_X 6 +#define FMUX_SEL_MUX_SPI1_CS__DBG_16 7 +#define FMUX_SEL_MUX_SPI1_SCK__UART3_TX 1 +#define FMUX_SEL_MUX_SPI1_SCK__CAM_MCLK1 2 +#define FMUX_SEL_MUX_SPI1_SCK__XGPIOB_9 3 +#define FMUX_SEL_MUX_SPI1_SCK__PWM_10 4 +#define FMUX_SEL_MUX_SPI1_SCK__KEY_ROW2 5 +#define FMUX_SEL_MUX_SPI1_SCK__SPI1_SCK 6 +#define FMUX_SEL_MUX_SPI1_SCK__DBG_15 7 +#define FMUX_SEL_PAD_ETH_TXM__UART3_RTS 1 +#define FMUX_SEL_PAD_ETH_TXM__IIC1_SDA 2 +#define FMUX_SEL_PAD_ETH_TXM__XGPIOB_24 3 +#define FMUX_SEL_PAD_ETH_TXM__PWM_12 4 +#define FMUX_SEL_PAD_ETH_TXM__CAM_MCLK1 5 +#define FMUX_SEL_PAD_ETH_TXM__SPI1_SDI 6 +#define FMUX_SEL_PAD_ETH_TXM__IIS2_BCLK 7 +#define FMUX_SEL_PAD_ETH_TXP__UART3_RX 1 +#define FMUX_SEL_PAD_ETH_TXP__IIC1_SCL 2 +#define FMUX_SEL_PAD_ETH_TXP__XGPIOB_25 3 +#define FMUX_SEL_PAD_ETH_TXP__PWM_13 4 +#define FMUX_SEL_PAD_ETH_TXP__CAM_MCLK0 5 +#define FMUX_SEL_PAD_ETH_TXP__SPI1_SDO 6 +#define FMUX_SEL_PAD_ETH_TXP__IIS2_LRCK 7 +#define FMUX_SEL_PAD_ETH_RXM__UART3_CTS 1 +#define FMUX_SEL_PAD_ETH_RXM__CAM_MCLK0 2 +#define FMUX_SEL_PAD_ETH_RXM__XGPIOB_26 3 +#define FMUX_SEL_PAD_ETH_RXM__PWM_14 4 +#define FMUX_SEL_PAD_ETH_RXM__CAM_VS0 5 +#define FMUX_SEL_PAD_ETH_RXM__SPI1_CS_X 6 +#define FMUX_SEL_PAD_ETH_RXM__IIS2_DI 7 +#define FMUX_SEL_PAD_ETH_RXP__UART3_TX 1 +#define FMUX_SEL_PAD_ETH_RXP__CAM_MCLK1 2 +#define FMUX_SEL_PAD_ETH_RXP__XGPIOB_27 3 +#define FMUX_SEL_PAD_ETH_RXP__PWM_15 4 +#define FMUX_SEL_PAD_ETH_RXP__CAM_HS0 5 +#define FMUX_SEL_PAD_ETH_RXP__SPI1_SCK 6 +#define FMUX_SEL_PAD_ETH_RXP__IIS2_DO 7 +#define FMUX_SEL_VIVO_D10__PWM_1 0 +#define FMUX_SEL_VIVO_D10__VI1_D_10 1 +#define FMUX_SEL_VIVO_D10__VO_D_23 2 +#define FMUX_SEL_VIVO_D10__XGPIOB_11 3 +#define FMUX_SEL_VIVO_D10__RMII0_IRQ 4 +#define FMUX_SEL_VIVO_D10__CAM_MCLK0 5 +#define FMUX_SEL_VIVO_D10__IIC1_SDA 6 +#define FMUX_SEL_VIVO_D10__UART2_TX 7 +#define FMUX_SEL_VIVO_D9__PWM_2 0 +#define FMUX_SEL_VIVO_D9__VI1_D_9 1 +#define FMUX_SEL_VIVO_D9__VO_D_22 2 +#define FMUX_SEL_VIVO_D9__XGPIOB_12 3 +#define FMUX_SEL_VIVO_D9__CAM_MCLK1 5 +#define FMUX_SEL_VIVO_D9__IIC1_SCL 6 +#define FMUX_SEL_VIVO_D9__UART2_RX 7 +#define FMUX_SEL_VIVO_D8__PWM_3 0 +#define FMUX_SEL_VIVO_D8__VI1_D_8 1 +#define FMUX_SEL_VIVO_D8__VO_D_21 2 +#define FMUX_SEL_VIVO_D8__XGPIOB_13 3 +#define FMUX_SEL_VIVO_D8__RMII0_MDIO 4 +#define FMUX_SEL_VIVO_D8__SPI3_SDO 5 +#define FMUX_SEL_VIVO_D8__IIC2_SCL 6 +#define FMUX_SEL_VIVO_D8__CAM_VS0 7 +#define FMUX_SEL_VIVO_D7__VI2_D_7 0 +#define FMUX_SEL_VIVO_D7__VI1_D_7 1 +#define FMUX_SEL_VIVO_D7__VO_D_20 2 +#define FMUX_SEL_VIVO_D7__XGPIOB_14 3 +#define FMUX_SEL_VIVO_D7__RMII0_RXD1 4 +#define FMUX_SEL_VIVO_D7__SPI3_SDI 5 +#define FMUX_SEL_VIVO_D7__IIC2_SDA 6 +#define FMUX_SEL_VIVO_D7__CAM_HS0 7 +#define FMUX_SEL_VIVO_D6__VI2_D_6 0 +#define FMUX_SEL_VIVO_D6__VI1_D_6 1 +#define FMUX_SEL_VIVO_D6__VO_D_19 2 +#define FMUX_SEL_VIVO_D6__XGPIOB_15 3 +#define FMUX_SEL_VIVO_D6__RMII0_REFCLKI 4 +#define FMUX_SEL_VIVO_D6__SPI3_SCK 5 +#define FMUX_SEL_VIVO_D6__UART2_TX 6 +#define FMUX_SEL_VIVO_D6__CAM_VS0 7 +#define FMUX_SEL_VIVO_D5__VI2_D_5 0 +#define FMUX_SEL_VIVO_D5__VI1_D_5 1 +#define FMUX_SEL_VIVO_D5__VO_D_18 2 +#define FMUX_SEL_VIVO_D5__XGPIOB_16 3 +#define FMUX_SEL_VIVO_D5__RMII0_RXD0 4 +#define FMUX_SEL_VIVO_D5__SPI3_CS_X 5 +#define FMUX_SEL_VIVO_D5__UART2_RX 6 +#define FMUX_SEL_VIVO_D5__CAM_HS0 7 +#define FMUX_SEL_VIVO_D4__VI2_D_4 0 +#define FMUX_SEL_VIVO_D4__VI1_D_4 1 +#define FMUX_SEL_VIVO_D4__VO_D_17 2 +#define FMUX_SEL_VIVO_D4__XGPIOB_17 3 +#define FMUX_SEL_VIVO_D4__RMII0_MDC 4 +#define FMUX_SEL_VIVO_D4__IIC1_SDA 5 +#define FMUX_SEL_VIVO_D4__UART2_CTS 6 +#define FMUX_SEL_VIVO_D4__CAM_VS0 7 +#define FMUX_SEL_VIVO_D3__VI2_D_3 0 +#define FMUX_SEL_VIVO_D3__VI1_D_3 1 +#define FMUX_SEL_VIVO_D3__VO_D_16 2 +#define FMUX_SEL_VIVO_D3__XGPIOB_18 3 +#define FMUX_SEL_VIVO_D3__RMII0_TXD0 4 +#define FMUX_SEL_VIVO_D3__IIC1_SCL 5 +#define FMUX_SEL_VIVO_D3__UART2_RTS 6 +#define FMUX_SEL_VIVO_D3__CAM_HS0 7 +#define FMUX_SEL_VIVO_D2__VI2_D_2 0 +#define FMUX_SEL_VIVO_D2__VI1_D_2 1 +#define FMUX_SEL_VIVO_D2__VO_D_15 2 +#define FMUX_SEL_VIVO_D2__XGPIOB_19 3 +#define FMUX_SEL_VIVO_D2__RMII0_TXD1 4 +#define FMUX_SEL_VIVO_D2__CAM_MCLK1 5 +#define FMUX_SEL_VIVO_D2__PWM_2 6 +#define FMUX_SEL_VIVO_D2__UART2_TX 7 +#define FMUX_SEL_VIVO_D1__VI2_D_1 0 +#define FMUX_SEL_VIVO_D1__VI1_D_1 1 +#define FMUX_SEL_VIVO_D1__VO_D_14 2 +#define FMUX_SEL_VIVO_D1__XGPIOB_20 3 +#define FMUX_SEL_VIVO_D1__RMII0_RXDV 4 +#define FMUX_SEL_VIVO_D1__IIC3_SDA 5 +#define FMUX_SEL_VIVO_D1__PWM_3 6 +#define FMUX_SEL_VIVO_D1__IIC4_SCL 7 +#define FMUX_SEL_VIVO_D0__VI2_D_0 0 +#define FMUX_SEL_VIVO_D0__VI1_D_0 1 +#define FMUX_SEL_VIVO_D0__VO_D_13 2 +#define FMUX_SEL_VIVO_D0__XGPIOB_21 3 +#define FMUX_SEL_VIVO_D0__RMII0_TXCLK 4 +#define FMUX_SEL_VIVO_D0__IIC3_SCL 5 +#define FMUX_SEL_VIVO_D0__WG1_D0 6 +#define FMUX_SEL_VIVO_D0__IIC4_SDA 7 +#define FMUX_SEL_VIVO_CLK__VI2_CLK 0 +#define FMUX_SEL_VIVO_CLK__VI1_CLK 1 +#define FMUX_SEL_VIVO_CLK__VO_CLK1 2 +#define FMUX_SEL_VIVO_CLK__XGPIOB_22 3 +#define FMUX_SEL_VIVO_CLK__RMII0_TXEN 4 +#define FMUX_SEL_VIVO_CLK__CAM_MCLK0 5 +#define FMUX_SEL_VIVO_CLK__WG1_D1 6 +#define FMUX_SEL_VIVO_CLK__UART2_RX 7 +#define FMUX_SEL_PAD_MIPIRX5N__VI1_D_11 1 +#define FMUX_SEL_PAD_MIPIRX5N__VO_D_12 2 +#define FMUX_SEL_PAD_MIPIRX5N__XGPIOC_0 3 +#define FMUX_SEL_PAD_MIPIRX5N__CAM_MCLK0 5 +#define FMUX_SEL_PAD_MIPIRX5N__WG0_D0 6 +#define FMUX_SEL_PAD_MIPIRX5N__DBG_0 7 +#define FMUX_SEL_PAD_MIPIRX5P__VI1_D_12 1 +#define FMUX_SEL_PAD_MIPIRX5P__VO_D_11 2 +#define FMUX_SEL_PAD_MIPIRX5P__XGPIOC_1 3 +#define FMUX_SEL_PAD_MIPIRX5P__IIS1_MCLK 4 +#define FMUX_SEL_PAD_MIPIRX5P__CAM_MCLK1 5 +#define FMUX_SEL_PAD_MIPIRX5P__WG0_D1 6 +#define FMUX_SEL_PAD_MIPIRX5P__DBG_1 7 +#define FMUX_SEL_PAD_MIPIRX4N__VI0_CLK 1 +#define FMUX_SEL_PAD_MIPIRX4N__VI1_D_13 2 +#define FMUX_SEL_PAD_MIPIRX4N__XGPIOC_2 3 +#define FMUX_SEL_PAD_MIPIRX4N__IIC1_SDA 4 +#define FMUX_SEL_PAD_MIPIRX4N__CAM_MCLK0 5 +#define FMUX_SEL_PAD_MIPIRX4N__KEY_ROW0 6 +#define FMUX_SEL_PAD_MIPIRX4N__MUX_SPI1_SCK 7 +#define FMUX_SEL_PAD_MIPIRX4P__VI0_D_0 1 +#define FMUX_SEL_PAD_MIPIRX4P__VI1_D_14 2 +#define FMUX_SEL_PAD_MIPIRX4P__XGPIOC_3 3 +#define FMUX_SEL_PAD_MIPIRX4P__IIC1_SCL 4 +#define FMUX_SEL_PAD_MIPIRX4P__CAM_MCLK1 5 +#define FMUX_SEL_PAD_MIPIRX4P__KEY_ROW1 6 +#define FMUX_SEL_PAD_MIPIRX4P__MUX_SPI1_CS 7 +#define FMUX_SEL_PAD_MIPIRX3N__VI0_D_1 1 +#define FMUX_SEL_PAD_MIPIRX3N__VI1_D_15 2 +#define FMUX_SEL_PAD_MIPIRX3N__XGPIOC_4 3 +#define FMUX_SEL_PAD_MIPIRX3N__CAM_MCLK0 4 +#define FMUX_SEL_PAD_MIPIRX3N__MUX_SPI1_MISO 7 +#define FMUX_SEL_PAD_MIPIRX3P__VI0_D_2 1 +#define FMUX_SEL_PAD_MIPIRX3P__VI1_D_16 2 +#define FMUX_SEL_PAD_MIPIRX3P__XGPIOC_5 3 +#define FMUX_SEL_PAD_MIPIRX3P__MUX_SPI1_MOSI 7 +#define FMUX_SEL_PAD_MIPIRX2N__VI0_D_3 1 +#define FMUX_SEL_PAD_MIPIRX2N__VO_D_10 2 +#define FMUX_SEL_PAD_MIPIRX2N__XGPIOC_6 3 +#define FMUX_SEL_PAD_MIPIRX2N__VI1_D_17 4 +#define FMUX_SEL_PAD_MIPIRX2N__IIC4_SCL 5 +#define FMUX_SEL_PAD_MIPIRX2N__DBG_6 7 +#define FMUX_SEL_PAD_MIPIRX2P__VI0_D_4 1 +#define FMUX_SEL_PAD_MIPIRX2P__VO_D_9 2 +#define FMUX_SEL_PAD_MIPIRX2P__XGPIOC_7 3 +#define FMUX_SEL_PAD_MIPIRX2P__VI1_D_18 4 +#define FMUX_SEL_PAD_MIPIRX2P__IIC4_SDA 5 +#define FMUX_SEL_PAD_MIPIRX2P__DBG_7 7 +#define FMUX_SEL_PAD_MIPIRX1N__VI0_D_5 1 +#define FMUX_SEL_PAD_MIPIRX1N__VO_D_8 2 +#define FMUX_SEL_PAD_MIPIRX1N__XGPIOC_8 3 +#define FMUX_SEL_PAD_MIPIRX1N__KEY_ROW3 6 +#define FMUX_SEL_PAD_MIPIRX1N__DBG_8 7 +#define FMUX_SEL_PAD_MIPIRX1P__VI0_D_6 1 +#define FMUX_SEL_PAD_MIPIRX1P__VO_D_7 2 +#define FMUX_SEL_PAD_MIPIRX1P__XGPIOC_9 3 +#define FMUX_SEL_PAD_MIPIRX1P__IIC1_SDA 4 +#define FMUX_SEL_PAD_MIPIRX1P__KEY_ROW2 6 +#define FMUX_SEL_PAD_MIPIRX1P__DBG_9 7 +#define FMUX_SEL_PAD_MIPIRX0N__VI0_D_7 1 +#define FMUX_SEL_PAD_MIPIRX0N__VO_D_6 2 +#define FMUX_SEL_PAD_MIPIRX0N__XGPIOC_10 3 +#define FMUX_SEL_PAD_MIPIRX0N__IIC1_SCL 4 +#define FMUX_SEL_PAD_MIPIRX0N__CAM_MCLK1 5 +#define FMUX_SEL_PAD_MIPIRX0N__DBG_10 7 +#define FMUX_SEL_PAD_MIPIRX0P__VI0_D_8 1 +#define FMUX_SEL_PAD_MIPIRX0P__VO_D_5 2 +#define FMUX_SEL_PAD_MIPIRX0P__XGPIOC_11 3 +#define FMUX_SEL_PAD_MIPIRX0P__CAM_MCLK0 4 +#define FMUX_SEL_PAD_MIPIRX0P__DBG_11 7 +#define FMUX_SEL_PAD_MIPI_TXM4__SD1_CLK 1 +#define FMUX_SEL_PAD_MIPI_TXM4__VO_D_24 2 +#define FMUX_SEL_PAD_MIPI_TXM4__XGPIOC_18 3 +#define FMUX_SEL_PAD_MIPI_TXM4__CAM_MCLK1 4 +#define FMUX_SEL_PAD_MIPI_TXM4__PWM_12 5 +#define FMUX_SEL_PAD_MIPI_TXM4__IIC1_SDA 6 +#define FMUX_SEL_PAD_MIPI_TXM4__DBG_18 7 +#define FMUX_SEL_PAD_MIPI_TXP4__SD1_CMD 1 +#define FMUX_SEL_PAD_MIPI_TXP4__VO_D_25 2 +#define FMUX_SEL_PAD_MIPI_TXP4__XGPIOC_19 3 +#define FMUX_SEL_PAD_MIPI_TXP4__CAM_MCLK0 4 +#define FMUX_SEL_PAD_MIPI_TXP4__PWM_13 5 +#define FMUX_SEL_PAD_MIPI_TXP4__IIC1_SCL 6 +#define FMUX_SEL_PAD_MIPI_TXP4__DBG_19 7 +#define FMUX_SEL_PAD_MIPI_TXM3__SD1_D0 1 +#define FMUX_SEL_PAD_MIPI_TXM3__VO_D_26 2 +#define FMUX_SEL_PAD_MIPI_TXM3__XGPIOC_20 3 +#define FMUX_SEL_PAD_MIPI_TXM3__IIC2_SDA 4 +#define FMUX_SEL_PAD_MIPI_TXM3__PWM_14 5 +#define FMUX_SEL_PAD_MIPI_TXM3__IIC1_SDA 6 +#define FMUX_SEL_PAD_MIPI_TXM3__CAM_VS0 7 +#define FMUX_SEL_PAD_MIPI_TXP3__SD1_D1 1 +#define FMUX_SEL_PAD_MIPI_TXP3__VO_D_27 2 +#define FMUX_SEL_PAD_MIPI_TXP3__XGPIOC_21 3 +#define FMUX_SEL_PAD_MIPI_TXP3__IIC2_SCL 4 +#define FMUX_SEL_PAD_MIPI_TXP3__PWM_15 5 +#define FMUX_SEL_PAD_MIPI_TXP3__IIC1_SCL 6 +#define FMUX_SEL_PAD_MIPI_TXP3__CAM_HS0 7 +#define FMUX_SEL_PAD_MIPI_TXM2__VI0_D_13 1 +#define FMUX_SEL_PAD_MIPI_TXM2__VO_D_0 2 +#define FMUX_SEL_PAD_MIPI_TXM2__XGPIOC_16 3 +#define FMUX_SEL_PAD_MIPI_TXM2__IIC1_SDA 4 +#define FMUX_SEL_PAD_MIPI_TXM2__PWM_8 5 +#define FMUX_SEL_PAD_MIPI_TXM2__SPI0_SCK 6 +#define FMUX_SEL_PAD_MIPI_TXM2__SD1_D2 7 +#define FMUX_SEL_PAD_MIPI_TXP2__VI0_D_14 1 +#define FMUX_SEL_PAD_MIPI_TXP2__VO_CLK0 2 +#define FMUX_SEL_PAD_MIPI_TXP2__XGPIOC_17 3 +#define FMUX_SEL_PAD_MIPI_TXP2__IIC1_SCL 4 +#define FMUX_SEL_PAD_MIPI_TXP2__PWM_9 5 +#define FMUX_SEL_PAD_MIPI_TXP2__SPI0_CS_X 6 +#define FMUX_SEL_PAD_MIPI_TXP2__SD1_D3 7 +#define FMUX_SEL_PAD_MIPI_TXM1__VI0_D_11 1 +#define FMUX_SEL_PAD_MIPI_TXM1__VO_D_2 2 +#define FMUX_SEL_PAD_MIPI_TXM1__XGPIOC_14 3 +#define FMUX_SEL_PAD_MIPI_TXM1__IIC2_SDA 4 +#define FMUX_SEL_PAD_MIPI_TXM1__PWM_10 5 +#define FMUX_SEL_PAD_MIPI_TXM1__SPI0_SDO 6 +#define FMUX_SEL_PAD_MIPI_TXM1__DBG_14 7 +#define FMUX_SEL_PAD_MIPI_TXP1__VI0_D_12 1 +#define FMUX_SEL_PAD_MIPI_TXP1__VO_D_1 2 +#define FMUX_SEL_PAD_MIPI_TXP1__XGPIOC_15 3 +#define FMUX_SEL_PAD_MIPI_TXP1__IIC2_SCL 4 +#define FMUX_SEL_PAD_MIPI_TXP1__PWM_11 5 +#define FMUX_SEL_PAD_MIPI_TXP1__SPI0_SDI 6 +#define FMUX_SEL_PAD_MIPI_TXP1__DBG_15 7 +#define FMUX_SEL_PAD_MIPI_TXM0__VI0_D_9 1 +#define FMUX_SEL_PAD_MIPI_TXM0__VO_D_4 2 +#define FMUX_SEL_PAD_MIPI_TXM0__XGPIOC_12 3 +#define FMUX_SEL_PAD_MIPI_TXM0__CAM_MCLK1 4 +#define FMUX_SEL_PAD_MIPI_TXM0__PWM_14 5 +#define FMUX_SEL_PAD_MIPI_TXM0__CAM_VS0 6 +#define FMUX_SEL_PAD_MIPI_TXM0__DBG_12 7 +#define FMUX_SEL_PAD_MIPI_TXP0__VI0_D_10 1 +#define FMUX_SEL_PAD_MIPI_TXP0__VO_D_3 2 +#define FMUX_SEL_PAD_MIPI_TXP0__XGPIOC_13 3 +#define FMUX_SEL_PAD_MIPI_TXP0__CAM_MCLK0 4 +#define FMUX_SEL_PAD_MIPI_TXP0__PWM_15 5 +#define FMUX_SEL_PAD_MIPI_TXP0__CAM_HS0 6 +#define FMUX_SEL_PAD_MIPI_TXP0__DBG_13 7 +#define FMUX_SEL_PAD_AUD_AINL_MIC__XGPIOC_23 3 +#define FMUX_SEL_PAD_AUD_AINL_MIC__IIS1_BCLK 4 +#define FMUX_SEL_PAD_AUD_AINL_MIC__IIS2_BCLK 5 +#define FMUX_SEL_PAD_AUD_AINR_MIC__XGPIOC_22 3 +#define FMUX_SEL_PAD_AUD_AINR_MIC__IIS1_DO 4 +#define FMUX_SEL_PAD_AUD_AINR_MIC__IIS2_DI 5 +#define FMUX_SEL_PAD_AUD_AINR_MIC__IIS1_DI 6 +#define FMUX_SEL_PAD_AUD_AOUTL__XGPIOC_25 3 +#define FMUX_SEL_PAD_AUD_AOUTL__IIS1_LRCK 4 +#define FMUX_SEL_PAD_AUD_AOUTL__IIS2_LRCK 5 +#define FMUX_SEL_PAD_AUD_AOUTR__XGPIOC_24 3 +#define FMUX_SEL_PAD_AUD_AOUTR__IIS1_DI 4 +#define FMUX_SEL_PAD_AUD_AOUTR__IIS2_DO 5 +#define FMUX_SEL_PAD_AUD_AOUTR__IIS1_DO 6 +#define FMUX_SEL_GPIO_RTX__XGPIOB_23 3 +#define FMUX_SEL_GPIO_RTX__PWM_1 4 +#define FMUX_SEL_GPIO_RTX__CAM_MCLK0 5 +#define FMUX_SEL_GPIO_ZQ__PWR_GPIO_24 3 +#define FMUX_SEL_GPIO_ZQ__PWM_2 4 + +#endif /* ZEPHYR_DT_SOPHGO_CV180X_PINCTRL_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/sophgo-cvi-pinctrl-common.h b/include/zephyr/dt-bindings/pinctrl/sophgo-cvi-pinctrl-common.h new file mode 100644 index 00000000000000..9cdee4d35dcb0b --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/sophgo-cvi-pinctrl-common.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023-2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DT_SOPHGO_CVI_PINCTRL_COMMON_H_ +#define ZEPHYR_DT_SOPHGO_CVI_PINCTRL_COMMON_H_ + +#include + +#define CVI_PINMUX_FMUX_IDX_S (0) +#define CVI_PINMUX_FMUX_IDX_M BIT_MASK(8) + +#define CVI_PINMUX_FMUX_SEL_S (8) +#define CVI_PINMUX_FMUX_SEL_M BIT_MASK(3) + +#define CVI_PINMUX(pin, func) \ + ((((FMUX_IDX_##pin) & CVI_PINMUX_FMUX_IDX_M) << CVI_PINMUX_FMUX_IDX_S) | \ + (((FMUX_SEL_##pin##__##func) & CVI_PINMUX_FMUX_SEL_M) << CVI_PINMUX_FMUX_SEL_S)) + +#endif /* ZEPHYR_DT_SOPHGO_CVI_PINCTRL_COMMON_H_ */ diff --git a/scripts/west_commands/runners/__init__.py b/scripts/west_commands/runners/__init__.py index 6d5539905e334c..5e09d51c66c55d 100644 --- a/scripts/west_commands/runners/__init__.py +++ b/scripts/west_commands/runners/__init__.py @@ -28,6 +28,7 @@ def _import_runner_module(runner_name): 'blackmagicprobe', 'bossac', 'canopen_program', + 'cvi_fiptool', 'dediprog', 'dfu', 'esp32', diff --git a/scripts/west_commands/runners/cvi_fiptool.py b/scripts/west_commands/runners/cvi_fiptool.py new file mode 100644 index 00000000000000..4933b89b68cec7 --- /dev/null +++ b/scripts/west_commands/runners/cvi_fiptool.py @@ -0,0 +1,62 @@ +# Copyright (c) 2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +'''SOPHGO CVI specific flash only runner.''' + +import sys +import time +from os import path + +from runners.core import ZephyrBinaryRunner, RunnerCaps + + +class CviFiptoolBinaryRunner(ZephyrBinaryRunner): + '''Runner front-end for the SOPHGO CVI boards, using fiptool.py from SDK.''' + + def __init__(self, cfg, fiptool_py, fip_bin): + super().__init__(cfg) + self.fiptool_py = fiptool_py + self.fip_bin = fip_bin + self.bin_name = cfg.bin_file + + @classmethod + def name(cls): + return 'cvi-fiptool' + + @classmethod + def capabilities(cls): + return RunnerCaps(commands={'flash'}) + + @classmethod + def do_add_parser(cls, parser): + parser.add_argument('--fiptool', required=True, + help='path to fiptool.py script from SDK') + parser.add_argument('--fip-bin', required=True, + help='path to fip.bin file to be updated') + + @classmethod + def do_create(cls, cfg, args): + return CviFiptoolBinaryRunner(cfg, args.fiptool, args.fip_bin) + + def do_run(self, command, **kwargs): + self.require(self.fiptool_py) + + fip_dir = path.dirname(self.fip_bin) + if not path.exists(fip_dir): + print(f'Waiting for {fip_dir} to be present...') + while not path.exists(fip_dir): + time.sleep(1) + + if not path.exists(self.fip_bin): + raise RuntimeError(f'File {self.fip_bin} not found') + + cmd_flash = [sys.executable, self.fiptool_py] + + cmd_flash.extend(['-v', 'genfip', self.fip_bin]) + cmd_flash.extend(['--OLD_FIP', self.fip_bin]) + cmd_flash.extend(['--BLCP_2ND', self.bin_name]) + + self.check_call(cmd_flash) + + print('') + print('fip.bin updated. Remember to eject the drive before unplugging.') diff --git a/scripts/west_commands/tests/test_imports.py b/scripts/west_commands/tests/test_imports.py index 42fb983586dfa0..24966329c17028 100644 --- a/scripts/west_commands/tests/test_imports.py +++ b/scripts/west_commands/tests/test_imports.py @@ -18,6 +18,7 @@ def test_runner_imports(): 'blackmagicprobe', 'bossac', 'canopen', + 'cvi-fiptool', 'dediprog', 'dfu-util', 'esp32', diff --git a/soc/sophgo/CMakeLists.txt b/soc/sophgo/CMakeLists.txt new file mode 100644 index 00000000000000..c5f97039eb75b4 --- /dev/null +++ b/soc/sophgo/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/sophgo/Kconfig b/soc/sophgo/Kconfig new file mode 100644 index 00000000000000..4667869008e8ba --- /dev/null +++ b/soc/sophgo/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_SOPHGO + +rsource "*/Kconfig" + +endif # SOC_FAMILY_SOPHGO diff --git a/soc/sophgo/Kconfig.defconfig b/soc/sophgo/Kconfig.defconfig new file mode 100644 index 00000000000000..afd11b86766ab2 --- /dev/null +++ b/soc/sophgo/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_SOPHGO + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_SOPHGO diff --git a/soc/sophgo/Kconfig.soc b/soc/sophgo/Kconfig.soc new file mode 100644 index 00000000000000..fd1254724a72d7 --- /dev/null +++ b/soc/sophgo/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_SOPHGO + bool + +config SOC_FAMILY + default "sophgo" if SOC_FAMILY_SOPHGO + +rsource "*/Kconfig.soc" diff --git a/soc/sophgo/common/CMakeLists.txt b/soc/sophgo/common/CMakeLists.txt new file mode 100644 index 00000000000000..f75aec6b311768 --- /dev/null +++ b/soc/sophgo/common/CMakeLists.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/sophgo/common/pinctrl_soc.h b/soc/sophgo/common/pinctrl_soc.h new file mode 100644 index 00000000000000..5a4afe88b10497 --- /dev/null +++ b/soc/sophgo/common/pinctrl_soc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2023-2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __SOC_SOPHGO_PINCTRL_H__ +#define __SOC_SOPHGO_PINCTRL_H__ + +#include +#include + +struct pinctrl_soc_pin { + uint32_t fmux_idx; + uint32_t fmux_sel; +}; + +typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; + +#define CVI_PINMUX_GET(pinmux, field) ((pinmux >> CVI_PINMUX_##field##_S) & CVI_PINMUX_##field##_M) + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + { \ + .fmux_idx = CVI_PINMUX_GET(DT_PROP_BY_IDX(node_id, prop, idx), FMUX_IDX), \ + .fmux_sel = CVI_PINMUX_GET(DT_PROP_BY_IDX(node_id, prop, idx), FMUX_SEL), \ + }, + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { \ + DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT) \ + } + +#endif /* __SOC_SOPHGO_PINCTRL_H__ */ diff --git a/soc/sophgo/cv180x/CMakeLists.txt b/soc/sophgo/cv180x/CMakeLists.txt new file mode 100644 index 00000000000000..187982e821607a --- /dev/null +++ b/soc/sophgo/cv180x/CMakeLists.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/sophgo/cv180x/Kconfig b/soc/sophgo/cv180x/Kconfig new file mode 100644 index 00000000000000..bef8c362b09f99 --- /dev/null +++ b/soc/sophgo/cv180x/Kconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CV180X + select 64BIT + select RISCV + select RISCV_PRIVILEGED + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_F + select RISCV_ISA_EXT_D + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select INCLUDE_RESET_VECTOR + select ATOMIC_OPERATIONS_C diff --git a/soc/sophgo/cv180x/Kconfig.defconfig b/soc/sophgo/cv180x/Kconfig.defconfig new file mode 100644 index 00000000000000..4fe580fd39f688 --- /dev/null +++ b/soc/sophgo/cv180x/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CV180X + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 + +config NUM_IRQS + int + default 128 + +config RISCV_GP + default y + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_HAS_PLIC + default y + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +endif # SOC_SERIES_CV180X diff --git a/soc/sophgo/cv180x/Kconfig.soc b/soc/sophgo/cv180x/Kconfig.soc new file mode 100644 index 00000000000000..a14b0d6a53dc86 --- /dev/null +++ b/soc/sophgo/cv180x/Kconfig.soc @@ -0,0 +1,16 @@ +# Copyright (c) 2023-2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CV180X + bool + select SOC_FAMILY_SOPHGO + +config SOC_SERIES + default "cv180x" if SOC_SERIES_CV180X + +config SOC_CV1800B + bool + select SOC_SERIES_CV180X + +config SOC + default "cv1800b" if SOC_CV1800B diff --git a/soc/sophgo/cv181x/CMakeLists.txt b/soc/sophgo/cv181x/CMakeLists.txt new file mode 100644 index 00000000000000..187982e821607a --- /dev/null +++ b/soc/sophgo/cv181x/CMakeLists.txt @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/sophgo/cv181x/Kconfig b/soc/sophgo/cv181x/Kconfig new file mode 100644 index 00000000000000..81739d7b6220af --- /dev/null +++ b/soc/sophgo/cv181x/Kconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CV181X + select 64BIT + select RISCV + select RISCV_PRIVILEGED + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_F + select RISCV_ISA_EXT_D + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select INCLUDE_RESET_VECTOR + select ATOMIC_OPERATIONS_C diff --git a/soc/sophgo/cv181x/Kconfig.defconfig b/soc/sophgo/cv181x/Kconfig.defconfig new file mode 100644 index 00000000000000..7107b6616837b8 --- /dev/null +++ b/soc/sophgo/cv181x/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CV181X + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 + +config NUM_IRQS + int + default 128 + +config RISCV_GP + default y + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_HAS_PLIC + default y + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +endif # SOC_SERIES_CV181X diff --git a/soc/sophgo/cv181x/Kconfig.soc b/soc/sophgo/cv181x/Kconfig.soc new file mode 100644 index 00000000000000..3f252f607fd4ef --- /dev/null +++ b/soc/sophgo/cv181x/Kconfig.soc @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Chen Xingyu +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CV181X + bool + select SOC_FAMILY_SOPHGO + +config SOC_SERIES + default "cv181x" if SOC_SERIES_CV181X + +config SOC_SG2000 + bool + select SOC_SERIES_CV181X + +config SOC_SG2002 + bool + select SOC_SERIES_CV181X + +config SOC + default "sg2000" if SOC_SG2000 + default "sg2002" if SOC_SG2002 diff --git a/soc/sophgo/soc.yml b/soc/sophgo/soc.yml new file mode 100644 index 00000000000000..1a1b48eb907922 --- /dev/null +++ b/soc/sophgo/soc.yml @@ -0,0 +1,10 @@ +family: +- name: sophgo + series: + - name: cv180x + socs: + - name: cv1800b + - name: cv181x + socs: + - name: sg2000 + - name: sg2002 diff --git a/tests/drivers/pwm/pwm_api/boards/milkv_duo.overlay b/tests/drivers/pwm/pwm_api/boards/milkv_duo.overlay new file mode 100644 index 00000000000000..15322cca58c78a --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/milkv_duo.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2023-2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + pwm-0 = &pwm1; + }; +}; + +&pinctrl { + pwm1_default: pwm1_default { + group1 { + pinmux = ; /* GP4 */ + }; + }; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; +}; diff --git a/tests/drivers/pwm/pwm_api/boards/milkv_duo256m.overlay b/tests/drivers/pwm/pwm_api/boards/milkv_duo256m.overlay new file mode 100644 index 00000000000000..ba949cf448907c --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/milkv_duo256m.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + pwm-0 = &pwm1; + }; +}; + +&pinctrl { + pwm1_default: pwm1_default { + group1 { + pinmux = ; /* GP4 */ + }; + }; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; +}; diff --git a/tests/drivers/pwm/pwm_api/boards/milkv_duos.overlay b/tests/drivers/pwm/pwm_api/boards/milkv_duos.overlay new file mode 100644 index 00000000000000..660d26a6609bb9 --- /dev/null +++ b/tests/drivers/pwm/pwm_api/boards/milkv_duos.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Chen Xingyu + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + pwm-0 = &pwm0; + }; +}; + +&pinctrl { + pwm0_default: pwm0_default { + group1 { + pinmux = ; /* B20 */ + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; +}; diff --git a/tests/drivers/pwm/pwm_api/src/test_pwm.c b/tests/drivers/pwm/pwm_api/src/test_pwm.c index b5fc72b37e8cd5..a344a03704fc34 100644 --- a/tests/drivers/pwm/pwm_api/src/test_pwm.c +++ b/tests/drivers/pwm/pwm_api/src/test_pwm.c @@ -88,6 +88,10 @@ #elif defined(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS) || \ defined(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0) #define DEFAULT_PWM_PORT 2 /* D2 on Arduino connector P18 */ +#elif defined(CONFIG_BOARD_MILKV_DUO) || defined(CONFIG_BOARD_MILKV_DUO256M) +#define DEFAULT_PWM_PORT 1 +#elif defined CONFIG_BOARD_MILKV_DUOS +#define DEFAULT_PWM_PORT 3 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_pwm) /* Default port should be adapted per board to fit the channel * associated to the PWM pin. For intsance, for following device,