uart_echo unable to compile

[quantrpeter]

hi

/home/peter/workspace/icesugar/src/basic/verilog/uart_echo>make
Makefile:5: iCELink path: /media/peter/iCELink
yosys -p "synth_ice40 -blif pll_uart_mirror.blif" pll_uart_mirror.v

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <[email protected]>         |
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 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
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 \----------------------------------------------------------------------------/

 Yosys 0.30+48 (git sha1 14d50a176, clang 14.0.0-1ubuntu1 -fPIC -Os)


-- Parsing `pll_uart_mirror.v' using frontend ` -vlog2k' --

1. Executing Verilog-2005 frontend: pll_uart_mirror.v
Parsing Verilog input from `pll_uart_mirror.v' to AST representation.
pll_uart_mirror.v:69: ERROR: syntax error, unexpected TOK_REG
make: *** [Makefile:8: build] Error 1

thanks