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make gateware failed #40
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fix a lot on firmware section ///THE success message// Info: Placed 16 cells based on constraints. Info: Running simulated annealing placer for refinement. Info: Max frequency for clock 'clk12$SB_IO_IN_$glb_clk': 22.55 MHz (PASS at 12.00 MHz) Info: Max delay -> posedge clk12$SB_IO_IN_$glb_clk: 10.37 ns Info: Slack histogram: Info: Routing.. Info: Critical path report for clock 'clk12$SB_IO_IN_$glb_clk' (posedge -> posedge): Info: Critical path report for cross-domain path '' -> 'posedge clk12$SB_IO_IN_$glb_clk': Info: Critical path report for cross-domain path 'posedge clk12$SB_IO_IN_$glb_clk' -> '': Info: Max frequency for clock 'clk12$SB_IO_IN_$glb_clk': 23.75 MHz (PASS at 12.00 MHz) Info: Max delay -> posedge clk12$SB_IO_IN_$glb_clk: 10.62 ns Info: Slack histogram: real 0m29.493s |
export PLATFORM=ice40_up5k_b_evn
export TARGET=base
export CPU=vexriscv
export CPU_VARIANT=linux
export FIRMWARE=linux
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
chmod +x ./litex_setup.py
./litex_setup.py init install --user
./scripts/debian-setup.sh
./scripts/download-env.sh
source ./scripts/enter-env.sh
make gateware
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