From d67da2834effd83ff6e9299eda43eb54a16cd766 Mon Sep 17 00:00:00 2001
From: Vikram Jain <vikramjainiit@gmail.com>
Date: Fri, 5 Jul 2024 15:38:36 -0700
Subject: [PATCH] reduced accum bitwidth 40 16 and buffer to 64kB

---
 src/main/scala/gemmini/ConfigsFP.scala      | 25 ++++++++++++---------
 src/main/scala/gemmini/GemminiConfigs.scala |  4 ++--
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/src/main/scala/gemmini/ConfigsFP.scala b/src/main/scala/gemmini/ConfigsFP.scala
index c2bb1383..2f60600a 100644
--- a/src/main/scala/gemmini/ConfigsFP.scala
+++ b/src/main/scala/gemmini/ConfigsFP.scala
@@ -133,23 +133,28 @@ object GemminiFPConfigs {
     clock_gate = true 
   )
 
-  val chipFP16Config = FP16DefaultConfig.copy(sp_capacity=CapacityInKilobytes(128), acc_capacity=CapacityInKilobytes(128), dataflow=Dataflow.WS,
-    meshRows = 8,
-    meshColumns = 8,
-    acc_scale_args = Some(ScaleArguments((t: Float, u: Float) => {t}, 1, Float(8, 24), -1, identity = "1.0",
-      c_str = "((x))"
-    )),
-    mvin_scale_args = Some(ScaleArguments((t: Float, u: Float) => t * u, 3, Float(5, 11), -1, identity = "1.0", c_str="((x) * (scale))")),
+  val chipFP16Config = FP16DefaultConfig.copy(sp_capacity=CapacityInKilobytes(128), acc_capacity=CapacityInKilobytes(64), dataflow=Dataflow.WS,
+    meshRows = 16,
+    meshColumns = 16,
+    accType = Float(5, 11),
+    //acc_scale_args = Some(ScaleArguments((t: Float, u: Float) => {t}, 1, Float(8, 24), -1, identity = "1.0",
+    //  c_str = "((x))"
+    //)),
+    acc_scale_args = Some(ScaleArguments((t: Float, u: Float) => t * u, 4, Float(5, 11), -1, identity = "1.0",
+      c_str = "((x) * (scale))"
+    )),  
+    //mvin_scale_args = Some(ScaleArguments((t: Float, u: Float) => t * u, 3, Float(5, 11), -1, identity = "1.0", c_str="((x) * (scale))")),
+    mvin_scale_args = Some(ScaleArguments((t: Float, u: Float) => {t}, 1, Float(5, 11), -1, identity = "1.0", c_str="((x))")),
     mvin_scale_acc_args=None,
-    acc_singleported=false,
-    acc_sub_banks = 1,
+    acc_singleported=true,
+    acc_sub_banks = 2,
     acc_banks = 2,
     mesh_output_delay = 2,
     tile_latency = 1,
     acc_latency = 3,
     ex_read_from_acc=false,
     ex_write_to_spad=false,
-    has_training_convs = false,                                                                                      
+    has_training_convs = false,
     hardcode_d_to_garbage_addr = true,
     acc_read_full_width = false,
     max_in_flight_mem_reqs = 16,
diff --git a/src/main/scala/gemmini/GemminiConfigs.scala b/src/main/scala/gemmini/GemminiConfigs.scala
index 98254299..4d1793ec 100644
--- a/src/main/scala/gemmini/GemminiConfigs.scala
+++ b/src/main/scala/gemmini/GemminiConfigs.scala
@@ -247,8 +247,8 @@ case class GemminiArrayConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
   val USABLE_SP_TILES = (SP_ROWS / DIM) - 2
   val TOTAL_ACC_TILES = (ACC_ROWS / DIM)
   val SQRT_ACC_TILES = sqrt(TOTAL_ACC_TILES).toInt
-  assert(USABLE_SP_TILES >= TOTAL_ACC_TILES, 
-    s"SP_TILES($USABLE_SP_TILES) + 2 < ACC_TILES($TOTAL_ACC_TILES)")
+  //assert(USABLE_SP_TILES >= TOTAL_ACC_TILES, 
+  //  s"SP_TILES($USABLE_SP_TILES) + 2 < ACC_TILES($TOTAL_ACC_TILES)")
 
   // prioritize sizes that cause the output-group to be further from square
   val OG_HEIGHT_MAP = (1 to TOTAL_ACC_TILES).sortWith((h1, h2) => {