From b2f9cbc8457ea968c70e15511cbeb751f4341656 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 23 Jan 2024 22:26:41 -0800 Subject: [PATCH] Set MMIO base address to within smem range --- src/main/scala/gemmini/Controller.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/gemmini/Controller.scala b/src/main/scala/gemmini/Controller.scala index f7210b76..87d776bf 100644 --- a/src/main/scala/gemmini/Controller.scala +++ b/src/main/scala/gemmini/Controller.scala @@ -145,7 +145,7 @@ class Gemmini[T <: Data : Arithmetic, U <: Data, V <: Data](val config: GemminiA val regDevice = new SimpleDevice("gemmini-cmd-reg", Seq(s"gemmini-cmd-reg")) val regNode = TLRegisterNode( - address = Seq(AddressSet(0x60000000, 0xfff)), + address = Seq(AddressSet(0xff002000L, 0xfff)), device = regDevice, beatBytes = 8, concurrency = 1) @@ -384,6 +384,8 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data] 0x10 -> Seq(RegField.w(64, gemminiRs1Reg)), 0x18 -> Seq(RegField.w(64, gemminiRs2Reg)) ) + dontTouch(outer.regNode.in(0)._1.a) + dontTouch(outer.regNode.in(0)._1.d) val raw_cmd = raw_cmd_q.io.deq