From 79f523057df9cadfc387deb64ffb84b8d3756b25 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 27 Jan 2024 20:16:32 -0800 Subject: [PATCH] Switch to chisel6-compatible APIs --- build.sbt | 4 +- src/main/scala/gemmini/Controller.scala | 2 +- src/main/scala/gemmini/DMA.scala | 5 +- src/main/scala/gemmini/LoopConv.scala | 2 +- src/main/scala/gemmini/LoopMatmul.scala | 6 +-- src/main/scala/gemmini/NormCmd.scala | 1 - src/main/scala/gemmini/Normalizer.scala | 53 +++++++++---------- .../scala/gemmini/ReservationStation.scala | 8 +-- src/main/scala/gemmini/Scratchpad.scala | 2 +- .../gemmini/TransposePreloadUnroller.scala | 1 - 10 files changed, 40 insertions(+), 44 deletions(-) diff --git a/build.sbt b/build.sbt index 9664bcd2..79a08763 100644 --- a/build.sbt +++ b/build.sbt @@ -4,10 +4,10 @@ name := "gemmini" version := "3.1.0" -scalaVersion := "2.13.10" +scalaVersion := "2.13.12" libraryDependencies ++= Seq( - "edu.berkeley.cs" %% "chisel3" % "3.6.0", + "org.chipsalliance" %% "chisel" % "6.0.0", "edu.berkeley.cs" %% "rocketchip" % "1.2.+", "org.scalanlp" %% "breeze" % "1.1") diff --git a/src/main/scala/gemmini/Controller.scala b/src/main/scala/gemmini/Controller.scala index 0fdda55f..33e5fd93 100644 --- a/src/main/scala/gemmini/Controller.scala +++ b/src/main/scala/gemmini/Controller.scala @@ -403,7 +403,7 @@ class GemminiModule[T <: Data: Arithmetic, U <: Data, V <: Data] // Debugging signals val pipeline_stall_counter = RegInit(0.U(32.W)) - when (io.cmd.fire()) { + when (io.cmd.fire) { pipeline_stall_counter := 0.U }.elsewhen(io.busy) { pipeline_stall_counter := pipeline_stall_counter + 1.U diff --git a/src/main/scala/gemmini/DMA.scala b/src/main/scala/gemmini/DMA.scala index dac1a369..29252955 100644 --- a/src/main/scala/gemmini/DMA.scala +++ b/src/main/scala/gemmini/DMA.scala @@ -3,7 +3,6 @@ package gemmini import chisel3._ import chisel3.util._ -import chisel3.experimental.DataMirror import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp} @@ -211,7 +210,7 @@ class StreamReaderCore[T <: Data, U <: Data, V <: Data](config: GemminiArrayConf )._2 class TLBundleAWithInfo extends Bundle { - val tl_a = DataMirror.internal.chiselTypeClone[TLBundleA](tl.a.bits) + val tl_a = tl.a.bits.cloneType val vaddr = Output(UInt(vaddrBits.W)) val status = Output(new MStatus) } @@ -499,7 +498,7 @@ class StreamWriter[T <: Data: Arithmetic](nXacts: Int, beatBits: Int, maxBytes: )._2 class TLBundleAWithInfo extends Bundle { - val tl_a = DataMirror.internal.chiselTypeClone[TLBundleA](tl.a.bits) + val tl_a = tl.a.bits.cloneType val vaddr = Output(UInt(vaddrBits.W)) val status = Output(new MStatus) } diff --git a/src/main/scala/gemmini/LoopConv.scala b/src/main/scala/gemmini/LoopConv.scala index 07dfefdc..2db2b034 100644 --- a/src/main/scala/gemmini/LoopConv.scala +++ b/src/main/scala/gemmini/LoopConv.scala @@ -974,7 +974,7 @@ class LoopConvSt(block_size: Int, coreMaxAddrBits: Int, large_iterator_bitwidth: io.loop_id := req.loop_id command_p.io.in.valid := state =/= idle && !skip && io.ex_completed - command_p.io.in.bits.cmd := MuxLookup(state.asUInt, mvout_cmd, Seq( + command_p.io.in.bits.cmd := MuxLookup(state.asUInt, mvout_cmd)(Seq( pre_pool_config.asUInt -> pre_pool_config_cmd, pool.asUInt -> pool_cmd, post_pool_config.asUInt -> post_pool_config_cmd) diff --git a/src/main/scala/gemmini/LoopMatmul.scala b/src/main/scala/gemmini/LoopMatmul.scala index 91a4afbe..07d8d49e 100644 --- a/src/main/scala/gemmini/LoopMatmul.scala +++ b/src/main/scala/gemmini/LoopMatmul.scala @@ -643,7 +643,7 @@ class LoopMatmulStC(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: In when (req.dram_addr === 0.U) { state := idle - }.elsewhen (io.cmd.fire() && state === st) { + }.elsewhen (io.cmd.fire && state === st) { // The order here is k, j, i val next_i = floorAdd(i, 1.U, req.max_i) val next_j = floorAdd(j, max_blocks, req.max_j, next_i === 0.U) @@ -654,9 +654,9 @@ class LoopMatmulStC(block_size: Int, coreMaxAddrBits: Int, iterator_bitwidth: In when (next_i === 0.U && next_j === 0.U) { state := idle } - }.elsewhen (io.cmd.fire() && state === ln_config) { + }.elsewhen (io.cmd.fire && state === ln_config) { state := ln_st - }.elsewhen (io.cmd.fire() && state === ln_st) { + }.elsewhen (io.cmd.fire && state === ln_st) { val next_j = floorAdd(j, max_blocks, req.max_j) val next_stat_id = floorAdd(ln_stat_id, 1.U, ln_stat_ids, next_j === 0.U) val next_cmd = floorAdd(ln_cmd, 1.U, ln_norm_cmds.size.U, next_j === 0.U && next_stat_id === 0.U) diff --git a/src/main/scala/gemmini/NormCmd.scala b/src/main/scala/gemmini/NormCmd.scala index 515fabb0..52da8cde 100644 --- a/src/main/scala/gemmini/NormCmd.scala +++ b/src/main/scala/gemmini/NormCmd.scala @@ -3,7 +3,6 @@ package gemmini import chisel3._ import chisel3.util._ -import chisel3.experimental.ChiselEnum object NormCmd extends ChiselEnum { val RESET, SUM, MEAN, VARIANCE, INV_STDDEV, MAX, SUM_EXP, INV_SUM_EXP = Value diff --git a/src/main/scala/gemmini/Normalizer.scala b/src/main/scala/gemmini/Normalizer.scala index de3f301b..c22e9af8 100644 --- a/src/main/scala/gemmini/Normalizer.scala +++ b/src/main/scala/gemmini/Normalizer.scala @@ -2,7 +2,6 @@ package gemmini import chisel3._ -import chisel3.experimental.ChiselEnum import chisel3.util._ import gemmini.AccumulatorScale.iexp import hardfloat.{DivSqrtRecFN_small, INToRecFN, MulRecFN, consts, fNFromRecFN, recFNFromFN} @@ -348,7 +347,7 @@ class Normalizer[T <: Data, U <: Data](max_len: Int, num_reduce_lanes: Int, num_ lanes.io.ins.bits.stats_id := in_lanes_stats_id lanes.io.ins.bits.iexp_const := iexp_const - when (lanes.io.ins.fire()) { + when (lanes.io.ins.fire) { stat.elems_left := stat.elems_left - len } } @@ -359,7 +358,7 @@ class Normalizer[T <: Data, U <: Data](max_len: Int, num_reduce_lanes: Int, num_ val stat = stats(out_lanes_stats_id) - when (lanes.io.out.fire()) { + when (lanes.io.out.fire) { stat.sum := stat.sum + lanes.io.out.bits.result } } @@ -379,7 +378,7 @@ class Normalizer[T <: Data, U <: Data](max_len: Int, num_reduce_lanes: Int, num_ max_lanes.io.ins.bits.len := len max_lanes.io.ins.bits.stats_id := max_in_lanes_stats_id - when (max_lanes.io.ins.fire()) { + when (max_lanes.io.ins.fire) { stat.elems_left := stat.elems_left - len } } @@ -390,7 +389,7 @@ class Normalizer[T <: Data, U <: Data](max_len: Int, num_reduce_lanes: Int, num_ val stat = stats(max_out_lanes_stats_id) - when (max_lanes.io.out.fire()) { + when (max_lanes.io.out.fire) { val new_max = Mux(max_lanes.io.out.bits.result > stat.running_max, max_lanes.io.out.bits.result, stat.running_max) stat.running_max := new_max stat.max := new_max @@ -645,13 +644,13 @@ class Normalizer[T <: Data, U <: Data](max_len: Int, num_reduce_lanes: Int, num_ next_state := idle done := DontCare }.elsewhen(state === output) { - next_state := Mux(io.out.fire() && out_stats_id === id.U, idle, state) - done := io.out.fire() && out_stats_id === id.U + next_state := Mux(io.out.fire && out_stats_id === id.U, idle, state) + done := io.out.fire && out_stats_id === id.U }.elsewhen(state === get_max) { val is_last_lane_input = stat.vec_groups_left === 0.U || (stat.vec_groups_left === 1.U && max_lanes.io.ins.bits.stats_id === id.U && - max_lanes.io.ins.fire()) + max_lanes.io.ins.fire) next_state := Mux( is_last_lane_input, @@ -667,7 +666,7 @@ class Normalizer[T <: Data, U <: Data](max_len: Int, num_reduce_lanes: Int, num_ val is_last_lane_input = stat.vec_groups_left === 0.U || (stat.vec_groups_left === 1.U && lanes.io.ins.bits.stats_id === id.U && - lanes.io.ins.fire()) + lanes.io.ins.fire) next_state := Mux( is_last_lane_input, @@ -688,51 +687,51 @@ class Normalizer[T <: Data, U <: Data](max_len: Int, num_reduce_lanes: Int, num_ done := is_last_lane_input && cmd =/= NormCmd.MEAN && cmd =/= NormCmd.INV_STDDEV && cmd =/= NormCmd.INV_SUM_EXP }.elsewhen(state === get_mean || state === get_variance) { - next_state := Mux(divider_in.fire() && sum_to_divide_id === id.U, state.next, state) + next_state := Mux(divider_in.fire && sum_to_divide_id === id.U, state.next, state) done := false.B }.elsewhen(state === waiting_for_mean) { - next_state := Mux(divider_out.fire(), idle, state) - done := divider_out.fire() + next_state := Mux(divider_out.fire, idle, state) + done := divider_out.fire }.elsewhen(state === waiting_for_variance) { - next_state := Mux(divider_out.fire(), get_stddev, state) + next_state := Mux(divider_out.fire, get_stddev, state) done := false.B }.elsewhen(state === get_stddev) { - next_state := Mux(sqrt_in.fire() && variance_to_sqrt_id === id.U, state.next, state) + next_state := Mux(sqrt_in.fire && variance_to_sqrt_id === id.U, state.next, state) done := false.B }.elsewhen(state === waiting_for_stddev) { - next_state := Mux(sqrt_out.fire(), state.next, state) + next_state := Mux(sqrt_out.fire, state.next, state) done := false.B }.elsewhen(state === get_inv_stddev) { - next_state := Mux(reciprocal_in.fire() && stddev_to_inv_id === id.U, state.next, state) + next_state := Mux(reciprocal_in.fire && stddev_to_inv_id === id.U, state.next, state) done := false.B }.elsewhen(state === waiting_for_inv_stddev) { - next_state := Mux(reciprocal_out.fire(), state.next, state) + next_state := Mux(reciprocal_out.fire, state.next, state) done := false.B }.elsewhen(state === get_scaled_inv_stddev) { - next_state := Mux(inv_stddev_scale_mul_pipe.io.ins.fire() && inv_stddev_to_scale_id === id.U, state.next, state) + next_state := Mux(inv_stddev_scale_mul_pipe.io.ins.fire && inv_stddev_to_scale_id === id.U, state.next, state) done := false.B }.elsewhen(state === waiting_for_scaled_inv_stddev) { - next_state := Mux(inv_stddev_scale_mul_pipe.io.out.fire(), idle, state) - done := inv_stddev_scale_mul_pipe.io.out.fire() + next_state := Mux(inv_stddev_scale_mul_pipe.io.out.fire, idle, state) + done := inv_stddev_scale_mul_pipe.io.out.fire }.elsewhen(state === get_inv_sum_exp) { - next_state := Mux(exp_divider_in.fire() && sum_exp_to_inv_id === id.U, state.next, state) + next_state := Mux(exp_divider_in.fire && sum_exp_to_inv_id === id.U, state.next, state) done := false.B }.elsewhen(state === waiting_for_inv_sum_exp) { - next_state := Mux(exp_divider_out.fire(), state.next, state) + next_state := Mux(exp_divider_out.fire, state.next, state) done := false.B }.elsewhen(state === get_scaled_inv_sum_exp) { - next_state := Mux(inv_sum_exp_scale_mul_pipe.io.ins.fire() && inv_sum_exp_to_scale_id === id.U, state.next, state) + next_state := Mux(inv_sum_exp_scale_mul_pipe.io.ins.fire && inv_sum_exp_to_scale_id === id.U, state.next, state) done := false.B }.elsewhen(state === waiting_for_scaled_inv_sum_exp) { - next_state := Mux(inv_sum_exp_scale_mul_pipe.io.out.fire(), idle, state) - done := inv_sum_exp_scale_mul_pipe.io.out.fire() + next_state := Mux(inv_sum_exp_scale_mul_pipe.io.out.fire, idle, state) + done := inv_sum_exp_scale_mul_pipe.io.out.fire }.otherwise { assert(false.B, "invalid state in Normalizer") next_state := DontCare done := DontCare } - when (io.in.fire() && in_stats_id === id.U) { + when (io.in.fire && in_stats_id === id.U) { next_state := Mux(io.in.bits.cmd === NormCmd.RESET, output, Mux(io.in.bits.cmd === NormCmd.MAX, get_max, get_sum)) } @@ -747,7 +746,7 @@ class Normalizer[T <: Data, U <: Data](max_len: Int, num_reduce_lanes: Int, num_ (state === get_mean && next_state =/= get_mean) || (state === get_variance && next_state =/= get_variance) - val is_input = io.in.fire() && in_stats_id === id.U + val is_input = io.in.fire && in_stats_id === id.U when (is_input) { stat.req := io.in.bits diff --git a/src/main/scala/gemmini/ReservationStation.scala b/src/main/scala/gemmini/ReservationStation.scala index 47dd5ef1..3c2600df 100644 --- a/src/main/scala/gemmini/ReservationStation.scala +++ b/src/main/scala/gemmini/ReservationStation.scala @@ -19,7 +19,7 @@ class ReservationStationIssue[T <: Data](cmd_t: T, id_width: Int) extends Bundle val cmd = Output(cmd_t.cloneType) val rob_id = Output(UInt(id_width.W)) - def fire(dummy: Int=0) = valid && ready + def fire = valid && ready } // TODO we don't need to store the full command in here. We should be able to release the command directly into the relevant controller and only store the associated metadata in the ROB. This would reduce the size considerably @@ -178,7 +178,7 @@ class ReservationStation[T <: Data : Arithmetic, U <: Data, V <: Data](config: G val new_entry_oh = new_allocs_oh_ld ++ new_allocs_oh_ex ++ new_allocs_oh_st new_entry_oh.foreach(_ := false.B) - val alloc_fire = io.alloc.fire() + val alloc_fire = io.alloc.fire io.alloc.ready := false.B when (io.alloc.valid) { @@ -410,7 +410,7 @@ class ReservationStation[T <: Data : Arithmetic, U <: Data, V <: Data](config: G val from_conv_fsm = entries_type(issue_id).bits.cmd.from_conv_fsm val from_matmul_fsm = entries_type(issue_id).bits.cmd.from_matmul_fsm - when (io.fire()) { + when (io.fire) { entries_type.zipWithIndex.foreach { case (e, i) => when (issue_sel(i)) { e.bits.issued := true.B @@ -519,7 +519,7 @@ class ReservationStation[T <: Data : Arithmetic, U <: Data, V <: Data](config: G val cycles_since_issue = RegInit(0.U(16.W)) - when (io.issue.ld.fire() || io.issue.st.fire() || io.issue.ex.fire() || !io.busy || io.completed.fire) { + when (io.issue.ld.fire || io.issue.st.fire || io.issue.ex.fire || !io.busy || io.completed.fire) { cycles_since_issue := 0.U }.elsewhen(io.busy) { cycles_since_issue := cycles_since_issue + 1.U diff --git a/src/main/scala/gemmini/Scratchpad.scala b/src/main/scala/gemmini/Scratchpad.scala index cdd63062..d07614b3 100644 --- a/src/main/scala/gemmini/Scratchpad.scala +++ b/src/main/scala/gemmini/Scratchpad.scala @@ -597,7 +597,7 @@ class Scratchpad[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T, acc_scale_unit.io.in.valid := acc_norm_unit_out.valid && acc_waiting_to_be_scaled acc_scale_unit.io.in.bits := acc_norm_unit_out.bits - when (acc_scale_unit.io.in.fire()) { + when (acc_scale_unit.io.in.fire) { write_issue_q.io.enq <> write_scale_q.io.deq } diff --git a/src/main/scala/gemmini/TransposePreloadUnroller.scala b/src/main/scala/gemmini/TransposePreloadUnroller.scala index 68407344..878eaa1a 100644 --- a/src/main/scala/gemmini/TransposePreloadUnroller.scala +++ b/src/main/scala/gemmini/TransposePreloadUnroller.scala @@ -2,7 +2,6 @@ package gemmini import chisel3._ import chisel3.util._ -import chisel3.experimental.ChiselEnum import org.chipsalliance.cde.config.Parameters import Util._ import midas.targetutils.PerfCounter