add small configs

ucb-bar · Sep 27, 2023 · 32e977e · 32e977e
1 parent 0064b94
commit 32e977e
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Showing 2 changed files with 47 additions and 4 deletions.
diff --git a/src/main/scala/gemmini/Configs.scala b/src/main/scala/gemmini/Configs.scala
@@ -267,6 +267,23 @@ object GemminiConfigs {
     num_counter = 0,
     clock_gate = true
   )
+  val chipsmallConfig = defaultConfig.copy(sp_capacity=CapacityInKilobytes(32), acc_capacity=CapacityInKilobytes(4), dataflow=Dataflow.WS,
+    sp_banks=4,
+    acc_banks=2,
+    acc_scale_args=Some(defaultConfig.acc_scale_args.get.copy(latency=3, num_scale_units=4)), // 4->3
+    mvin_scale_args=Some(defaultConfig.mvin_scale_args.get.copy(latency=3)), // 4->3
+    acc_singleported=false,
+    acc_sub_banks=1,
+    mesh_output_delay = 2,
+    ex_read_from_acc=false,
+    ex_write_to_spad=false,
+    has_training_convs = false,
+    hardcode_d_to_garbage_addr = true,
+    acc_read_full_width = false,
+    max_in_flight_mem_reqs = 32,
+    num_counter = 0,
+    clock_gate = true
+  )
   val largeChipConfig = chipConfig.copy(sp_capacity=CapacityInKilobytes(128), acc_capacity=CapacityInKilobytes(64),
     tileRows=1, tileColumns=1,
     meshRows=32, meshColumns=32
@@ -334,6 +351,18 @@ class ChipLeanGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
   )
 })
 
+class ChipSmallGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
+  gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.chipsmallConfig
+) extends Config((site, here, up) => {
+  case BuildRoCC => up(BuildRoCC) ++ Seq(
+    (p: Parameters) => {
+      implicit val q = p
+      val gemmini = LazyModule(new Gemmini(gemminiConfig))
+      gemmini
+    }
+  )
+})
+
 class LeanGemminiPrintfConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
   gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.leanPrintfConfig
 ) extends Config((site, here, up) => {

diff --git a/src/main/scala/gemmini/ConfigsFP.scala b/src/main/scala/gemmini/ConfigsFP.scala
@@ -113,16 +113,18 @@ object GemminiFPConfigs {
     clock_gate = true // enable this
   )
 
-  val chipFPVConfig = FP32DefaultConfig.copy(sp_capacity=CapacityInKilobytes(32), acc_capacity=CapacityInKilobytes(2), dataflow=Dataflow.WS,
+  val chipFPsmallConfig = FP32DefaultConfig.copy(sp_capacity=CapacityInKilobytes(32), acc_capacity=CapacityInKilobytes(4), dataflow=Dataflow.WS,
+    sp_banks = 4,
+    acc_banks = 2,
     //acc_scale_args=Some(defaultFPConfig.acc_scale_args.get.copy(num_scale_units=0, latency=1)),
     acc_scale_args = Some(ScaleArguments((t: Float, u: Float) => {t}, 1, Float(8, 24), -1, identity = "1.0",
       c_str = "((x))"
     )),
     //mvin_scale_args=Some(defaultFPConfig.mvin_scale_args.get.copy(num_scale_units=0)),
+    mvin_scale_args = Some(ScaleArguments((t: Float, u: Float) => {Mux(u > 0.U.asTypeOf(Float(8, 24)), t, 0.U.asTypeOf(Float(8,24)) - t)}, 1, Float(8, 24), -1, identity = "1.0", c_str="((x) * (scale))")), // 2 -> 1 stage
     mvin_scale_acc_args=None,
     acc_singleported=false,
     acc_sub_banks = 1,
-    acc_banks = 2,
     mesh_output_delay = 2,
     //acc_latency = 3,
     ex_read_from_acc=false,
@@ -132,10 +134,11 @@ object GemminiFPConfigs {
     acc_read_full_width = false,
     has_loop_conv = false,
     max_in_flight_mem_reqs = 32,
-    headerFileName = "gemmini_params_fp32v.h",
+    headerFileName = "gemmini_params_fp32.h",
     num_counter = 0,
-    //clock_gate = true
+    clock_gate = true // enable this
   )
+
   //FP16 Half Precision Configuration
   val FP16DefaultConfig = defaultFPConfig.copy(inputType = Float(5, 11), spatialArrayOutputType = Float(5, 11), accType = Float(8, 24),
                                                tile_latency = 2,
@@ -193,6 +196,17 @@ class ChipFPGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
     }
   )
 })
+class ChipSmallFPGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
+  gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiFPConfigs.chipFPsmallConfig
+) extends Config((site, here, up) => {
+  case BuildRoCC => up(BuildRoCC) ++ Seq(
+    (p: Parameters) => {
+      implicit val q = p
+      val gemmini = LazyModule(new Gemmini(gemminiConfig))
+      gemmini
+    }
+  )
+})
 //===========FP16 Default Config=========
 class GemminiFP16DefaultConfig extends Config((site, here, up) => {
   case BuildRoCC => Seq(