TopLevel output port cannot have inferred width if testing with verilator

[chick]

Problem is verilator executive attempts to generate cpp file with elaborated dut, do to so it needs widths of all top level inputs but dut has not been run through infer widths and therefore blows up.
Following demonstrates problem

import chisel3._
import chiseltest._
import chiseltest.experimental.TestOptionBuilder.ChiselScalatestOptionBuilder
import chiseltest.internal.{TreadleBackendAnnotation, VerilatorBackendAnnotation}
import org.scalatest.flatspec.AnyFlatSpec

class InferredWidthMod(val add: Boolean) extends MultiIOModule {
  val a = IO(Input(SInt(8.W)))
  val b = IO(Input(SInt(8.W)))
  val c = IO(Output(SInt()))

  c := (if (add) {
          a +% b
        } else {
          a -% b
        })
}

class VerilatorInferenceTest extends AnyFlatSpec with ChiselScalatestTester {

  behavior.of("Inferred output width should be supported by")

  it should "verilator" in {
    test(new InferredWidthMod(add = false)).withAnnotations(Seq(VerilatorBackendAnnotation)) { dut => }
  }
  it should "treadle" in {
    test(new InferredWidthMod(add = false)).withAnnotations(Seq(TreadleBackendAnnotation)) { dut => }
  }
}