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Add PTZ support to uvc device #150

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mithro opened this issue Jan 10, 2016 · 2 comments
Closed

Add PTZ support to uvc device #150

mithro opened this issue Jan 10, 2016 · 2 comments
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firmware-cypress-fx2 level-software type-enhancement type-pie-in-sky

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@mithro
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mithro commented Jan 10, 2016

From @shenki on September 3, 2014 5:37

It appears that the v4l2 uvcvideo device can support PTZ controls, and the kernel has support for this: https://lkml.org/lkml/2014/7/8/837

We should add support to our uvc device, and make the fx2 firmware pass on the commands through to the serial board that does PTZ control.

Copied from original issue: timvideos/HDMI2USB-jahanzeb-firmware#95
@mithro mithro mentioned this issue Jan 10, 2016
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mithro commented Jan 10, 2016

This will be possible after #149

@mithro mithro mentioned this issue May 19, 2017
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mithro commented May 19, 2017

This issue was moved to timvideos/HDMI2USB-fx2-firmware#15

@mithro mithro closed this as completed May 19, 2017
mithro pushed a commit that referenced this issue Jul 2, 2019
@mateusz-holenko
Updating submodules.
403f459 
 * edid-decode changed from 6def7bc to 15df4ae
    * 15df4ae - Makefile: add CPPFLAGS <Hans Verkuil>
    * dc763d7 - Update email addresses <Hans Verkuil>
    * 726576d - edid-decode: add CTA-861.4/5 support <Hans Verkuil>

 * flash_proxies changed from a628956 to 1c21ee4
    * 1c21ee4 - README: update <Robert Jördens>

 * litedram changed from d89b171 to 67de3ce
    *   67de3ce - Merge pull request #85 from antmicro/fix_databits <enjoy-digital>
    |\
    | * 24851c9 - PhySettings: set missing databits parameter for S6QuarterRateDDRPHY <Mateusz Holenko>
    * | fef5303 - test: clean test_downconverter/test_upconverter (thanks sb0) <Florent Kermarrec>
    |/
    *   7fbe0b7 - Merge pull request #84 from open-design/is42s16320 <enjoy-digital>
    |\
    | * 5c66547 - modules: SDRAM: add IS42S16320 support <Antony Pavlov>
    |/
    * 8e2df17 - modules: fix tRFC change on MT16KTF1G64HZ <Florent Kermarrec>
    * bc88cfa - modules: allow tRFC to be defined in ck or ns, fix some DDR3/DDR4 definitions (thanks @ambrop72 for the review) <Florent Kermarrec>
    * fbd7ae3 - modules: make IS43TR16128B consistent with others SDRAMModules <Florent Kermarrec>
    *   02448a3 - Merge pull request #83 from ambrop72/IS43TR16128B_125K <enjoy-digital>
    |\
    | * d108970 - modules/ddr3: add IS43TR16128B_125K <Ambroz Bizjak>
    |/
    *   da68e21 - Merge pull request #82 from gsomlo/gls-expose-csr <enjoy-digital>
    |\
    | * 65451f4 - examples/litedram_gen: allow direct access to CSR (I/O) registers <Gabriel L. Somlo>
    |/
    * 50e1d47 - PhySettings: add databits to allow SoC to compute memory size more easily <Florent Kermarrec>
    * b93412b - examples: remove verilog simulation <Florent Kermarrec>
    * a7e46bb - example/litedram_gen: reserve_nmi_interrupt no longer exists <Florent Kermarrec>
    *   094fc2e - Merge pull request #79 from gsomlo/gls-ulong-addr <enjoy-digital>
    |\
    | * 54d3312 - sdram_init: use "unsigned long" for address values <Gabriel L. Somlo>
    |/
    * 3caaa2e - common/tXXDController: revert Yosys workarounds <Florent Kermarrec>
    * 44bbb93 - phy: add copyrights <Florent Kermarrec>
    * 6ddc2c8 - README: update <Florent Kermarrec>
    * 9190a76 - travis: simplify and add RISC-V toolchain to run examples <Florent Kermarrec>
    * e824288 - frontend/axi: move AXIBurst2Beat to LiteX <Florent Kermarrec>
    * be269da - frontend/axi: use definitions from LiteX <Florent Kermarrec>
    * e81b5a1 - sdram_init: set __attribute__((unused)) on command_px to avoid compilation warning <Florent Kermarrec>
    * c4161cf - examples: update sim <Florent Kermarrec>
    * 201a0e2 - test/test_examples: add nexys4ddr <Florent Kermarrec>
    * 69afaf5 - common: add separators, reorganize a bit <Florent Kermarrec>
    * 0bc241c - phy/ecp5ddrphy: use inline comments on ECP5DDRPHYInit <Florent Kermarrec>
    * c65ff97 - phy/ecp5ddrphy: simplify ECP5DDRPHYInit, integrate it in the PHY, add burstdet registers <Florent Kermarrec>
    * 4274db8 - common/TXXDcontroller: fix for compatibility with Yosys and vendor tools <Florent Kermarrec>
    * a74d5c9 - common/TXXDcontroller: set ready default value to 1 with self.comb instead of reset value <Florent Kermarrec>
    *   cec35f3 - Merge pull request #77 from daveshah1/ecp5_75MHz <enjoy-digital>
    |\
    | * fa26dcd - ecp5ddrphy: Shift read position forwards to fix higher frequencies <David Shah>
    |/
    *   6715c1b - Merge pull request #76 from daveshah1/trellis_io <enjoy-digital>
    |\
    | * 691d930 - ecp5ddrphy: Use triples for inputs to fix build with TRELLIS_IOs <David Shah>
    |/
    * 9057f51 - phy: add ECP5 imports <Florent Kermarrec>
    * f660618 - phy: add initial ECP5DDRPHY <Florent Kermarrec>
    * 640194a - examples: add nexys4ddr_config <Florent Kermarrec>
    * 0ac1af3 - examples/litedram_gen: add DDR2 support <Florent Kermarrec>
    * f4184ec - example/litedram_gen: update, add descriptions of config parameters <Florent Kermarrec>
    * 79806aa - modules/ddr3: add MT41K64M16 <Florent Kermarrec>
    * ea6b841 - phy/s7ddrphy and usddrphy: add cmd_latency parameter <Florent Kermarrec>
    * fd3e9af - phy/s7ddrphy: fix cmd delays <Florent Kermarrec>
    * f61c8d9 - phy/s7ddrphy: make clk/cmd odelaye2s configurable <Florent Kermarrec>
    * e0224f4 - phy/usddrphy: make clk/cmd odelaye3s configurable <Florent Kermarrec>

 * liteeth changed from 77fa4bf to 2424e62
    * 2424e62 - software: also include generated/mem.h <Florent Kermarrec>
    * e88fc50 - software: remote ethmac_mem.h dependency (no longer exists in LiteX) <Florent Kermarrec>
    * b318300 - phy/ku_1000basex: keep tx/rx in reset until pll is fully reseted and locked <Florent Kermarrec>
    * e6c35cd - phy/ku_1000basex: incease pll_reset <Florent Kermarrec>
    * 816f592 - phy: add initial ECP5RGMII PHY <Florent Kermarrec>
    * b4c1cfe - core/icmp: fix reply checksum when request checksum >= 0xf800 <Florent Kermarrec>

 * litepcie changed from 3804c49 to de6cd01
    * de6cd01 - frontend/dma: ensure we finish LitePCIeDMAWriter transaction when DMA is disabled. <Florent Kermarrec>
    * 260c562 - frontend/wishbone: cleanup qword_aligned support <Florent Kermarrec>
    * 89b3920 - README: update <Florent Kermarrec>
    * 22310cc - phy: add initial Cyclone5 support <Florent Kermarrec>
    * 9cdb982 - phy/s7pciephy: rename external_phy to external_hard_ip <Florent Kermarrec>
    * 3b6cffd - frontend/wishbone: add qword_aligned parameter <Florent Kermarrec>
    * d191b1e - core: add endianness support <Florent Kermarrec>
    * 4df720a - examples/targets/dma: remove typo (dma connection is done internally in loopback mode) <Florent Kermarrec>
    * 14d852e - examples/targets/dma: remove soft reset, simplify crg, minor cleanups <Florent Kermarrec>
    * 64857af - phy/s7pciephy: improve presentation <Florent Kermarrec>
    * 55fa0d4 - phy/s7pciephy: remove pcie clk presence detection. <Florent Kermarrec>
    * f042273 - phy/s7pciephy: allow using external sources for the PHY. <Florent Kermarrec>
    * bd5d4dc - phy/s7pciephy: remove unnecessary reset on pcie clock domain <Florent Kermarrec>
    * ccfb201 - frontend/dma: update loop_status when request is sent <Florent Kermarrec>

 * litesata changed from b78a731 to 6fe4cce
    * 6fe4cce - examples/targets/bist: simplify analyzer <Florent Kermarrec>
    * 846bd62 - phy/a7sataphy: rework tx/rx_startup_fsm using liteiclink code <Florent Kermarrec>
    * 5e02ac9 - phy/a7sataphy: use proper transceiver name <Florent Kermarrec>
    * e63c8aa - examples/test/test_analyzer: use shorter import <Florent Kermarrec>
    * 319dd72 - examples/targets/bist: update <Florent Kermarrec>
    * df27cdf - examples/targets: add bist_nexys_video (still wip) <Florent Kermarrec>
    *   2ba5508 - Merge pull request #15 from enjoy-digital/artix7 <enjoy-digital>
    |\
    | * 0b254b0 - examples/make: remove platform option <Florent Kermarrec>
    | * e0fc55c - examples/targets/bist: revert kc705/genesys2 bist example <Florent Kermarrec>
    | * cabc908 - example: add led blinking on refclk, add startup fsm to analyzer <Florent Kermarrec>
    | * d16b495 - examples: add more debug, rx/tx leds not blinking (no clock? bad init?) <Florent Kermarrec>
    | * 1519dc3 - targets/bist: use 100 MHz clock, fix reset polarity <Florent Kermarrec>
    | * 1fe543f - phy/a7sataphy: integrate GTPQuadPLL <Florent Kermarrec>
    | * ca47e05 - examples/targets/bist: start artix7 testing with sata_gen1 <Florent Kermarrec>
    | * 1fc848e - examples: add nexys_video support <Florent Kermarrec>
    | * 9152729 - phy/a7sataphy: update parameters from wizard <Florent Kermarrec>
    | * ef5d0b9 - phy: add initial a7sataphy <Florent Kermarrec>
    | * 12b5085 - phy/k7sataphy: remove drp interface (not used) <Florent Kermarrec>
    | * 246487c - phy/k7sataphy: improve readibility <Florent Kermarrec>
    | * 41f4446 - phy/k7sataphy: make GTXE2_CHANNEL instance similar to gtx_7series in liteiclink <Florent Kermarrec>
    | * 27df062 - phy: replace trx_dw with data_width <Florent Kermarrec>
    | * d52c7b8 - phy/k7sataphy: remove ones <Florent Kermarrec>
    | * 1d1da98 - phy/k7sataphy: refactor gtxe2_channel instance <Florent Kermarrec>
    | * 10d6376 - phy: move k7 phy to a single k7sataphy file <Florent Kermarrec>
    * 7299fef - example/make.py: create the build directory when building the core if not existing <Florent Kermarrec>

 * litescope changed from c1d8bdf to 2474ce9
    * 2474ce9 - software/dump/common: change variable name for values2x loop (thanks keesj) <Florent Kermarrec>
    * 7f20aa4 - examples/make/build-core: create build directory if not existing <Florent Kermarrec>

 * litex changed from af52842f to 113f7f40
    *   113f7f40 - Merge pull request #199 from ambrop72/no-ethmac-fix <enjoy-digital>
    |\
    | * ca70ea91 - bios: Fix build when ethphy is present but ethmac is not. <Ambroz Bizjak>
    |/
    * ab1f5804 - test/test_axi: remove litex.gen.sim import (was only useful for debug) <Florent Kermarrec>
    * 5318bcd3 - setup.py: add migen to install_requires <Florent Kermarrec>
    *   33d7cc5f - Merge pull request #198 from TomKeddie/tomk_20190610_artyspi <enjoy-digital>
    |\
    | * 5346c368 - boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2 <Tom Keddie>
    * | 38a2d89a - test/test_code8b10b: add test_coding <Florent Kermarrec>
    * | 8fdd5220 - test/test_prbs: add PRBSGenerator/Checker tests <Florent Kermarrec>
    * | 243d7c76 - soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker <Florent Kermarrec>
    * | cfa952b0 - tools/litex_term: exit on 2 consecutive CTRL-C <Florent Kermarrec>
    * | 1c34b4a0 - cpu/vexriscv: update submodule <Florent Kermarrec>
    * | 79665873 - doc: add litex-hub logo <Florent Kermarrec>
    * | 442d7358 - doc: redesign new logo <Florent Kermarrec>
    * | 59118627 - doc: add new logo <Florent Kermarrec>
    * | 850b311d - cpu/vexriscv: update submodule <Florent Kermarrec>
    * | 755a2660 - build/sim: allow configuring verilator optimization level <Florent Kermarrec>
    * | 4b6ad8aa - build/sim: allow defining start/end cycles for tracing <Florent Kermarrec>
    * | ecb60f6e - build/sim: use -O0 for verilator compilation <Florent Kermarrec>
    * | c64129dc - soc/integration/soc_core: list rocket as supported CPU <Florent Kermarrec>
    * | ca4e7811 - software/bios: change prompt to "litex" in green. <Florent Kermarrec>
    * | 8d0f008a - integration/soc_core: improve readibility (add separators/comments) <Florent Kermarrec>
    * | 55ebcc00 - test/test_targets: add de10lite <Florent Kermarrec>
    * |   e545b15f - Merge pull request #196 from msloniewski/de10lite_support <enjoy-digital>
    |\ \
    | * | 04ce4790 - boards/targets: add target for de10lite platform <msloniewski>
    | * | f2a740d5 - boards/platforms: add de10lite Terasic platform support <msloniewski>
    | * | a826aaca - build/altera: Add possibility to turn off generation of .rbf file <msloniewski>
    * | |   77805a5e - Merge pull request #195 from antmicro/extend_generated_headers <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 93b61a65 - integration/builder: generate flash_boot address to csv <Mateusz Holenko>
    | * | d0b019b1 - integration/builder: generate shadow_base address to mem.h and csv <Mateusz Holenko>
    |/ /
    * |   cb2d4372 - Merge pull request #193 from gsomlo/gls-memcpy-fix <enjoy-digital>
    |\ \
    | * | f88b85a3 - software/libbase: memcpy: simple, arch-width agnostic implementation <Gabriel L. Somlo>
    |/ /
    * |   42e9d097 - Merge pull request #192 from sutajiokousagi/pr_c99_types <Tim Ansell>
    |\ \
    | * | ab0b2cac - fix signed char type to be explicitly signed <bunnie>
    * | |   b0d35a49 - Merge pull request #191 from sergachev/master <Tim Ansell>
    |\ \ \
    | * | | db890736 - fix csr_name in add_csr() <Ilia Sergachev>
    | * | | 40cbe3a9 - fix interrupt_name <Ilia Sergachev>
    |/ / /
    * | | b300c321 - test/test_targets: add de2_115, de1soc <Florent Kermarrec>
    * | | 220e2bdc - boards/platform/arty: add Arty A7-100 variant <Florent Kermarrec>
    * | |   8e6ecfb9 - Merge pull request #189 from open-design/terasic-boards <enjoy-digital>
    |\ \ \
    | * | | 6cf1a814 - boards: add Terasic DE2-115 initial support <Antony Pavlov>
    | * | | 03725991 - boards: add Terasic DE1-SoC Board support <Antony Pavlov>
    * | | |   9682189b - Merge pull request #190 from sutajiokousagi/pr_c99_types <Tim Ansell>
    |\ \ \ \
    | |/ / /
    |/| / /
    | |/ /
    | * | 200d413d - update stdint.h to include c99 types <bunnie>
    |/ /
    * |   a48858f8 - Merge pull request #188 from gsomlo/gls-csr-cleanup <enjoy-digital>
    |\ \
    | * | 273a3ea1 - soc/integration/cpu_interface: improve code legibility <Gabriel L. Somlo>
    |/ /
    * | 08a811b1 - soc/interconnect/gearbox: add msb_first/lsb_first order <Florent Kermarrec>
    * | 675f7830 - boards/targets/arty: generate 25MHz ethernet clock with S7PLL <Florent Kermarrec>
    * |   d7b00c8c - Merge pull request #187 from open-design/indent <Tim Ansell>
    |\ \
    | * | 26e6355f - litex/boards/targets: don't use tab for indentation <Antony Pavlov>
    |/ /
    * | 51095112 - soc/interconnect/axi: add round/robin arbitration between writes/reads <Florent Kermarrec>
    * | 0fb6342f - travis: update RISC-V toolchain <Florent Kermarrec>
    * | 961101d8 - bios/irc: remove compilation workaround <Florent Kermarrec>
    * | cd543b29 - README: update RISC-V toolchain <Florent Kermarrec>
    * | 7e837bf1 - .gitmodules/rocket: switch to https://github.com/enjoy-digital/rocket-litex-verilog <Florent Kermarrec>
    * | 712977a0 - software/bios/isr.c: workaround compilation issue (need to be fixed) <Florent Kermarrec>
    * | 28ba8b32 - soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now) <Florent Kermarrec>
    * | cf369c43 - boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it) <Florent Kermarrec>
    * |   aa640f29 - Merge pull request #186 from gsomlo/gls-rocket <enjoy-digital>
    |\ \
    | * | 019fd940 - fixup: generated-verilog submodule for experimental Rocket support <Gabriel L. Somlo>
    | * | 1a530cf2 - soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental) <Gabriel L. Somlo>
    |/ /
    * |   3de49118 - Merge pull request #185 from gsomlo/gls-sim-sdram <enjoy-digital>
    |\ \
    | |/
    |/|
    | * e90caa86 - tools/litex_sim: restore functionality of '--with-sdram' option <Gabriel L. Somlo>
    |/
    *   3a72688b - Merge pull request #183 from xobs/usb-to-0x43 <enjoy-digital>
    |\
    | * 014c9505 - remote: usb: print "access denied" error <Sean Cross>
    | * faf6554c - remote: usb: use 0x43/0xc3 for packet header <Sean Cross>
    |/
    * 10670e22 - soc/cores/minerva: update to latest <Florent Kermarrec>
    *   a3134f13 - Merge pull request #182 from gsomlo/gls-nexys4-eth-fixup <enjoy-digital>
    |\
    | * 5707bdc0 - boards/nexys4ddr: ethernet support fix-up <Gabriel L. Somlo>
    |/
    *   0a8699f1 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | * 1ea22d49 - software/include/base/csr-defs.h: add specific CSR_IRQ_MASK/PENDING for Minerva <Florent Kermarrec>
    * | 526ba1b1 - soc_core: remove csr_expose and add add_csr_master method <Florent Kermarrec>
    |/
    * f2570701 - software/bios/boot: remove specific linux commands (not needed with device tree) <Florent Kermarrec>
    * 938d00c2 - boards/targets/de0nano: reduce to 50MHz sys_clk, simplify CRG <Florent Kermarrec>
    * 11838bae - platforms/de0nano: change serial pins (put then next to the GND pin) <Florent Kermarrec>
    * eb6fa458 - cpu/vexriscv/core: update <Florent Kermarrec>
    * 0cad80e9 - cpu/vexriscv: update submodule (new linux variant) <Florent Kermarrec>
    * 5f6e7874 - boards/nexys4ddr: add ethernet support (RMII 100Mbps) <Florent Kermarrec>
    * 0ba1cb87 - boards/targets/netv2: +x <Florent Kermarrec>
    * 2f2b9b31 - soc/cores: remove cordic <Florent Kermarrec>
    * 6e4ac1c4 - LICENSE: clarify <Florent Kermarrec>
    * 67159349 - soc/interconnect: remove axi_lite <Florent Kermarrec>
    * 745d83a3 - boards: add initial NeTV2 support (clocks, leds, dram, ethernet) <Florent Kermarrec>
    * a49d170a - soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy <Florent Kermarrec>
    * 7445b9e2 - soc/integration/soc_core: allow user to defined internal csr/interrupts <Florent Kermarrec>
    * f333abcf - boards/targets: use new add_csr method <Florent Kermarrec>
    * d76a2c7d - tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method) <Florent Kermarrec>
    * b6be534c - soc/integration/soc_core: rework csr assignation/reservation <Florent Kermarrec>
    * 3f09af6d - boards/targets: declare ethmac interrupt with new add_interrupt method <Florent Kermarrec>
    *   2abb3e80 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   c11eb4b5 - Merge pull request #179 from gsomlo/gls-xtra-addrlen <enjoy-digital>
    | |\
    | | * c264a009 - soc/integration/cpu_interface: more arch-specific address size fixes <Gabriel L. Somlo>
    | |/
    * | 47dc8758 - integration/soc_core: rework interrupt assignation/reservation <Florent Kermarrec>
    * | 3ee9ce05 - test/test_targets: fix test_ulx3s name <Florent Kermarrec>
    * | 435cdad0 - boards/targets: fix ulx3s/versa_ecp5 build <Florent Kermarrec>
    * | 8caa38bc - cpu: add `reserved_interrupts` property <Mateusz Holenko>
    * | ff517915 - boards/targets: make sys_clk_freq a parameter <Florent Kermarrec>
    |/
    * a8cbe4ad - boards/targets/minispartan6: for now revert experimental s6pll clocking <Florent Kermarrec>
    * 6fcbf10e - boards/plarforms/minispartan6: default to xc6slx25 <Florent Kermarrec>
    * b7e37133 - bios/boot/ update linux memory mapping <Florent Kermarrec>
    * 190ff89a - tools/litex_term: add json support to load images to memory, allow passing speed as float <Florent Kermarrec>
    *   a50aff2c - Merge pull request #178 from daveshah1/vexriscv_linux_yosys <enjoy-digital>
    |\
    | * a048ba47 - vexriscv: Fix some floating signals <David Shah>
    |/
    * fcd518b5 - bios/boot: add specific flash_boot for linux with vexriscv <Florent Kermarrec>
    * 1ba1ad9a - bios/boot: rename MM_RAM to EMULATOR_RAM <Florent Kermarrec>
    * fbb24720 - soc/get_mem_data: add direct support for regions <Florent Kermarrec>
    * 0714816f - soc/interconnect/axi: add AXI2AXILite converter and use it in  AXI2Wishbone <Florent Kermarrec>
    * c6d0d234 - soc/interconnect/axi: add AXI Lite definition <Florent Kermarrec>
    * 9fab4752 - soc/interconnect/axi: add comment on axi signas that are present but not used <Florent Kermarrec>
    * 59890763 - cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant <Florent Kermarrec>
    * 21bf1038 - bios/boot: add liftoff banner just before booting <Florent Kermarrec>
    * 8f4685b3 - bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config <Florent Kermarrec>
    * 6cf1ff09 - soc/interconnect/axi: connect axi.ar/aw when selecting write or read <Florent Kermarrec>
    * 6affc56a - soc/interconnect/axi: wishbone address shift is not always 2, make it generic <Florent Kermarrec>
    * 698bc882 - soc/interconnect/wishbone: allow setting adr_width (default to 30) <Florent Kermarrec>
    * 4dccb8a9 - soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent <Florent Kermarrec>
    * 9f8f0eb1 - build/sim: update tapcfg <Florent Kermarrec>
    *   2515c7b0 - Merge pull request #176 from gsomlo/gls-ulong-addr <enjoy-digital>
    |\
    | * 5c2b8685 - software: use "unsigned long" for address values, also 8-byte alignment <Gabriel L. Somlo>
    |/
    * 74d37465 - test/test_targets: comment bad variant tests for now <Florent Kermarrec>
    * 5c1d9805 - soc/interconnect/axi: add burst support to AXI2Wishbone <Florent Kermarrec>
    * 6de27135 - soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize <Florent Kermarrec>
    * 305b8879 - integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k) <Florent Kermarrec>
    * 4e50f36b - build/tools: add deprecated_warning <Florent Kermarrec>
    * b40d1b73 - cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang) <Florent Kermarrec>
    * dbb71af1 - cpu: use property methods to return name, endianness, gcc triple/flags, linker output format <Florent Kermarrec>
    * d828c3a5 - cpu: integrate nmigen version of Minerva, add submodule <Florent Kermarrec>
    * 2c3c6bdf - Updating documents from LiteX BuildEnv Wiki <Florent Kermarrec>
    * bf27869a - fix vexriscv build <Kurt Kiefer>
    *   2d5bae3d - Merge pull request #175 from mithro/cpu-docs <enjoy-digital>
    |\
    | * 5cbc5bc1 - Adding testing of cpu variants. <Tim 'mithro' Ansell>
    | * 71a83731 - Work with no `cpu_variant` provided. <Tim 'mithro' Ansell>
    | * 65650919 - Updating documents from LiteX BuildEnv Wiki <Tim 'mithro' Ansell>
    | * a43de819 - Updating documents from LiteX BuildEnv Wiki <Tim 'mithro' Ansell>
    | * 39c579ba - Standardize the `cpu_variant` strings. <Tim 'mithro' Ansell>
    | * e42de8fe - docs: Adding script to pull useful docs from LiteX BuildEnv's wiki. <Tim 'mithro' Ansell>
    * | 3a2e2836 - .gitmodules: use our VexRiscv-verilog <Florent Kermarrec>
    |/
    * 78c09125 - soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes <Florent Kermarrec>
    * 0175f86c - soc/integration/soc_core: fix get_mem_data for json files <Florent Kermarrec>
    * 4443b507 - soc/integration/soc_core: add integrated_sram_init <Florent Kermarrec>
    * f27084c6 - soc/integration/cpu_interface: fix banner in get_mem_header <Florent Kermarrec>
    *   5ec99d94 - Merge pull request #173 from gsomlo/gls-git-revision <enjoy-digital>
    |\
    | * d21cba2f - build: handle exceptional case when litex/migen not deployed as git repo <Gabriel L. Somlo>
    |/
    * 27fbb814 - tools/remote/csr_builder: allow comments in csv file and cleanup <Florent Kermarrec>
    * e8f3c491 - software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding <Florent Kermarrec>
    * 44e0cdda - software/libnet/microudp: speed-up ARP by changing timeout/tries <Florent Kermarrec>
    * 3ee78a5b - build/tools: fix typo <Florent Kermarrec>
    * f0fe9f3c - setup.py: add short names for tools <Florent Kermarrec>
    * 9ded2eb2 - tools/litex_term: change TERM prompt to LXTERM <Florent Kermarrec>
    * 475deb51 - build: add migen and litex git revision to generated file <Florent Kermarrec>
    * 8b5cf295 - build/tools: git_revision is not doing what we want, return "--------" for now <Florent Kermarrec>
    * 228f2867 - litex_setup: revert default install behaviour but add --user support <Florent Kermarrec>
    *   9fbbf928 - Merge pull request #171 from keesj/develop_as_user <enjoy-digital>
    |\
    | * 24bdb648 - Install development packages in the user directory <Kees Jongenburger>
    * | 0f60ec35 - tools/litex_server: fix comms import <Florent Kermarrec>
    * | 68f12495 - soc/integration: also add sha-1/date to generated software files <Florent Kermarrec>
    * | 42574122 - build: add sha-1/date to generated verilog, change git_version to git_revision <Florent Kermarrec>
    |/
    * f7c0b118 - test/test_targets: cover all platforms <Florent Kermarrec>
    * 818dfae1 - boards/platforms/ulx3s: fix default clock <Florent Kermarrec>
    * 17b6164c - boards/platforms/sp605: apply same simplifications than on others platforms <Florent Kermarrec>
    * 24bf0293 - boards/platforms: add SP605 <Michael Betz>
    * 10cf0fde - cores/cpu/vexriscv: fix wrong revert <Florent Kermarrec>
    * d2ad1441 - targets/ac701: cleanup and make it similar to others targets. <Florent Kermarrec>
    * a24bf72f - targets/xilinx: remove keep attribute on clock going to idelayctrl <Florent Kermarrec>
    * ea8dbff8 - boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms <Florent Kermarrec>
    * 0122982e - boards/platforms/kc705: provide only one default programmer as others platforms <Florent Kermarrec>
    * 89a59026 - boards: Xilinx ac701 dev board support <Vamsi K Vytla>
    * 88b882c7 - build/xilinx/ise.py: write .v file for post synthesis sim <Michael Betz>
    * 7396ebbb - build/xilinx/programmer: cleanup XC3SProg position parameter <Florent Kermarrec>
    * f579cbc6 - build/xilinx/programmer: add position parameter to XC3SProg <Michael Betz>
    * fb4f8818 - .gitignore: ignore tilde files <Vamsi K Vytla>
    * 535d8672 - targets/minispartan6: use S6PLL in CRG <Florent Kermarrec>
    * 40342404 - cores/clock: add divclk_divide_range on S6PLL/S6DCM <Florent Kermarrec>
    * 0d282f38 - cores/clock: use common XilinxClocking class for all Xilinx clocking modules <Florent Kermarrec>
    * 83699ea0 - cores/clock: add initial Spartan6 PLL/DCM support <Michael Betz>
    * eff141da - build: add git version (sha-1) used to create the scripts <Florent Kermarrec>
    * cc141a64 - build: scripts are generated by LiteX <Florent Kermarrec>
    * 115c842e - build/xilinx/vivado: cleanup pull request #170 <Florent Kermarrec>
    *   3b24b8d5 - Merge pull request #170 from ldoolitt/master <enjoy-digital>
    |\
    | * fda18fd6 - build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path <Larry Doolittle>
    |/
    * 7d278854 - global: switch to VexRiscv as the default CPU <Florent Kermarrec>
    * 28d80bd6 - ci: fix test_targets/test_simple <Florent Kermarrec>
    * b7f53fb9 - test: remove waveforms generation <Florent Kermarrec>
    * e98ac680 - travis: simplify, enable and add RISC-V toolchain to build targets <Florent Kermarrec>
    * 8c789970 - boards/platforms: add separators, cleanup imports <Florent Kermarrec>
    * cb8c26d1 - boards/platforms: provide only one default programmer per platform. <Florent Kermarrec>
    * e1d202df - boards/platforms/kc705: only keep Vivado support <Florent Kermarrec>
    * 53c7be6e - boards: always define timing constraints the same way (1e9/freq_mhz) <Florent Kermarrec>
    * 02ffbed5 - boards/targets/ulx3s: allow running test_targets on it <Florent Kermarrec>
    * 5a1925df - boards/targets: add keep attribute directly in crg <Florent Kermarrec>
    *   67a79d7c - Merge pull request #167 from xobs/network-flag-check <enjoy-digital>
    |\
    | * f71b8d4f - litex_server: check socket flags exist before using them <Sean Cross>
    |/
    * 9ee6c35b - tools: move from litex.soc.tools to litex.tools and fix usb.core import <Florent Kermarrec>
    *   49fd93ae - Merge pull request #165 from xobs/vexriscv-cpu-reset-address <enjoy-digital>
    |\
    | *   c780fb22 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Sean Cross>
    | |\
    | * | e2cf45b8 - cpu: vexriscv: allow cpu_reset_address to be overridden <Sean Cross>
    * | |   ca6065a6 - Merge pull request #164 from xobs/litex-usb-server <enjoy-digital>
    |\ \ \
    | * | | c6918364 - utils: litex_server: add usb support <Sean Cross>
    | * | | 9dd59d63 - tools: remote: add usb communications protocol <Sean Cross>
    * | | | 9cbed91b - soc/interconnect/axi: add AXIBurst2Beat <Florent Kermarrec>
    * | | | 5a8115d9 - soc/interconnect/avalon: add description <Florent Kermarrec>
    | |_|/
    |/| |
    * | | fa956086 - soc/integration/soc_zynq: fix HP0 connections <Florent Kermarrec>
    * | | a78ca2de - build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog) <Florent Kermarrec>
    |/ /
    * | a92e90b2 - soc/interconnect: add avalon with converters to/from native streams <Florent Kermarrec>
    * |   d860eeea - Merge pull request #162 from antmicro/full-conf-vexriscv <enjoy-digital>
    |\ \
    | * | 40de01bc - vexriscv: Add full and full_debug CPU variant <Joanna Brozek>
    * | |   ce81a39c - Merge pull request #163 from gsomlo/gls-verilated-cmdargs <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | e1683078 - build/sim/core: Initialize Verilator commandArgs <Gabriel L. Somlo>
    |/ /
    * | 017147c6 - build/altera: switch to sdc constraints, add add_false_path_constraints method <Florent Kermarrec>
    * | 1275e2f1 - build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints <Florent Kermarrec>
    * | c252972b - soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale <Florent Kermarrec>
    * | f986974d - soc/cores/clock: improve presentation <Florent Kermarrec>
    * | 538ca59a - build/xilinx/vivado: round period constraints to lowest picosecond <Florent Kermarrec>
    * |   66a74b15 - Merge pull request #161 from enjoy-digital/litex_server_arguments <enjoy-digital>
    |\ \
    | * | a2bc4bb7 - litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination <Florent Kermarrec>
    | * | be99083e - litex_server: add message and exit when mandarory arguments are missing. <Florent Kermarrec>
    | * | db11aec9 - litex_server: allow setting bind port, remove auto-incrementing on bind_port <Florent Kermarrec>
    | * | 76bc5785 - litex_server: refactor parameters and to allow setting bind address <Florent Kermarrec>
    |/ /
    * | 13a76ec7 - software/libnet/microudp: simplify txbuffer managment <Florent Kermarrec>
    * | 3441eb05 - software/libnet/microudp: cleanup eth_init <Florent Kermarrec>
    * | 92a79c6d - software/libnet/microudp: simplify rxbuffer managment <Florent Kermarrec>
    * | fdeff7f6 - software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE <Florent Kermarrec>
    * | 1569e2e0 - software/libnet: remove use of ethmac_mem.h <Florent Kermarrec>
    * | c7ac9676 - bios/sdram: add __attribute__((unused)) on cdelay <Florent Kermarrec>
    * | 7e53bff3 - litex_setup: add litesata <Florent Kermarrec>
    * | 792245f1 - boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter) <Florent Kermarrec>
    * | f8dcdb70 - software/libnet: add #ifdef on eth_init <Florent Kermarrec>
    * |   e475cfbb - Merge pull request #158 from vbuitvydas/altera-contrib <enjoy-digital>
    |\ \
    | * | 04939990 - litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name <vytautasb>
    | * | 8558065f - litex/build/altera/common: added reset synchronizer <vytautasb>
    |/ /
    * | 866fa344 - integration/soc_zynq: fix missing SoCCore.do_finalize <Florent Kermarrec>
    * | 794c3c58 - integration/soc_zynq: add add_hp0 method <Florent Kermarrec>
    * | 38d404c3 - integration/soc_zynq: use add methods to add optional peripherals <Florent Kermarrec>
    * | 7375856b - integration/soc_zynq: connect axi signals that were missing <Florent Kermarrec>
    * | b15fd9d8 - interconnect/axi: add missing axi signals <Florent Kermarrec>
    * |   f95748d1 - Merge pull request #157 from CBJamo/master <enjoy-digital>
    |\ \
    | * | 1f0b3f81 - Add ifdef check for MAIN_RAM_SIZE <Caleb Jamison>
    |/ /
    * | f452d3e9 - README: bump copyright year <Florent Kermarrec>
    * | dd214d2d - bios/main: align SoC info, show CPU speed on CPU line, show L2 <Florent Kermarrec>
    * | 6599f7bb - bios/main: move sdrinit <Florent Kermarrec>
    * | b92b89ab - bios/main: print boot sequence only if sdr_ok <Florent Kermarrec>
    * | f4369c8f - bios/main: remove csr functions (not used and only supported by lm32), improve help presentation <Florent Kermarrec>
    * | 66dffb70 - software/bios: improve readibility, add soc informations <Florent Kermarrec>
    * |   e8559990 - Merge pull request #156 from gsomlo/gls-axi-width <enjoy-digital>
    |\ \
    | * | 449632e4 - soc/interconnect/axi: data/address length cleanup <Gabriel L. Somlo>
    |/ /
    * | 552b0243 - soc/interconnect/axi: remove dead code (thanks gsomlo) <Florent Kermarrec>
    * |   b682dacd - Merge pull request #154 from daveshah1/yosys_xilinx_edif <enjoy-digital>
    |\ \
    | * | 57e1ccd5 - build/xilinx: Update Yosys write_edif parameters <David Shah>
    * | | fd7ed6c1 - utils/litex_sim: fix main_ram_size <Florent Kermarrec>
    * | | 3f386dad - soc_core/get_mem_data: add json support <Florent Kermarrec>
    * | | 7bc13ba8 - build/microsemi/libero_soc: add linux build script support <Florent Kermarrec>
    * | | 7b88980d - vexriscv: allow user to use an external variant <Florent Kermarrec>
    * | | b04a756a - vexriscv/core: fix min variant <Florent Kermarrec>
    * | | a549f094 - utils/litex_sim: handle cpu_endianness for rom-init/ram-init <Florent Kermarrec>
    * | | 411bca79 - utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified <Florent Kermarrec>
    * | |   7ec3ed4d - Merge pull request #153 from railnova/fix_utils <enjoy-digital>
    |\ \ \
    | * | | aed2e9b4 - [fix] utils was not installed from pip <chmousset>
    | |/ /
    * | |   3543b567 - Merge pull request #152 from gsomlo/gls-trellis-svf <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | b014c719 - build/lattice/trellis: also generate bitstream in svf format <Gabriel L. Somlo>
    |/ /
    * | 317dba83 - software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation <Florent Kermarrec>
    * | 7de1fe51 - targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC <Florent Kermarrec>
    * | ca63db40 - bios/sdram: use burstdet detection for ECP5DDRPHY init <Florent Kermarrec>
    |/
    *   2ebfab5e - Merge pull request #150 from daveshah1/trellis_bus_fixes <enjoy-digital>
    |\
    | * ebe8f600 - lattice/common: Fix tristate buses with Trellis <David Shah>
    |/
    * 935f3a53 - boards/ulx3s: add device selection parameter <Florent Kermarrec>
    * e6f97e08 - targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25 <Florent Kermarrec>
    * 5ef28bdf - build/lattice/trellis: add package support <Florent Kermarrec>
    * 1b34c07d - build/lattice/trellis: basecfg now integrated in nextpnr <Florent Kermarrec>
    * 7e995eb4 - boards/targets/ulx3s: allow building with diamond or trellis <Florent Kermarrec>
    * 4bf789ea - soc/software/bios/boot: add vexriscv workaround <Florent Kermarrec>
    * 1fd81c28 - soc/integration: add initial SoCZynq SoC <Florent Kermarrec>
    * 3c527dcb - soc/interconnect: add initial axi code with bus definition and AXI2Wishbone <Florent Kermarrec>
    * ed257879 - test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified) <Florent Kermarrec>
    * 4aa07f2a - soc/interconnect: rename axi to axi_lite <Florent Kermarrec>
    * 6a4c133c - test: add basic test_csr <Florent Kermarrec>
    *   c9f9e237 - Merge pull request #149 from daveshah1/versa_trellis <enjoy-digital>
    |\
    | * ff7e0fab - versa_ecp5: Add option to build with Trellis <David Shah>
    | * 024b41c5 - trellis: Add LPF frequency constraints and remove -nomux <David Shah>
    * | e38dfd99 - soc/software/sdram: fix compilation on ultrascale <Florent Kermarrec>
    |/
    * 5f29a12e - targets/versa_ecp5: integrate DDR3 <Florent Kermarrec>
    * 3dd529e4 - soc/software/bios/sdram: add ECP5 support <Florent Kermarrec>
    * 2fd6d0e7 - soc/software/bios/sdram: improve write_level robustness <Florent Kermarrec>
    * 36772b75 - soc/software/bios/sdram: improve sdrlevel readibility <Florent Kermarrec>
    * 6a980781 - soc/software/bios/sdram: add helpers for rst/inc of delays <Florent Kermarrec>
    *   dad7b292 - Merge pull request #148 from daveshah1/versa_remove_n <enjoy-digital>
    |\
    | * 321dd8fc - versa_ecp5: Remove negative diff IO pins <David Shah>
    |/
    * c03b1ad1 - platforms/versa_ecp5: add ddram pins <Florent Kermarrec>
    * ff155a47 - soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write <Florent Kermarrec>
    * d3ecdd99 - soc/cores/clock: add actual clk_freqs to config <Florent Kermarrec>

 * migen changed from 0.6.dev-241-gafe4405 to 0.6.dev-283-g562c046
    * 562c046 - Correct URL of logo Signed-off-by: Chipmuenk <[email protected]> <Chipmuenk>
    * db7ce84 - updated packaging infos <Chipmuenk>
    * a9e5029 - platforms: add de10lite support <msloniewski>
    * a69e1fd - altera/quartus: fix generated build script <msloniewski>
    * 1b804d7 - platforms: add max1000 support <msloniewski>
    * bc90344 - metlino: v1.0rc5 <Sebastien Bourdeauducq>
    * 9031bfe - metlino: add VHDCI EEM carrier connector <Sebastien Bourdeauducq>
    * 83b209e - metlino: add LEDs, I2C, Si5324, transceivers <Sebastien Bourdeauducq>
    * 4289590 - metlino: set bitstream properties <Sebastien Bourdeauducq>
    * aea0841 - metlino: add gth_clk200 and port0 <Sebastien Bourdeauducq>
    * 7299f4e - metlino: add spiflash <Sebastien Bourdeauducq>
    * 6815691 - metlino: use same SDRAM constraints as Sayma <Sebastien Bourdeauducq>
    * 42fe506 - metlino: update pins to 1.0rc4 <Sebastien Bourdeauducq>
    * 54d666d - Lattice iCE40: add comment on the polarity of differential I/O pairs <airwoodix>
    * 090ece7 - Lattice iCE40: pass positive pin to SB_IO in DifferentialInput <airwoodix>
    * ee3508b - Revert e43cd74 <airwoodix>
    * e43cd74 - Lattice iCE40: fix DifferentialInput polarity <airwoodix>
    * e6d02be - humpback: fix serial pinouts (crossover cables) <airwoodix>
    * c8cae39 - Lattice iCE40: implement DifferentialInput <Etienne Wodey>
    * a6f9cbd - Add Sinara Humpback platform (#177) <Étienne Wodey>
    * 4e66a71 - Fix `-vlgincdir` for xst. <Tim 'mithro' Ansell>
    * edcadbc - sayma_rtm2: si5324_clkout -> cdr_clk_clean <Sebastien Bourdeauducq>
    * 49b9d8a - sayma_amc2: add rtm_amc_link <Sebastien Bourdeauducq>
    * 0080bed - sayma_rtm2: add AFE test pins <Sebastien Bourdeauducq>
    * 032340d - sayma_rtm2: add rtm_amc_link <Sebastien Bourdeauducq>
    * 8bf0ab8 - sayma_rtm2: fix clk50 IOStandard <Sebastien Bourdeauducq>
    * 5dc0b23 - sayma_rtm: select correct speed grade and IDCODE for v2 <Sebastien Bourdeauducq>
    * 98a075c - sayma_rtm: update for v2.0rc4 <Sebastien Bourdeauducq>
    * cd71a2a - fix permissions <Sebastien Bourdeauducq>
    * 5a843a1 - sayma_amc: update gth_clk200, add DDMTD signals <Sebastien Bourdeauducq>
    * 2154882 - sayma_amc: OVERTEMPPOWERDOWN is called OVERTEMPSHUTDOWN on Ultrascale <Sebastien Bourdeauducq>
    * 3773947 - sayma_amc: si5324_clkout -> cdr_clk_clean <Sebastien Bourdeauducq>
    * 383512b - sayma_amc2: update to v2.0rc4 <Sebastien Bourdeauducq>
    * 936732f - add sayma_rtm2 <Sebastien Bourdeauducq>
    * d482b93 - sayma_amc2: add ddrXX_clk <Sebastien Bourdeauducq>
    * 25646d4 - sayma_amc2: enable OVERTEMPPOWERDOWN <Sebastien Bourdeauducq>
    * 9fd7a48 - remove Roach <Sebastien Bourdeauducq>
    * 9d90900 - sayma_amc: use LVDS for serwb <Sebastien Bourdeauducq>
    * 3da7113 - sayma_amc: fix aux_clk I/O standard <Sebastien Bourdeauducq>
    * 9a25f90 - sayma_amc: fix v2 platform name <Sebastien Bourdeauducq>
    * 7765238 - add Sayma AMC v2 platform <Sebastien Bourdeauducq>
    * ae42105 - migen: replace `collections` with `collections.abc` as necessary (#176) <Sean Cross>

Full submodule status
--
 15df4aebf06da579241c58949493b866139d0e2b edid-decode (remotes/origin/HEAD)
 1c21ee44a2b3936f62e4b43f2bcbf63ce9404691 flash_proxies (heads/master)
 67de3cee14b13beabc90804e3b62c66e028fd951 litedram (heads/master)
 2424e62bf9637c2623b627a56aca7a3f90349e92 liteeth (heads/master)
 de6cd01d3f158387337bf4f47fd5a351ec2c3267 litepcie (heads/master)
 6fe4cceaab77d6a117fa539f461b3ae9ca7e668e litesata (heads/master)
 2474ce9db23e4d06bff4bbeacf0051efa3042f37 litescope (heads/master)
 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (heads/master)
 98e145fba8c25394e9958bad67e2a457d145127e litevideo (heads/master)
 113f7f408e7c95150011c55ca473f45befb7f9bb litex (remotes/origin/HEAD)
 562c0466443f859d6cf0c87a0bb50db094d27cf4 migen (0.6.dev-283-g562c046)
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