From 8eb22354fa4495d5698a731b1013954a05c5878b Mon Sep 17 00:00:00 2001 From: Suikan <26223147+suikan4github@users.noreply.github.com> Date: Sun, 2 Jul 2023 21:46:28 +0900 Subject: [PATCH] Simplified cache control algorithm. The SCB Cache controll functions has follwoing two functionality : 1. Round the start address to 32byte align ( by hardware register ). 2. Repeat untill all required area were processed. Thus, we don't need to do it in Murasaki. Followings are affected. CleanDataCacheByAddress() CleanAndInvalidateDataCacheByAddress() --- core/murasaki_defs.hpp | 32 ++++---------------------------- 1 file changed, 4 insertions(+), 28 deletions(-) diff --git a/core/murasaki_defs.hpp b/core/murasaki_defs.hpp index 4ba9862..1c1368d 100644 --- a/core/murasaki_defs.hpp +++ b/core/murasaki_defs.hpp @@ -341,24 +341,12 @@ static inline bool IsInsideInterrupt() */ static inline void CleanAndInvalidateDataCacheByAddress(void *address, size_t size) { -#ifdef __CORE_CM7_H_GENERIC +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) // Is data cache enabled? then, invalidate it if (( SCB->CCR & SCB_CCR_DC_Msk ) != 0 ) { - unsigned int aligned_address = reinterpret_cast(address); - - // extract modulo 32. The address have to be aligned to 32byte. - unsigned int adjustment = aligned_address & 0x1F; - // Adjust the address and size. - aligned_address -= adjustment; // aligne to 32byte boarder - size += adjustment; // Because the start address is lower, the size is bigger. - - ::SCB_CleanInvalidateDCache_by_Addr(reinterpret_cast(aligned_address), size); + ::SCB_CleanInvalidateDCache_by_Addr(reinterpret_cast(address), size); } -#elif defined ( __CORE_CM0_H_GENERIC ) ||defined ( __CORE_CM0PLUS_H_GENERIC ) ||defined ( __CORE_CM3_H_GENERIC ) ||defined ( __CORE_CM4_H_GENERIC ) ||defined ( __CORE_CM1_H_GENERIC ) ||defined ( __CORE_CM33_H_GENERIC ) -// Do nothing. These core doesn't have d-cache. -#else -#error "Unknown core" #endif } @@ -376,24 +364,12 @@ static inline void CleanAndInvalidateDataCacheByAddress(void *address, size_t si */ static inline void CleanDataCacheByAddress(void *address, size_t size) { -#ifdef __CORE_CM7_H_GENERIC +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) // Is data cache enabled? then, clean the data cache if (( SCB->CCR & SCB_CCR_DC_Msk ) != 0 ) { - unsigned int aligned_address = reinterpret_cast(address); - - // extract modulo 32. The address have to be aligned to 32byte. - unsigned int adjustment = aligned_address & 0x1F; - // Adjust the address and size. - aligned_address -= adjustment; // aligne to 32byte boarder - size += adjustment; // Because the start address is lower, the size is bigger. - - ::SCB_CleanDCache_by_Addr(reinterpret_cast(aligned_address), size); + ::SCB_CleanDCache_by_Addr(reinterpret_cast(address), size); } -#elif defined ( __CORE_CM0_H_GENERIC ) ||defined ( __CORE_CM0PLUS_H_GENERIC ) ||defined ( __CORE_CM3_H_GENERIC ) ||defined ( __CORE_CM4_H_GENERIC ) ||defined ( __CORE_CM1_H_GENERIC ) ||defined ( __CORE_CM33_H_GENERIC ) -// Do nothing. These core doesn't have d-cache. -#else -#error "Unknown core" #endif }