Verilog implementation

[pluseqs]

Hello. Thank you very much for your work. Your processor suited me best.

But my development environment does not support vhdl and therefore I have to translate it into verilog using your neorv32-verilog project.

Until version 1.10.5 I had no problems with compiling the resulting .v file. And already since 1.10.6 the resulting .v file causes an error in my environment. And unfortunately the environment does not say what exactly is wrong.

When converting the project to a .v file, a warning was noticed "no assignment for offset 2 of signal "auth" in the neorv32_debug_dm.vhd file (line 137).

In this structure, I commented out the "reset : std_ulogic; -- reset authentication (sync, high-active)" line, since it is probably not used. The warning disappeared and the .v file began to compile successfully.

The question is, is it correct to do this? Thank you!!!

[stnolting]

Hey @pluseqs!

When converting the project to a .v file, a warning was noticed "no assignment for offset 2 of signal "auth" in the neorv32_debug_dm.vhd file (line 137).

That is this line, right?

neorv32/rtl/core/neorv32_debug_dm.vhd

Line 133 in 1bf8c82

reset : std_ulogic; -- reset authentication (sync, high-active)

Hmm, I have no idea why this signal is there - it is not used at all... 🤔 Maybe it is just an artifact... However, we should remove that. Thanks for finding this!

The question is, is it correct to do this? Thank you!!!

Completely fine.

Btw, maybe we should enable more modules in https://github.com/stnolting/neorv32-verilog/blob/main/src/neorv32_verilog_wrapper.vhd to check for issues like this.

[stnolting]

Fixed in 894d5b8

[pluseqs]

Fixed in 894d5b8

Thanks a lot!

Btw, maybe we should enable more modules in https://github.com/stnolting/neorv32-verilog/blob/main/src/neorv32_verilog_wrapper.vhd to check for issues like this.

There is also a warning "(host_req_i.addr(31 downto 28) >= UC_BEGIN) comparing non-numeric vector is unexpected" in neorv32_cache.vhd file (line 179).

To get rid of this warning the line was changed to this "((unsigned(host_req_i.addr(31 downto 28)) >= unsigned(UC_BEGIN))" - unsigned conversion was added. And "use ieee.numeric_std.all;" library was added.

But I don't know how correct and necessary this is, since before the changes in the verilog file there was already this conversion "assign n1327_o = $unsigned(n1325_o) >= $unsigned(4'b1111);". And the files are identical.

I will try to test more modules in the future. At the moment my configuration looks like this:

neorv32_top_inst: neorv32_top
generic map (
	-- General --
	CLOCK_FREQUENCY              => CLOCK_FREQUENCY,   -- clock frequency of clk_i in Hz
	BOOT_MODE_SELECT             => 0,                 -- boot via internal bootloader
	HART_ID                      => hart_id_c,         -- hardware thread ID
	JEDEC_ID                     => jedec_id_c,        -- vendor's JEDEC ID
	-- On-Chip Debugger (OCD) --
	OCD_EN                       => true,              -- implement on-chip debugger
	-- RISC-V CPU Extensions --
	RISCV_ISA_C        			 => true,              -- implement compressed extension?
	RISCV_ISA_M        			 => true,              -- implement mul/div extension?
	RISCV_ISA_U        			 => true,              -- implement user mode extension?    
	RISCV_ISA_Zicntr   			 => true,              -- implement base counters?
        RISCV_ISA_Zfinx          => true,              -- implement 32-bit floating-point extension		
	-- Extension Options --
	FAST_MUL_EN                  => true,  		   	   -- use DSPs for M extension's multiplier
	FAST_SHIFT_EN                => true,  		   	   -- use barrel shifter for shift operations    
	-- Internal Instruction memory --
	MEM_INT_IMEM_EN              => true,              -- implement processor-internal instruction memory
	MEM_INT_IMEM_SIZE            => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
	-- Internal Data memory --
	MEM_INT_DMEM_EN              => true,              -- implement processor-internal data memory
	MEM_INT_DMEM_SIZE            => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes
	-- Internal Cache memory (iCACHE) --
	ICACHE_EN                    => true,  		   	   -- implement instruction cache
	ICACHE_NUM_BLOCKS            => 4,      		   -- i-cache: number of blocks (min 1), has to be a power of 2
	ICACHE_BLOCK_SIZE            => 64,     	       -- i-cache: block size in bytes (min 4), has to be a power of 2
	-- Internal Data Cache (dCACHE) --
	DCACHE_EN                    => true,  	  	   	   -- implement data cache
	DCACHE_NUM_BLOCKS            => 4,      		   -- d-cache: number of blocks (min 1), has to be a power of 2
	DCACHE_BLOCK_SIZE            => 64,     		   -- d-cache: block size in bytes (min 4), has to be a power of 2
	-- External bus interface (XBUS) --
	XBUS_EN               		 => true,              -- implement external memory bus interface?
	XBUS_TIMEOUT          		 => 1023,              -- cycles after a pending bus access auto-terminates (0 = disabled)
	XBUS_REGSTAGE_EN      		 => false,             -- add XBUS register stage
	XBUS_CACHE_EN         		 => true,    		   -- enable external bus cache (x-cache)
	XBUS_CACHE_NUM_BLOCKS 		 => 32,    			   -- x-cache: number of blocks (min 1), has to be a power of 2
	XBUS_CACHE_BLOCK_SIZE 		 => 32,    			   -- x-cache: block size in bytes (min 4), has to be a power of 2		
        -- External Interrupts Controller (XIRQ) --
        XIRQ_NUM_CH                => 31,            -- number of external IRQ channels (0..32)
	-- Processor peripherals --
	IO_GPIO_NUM                  => 8,                 -- number of GPIO input/output pairs (0..64)
	IO_MTIME_EN                  => true,              -- implement machine system timer (MTIME)?
	IO_GPTMR_EN                  => true,

	IO_SPI_EN                    => true,
	IO_SPI_FIFO                  => 1,	
        IO_TWI_EN                    => true,              -- implement two-wire interface (TWI)?			
	IO_UART0_EN                  => true               -- implement primary universal asynchronous receiver/transmitter (UART0)?
)

[stnolting]

Thanks for finding this! This is indeed a "bug". I've already created a PR for this (#1103).

I will try to test more modules in the future. At the moment my configuration looks like this:

Very good idea! I'll add that to the default wrapper in https://github.com/stnolting/neorv32-verilog as well.