diff --git a/Cargo.toml b/Cargo.toml
index 55fbfa75..27bd5272 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -29,7 +29,7 @@ members = [".", "testsuite", "codegen"]
 [dependencies]
 bxcan = { version = "0.7.0", optional = true }
 cfg-if = "1.0.0"
-cortex-m = "0.7.7"
+cortex-m = { version = "0.7.7", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7.3"
 critical-section = "1.1.2"
 defmt = { version = ">=0.2.3, <0.4.0", optional = true }
@@ -42,7 +42,7 @@ num-traits = { version = "0.2.17", default-features = false}
 paste = "1.0.14"
 rtcc = { version = "0.3.0", optional = true }
 stm32-usbd = { version = "0.6.0", optional = true }
-stm32f3 = { version = "0.15.1", default-features = false }
+stm32f3 = { version = "0.16.0", package = "stm32f3-staging", default-features = false }
 void = { version = "1.0.2", default-features = false }
 
 [dev-dependencies]
@@ -58,6 +58,7 @@ rtt-target = { version = "0.4.0" }
 systick-monotonic = "1.0"
 usb-device = "0.3.1"
 usbd-serial = "0.2.0"
+stm32f3 = { version = "0.16.0", package = "stm32f3-staging" }
 
 [build-dependencies]
 slice-group-by = "0.3.1"
diff --git a/examples/adc.rs b/examples/adc.rs
index 9c43d069..7b19553f 100644
--- a/examples/adc.rs
+++ b/examples/adc.rs
@@ -45,7 +45,7 @@ fn main() -> ! {
 
     // This is a workaround, so that the debugger will not disconnect imidiatly on asm::wfi();
     // https://github.com/probe-rs/probe-rs/issues/350#issuecomment-740550519
-    dp.DBGMCU.cr.modify(|_, w| {
+    dp.DBGMCU.cr().modify(|_, w| {
         w.dbg_sleep().set_bit();
         w.dbg_standby().set_bit();
         w.dbg_stop().set_bit()
diff --git a/examples/i2c_scanner.rs b/examples/i2c_scanner.rs
index ff9a1f45..375a5ce5 100644
--- a/examples/i2c_scanner.rs
+++ b/examples/i2c_scanner.rs
@@ -52,14 +52,14 @@ fn main() -> ! {
     for addr in 0x00_u8..0x80 {
         // Write the empty array and check the slave response.
         if VALID_ADDR_RANGE.contains(&addr) && i2c.write(addr, &[]).is_ok() {
-            hprint!("{:02x}", addr).unwrap();
+            hprint!("{:02x}", addr);
         } else {
-            hprint!("..").unwrap();
+            hprint!("..");
         }
         if addr % 0x10 == 0x0F {
-            hprintln!().unwrap();
+            hprintln!();
         } else {
-            hprint!(" ").unwrap();
+            hprint!(" ");
         }
     }
 
diff --git a/examples/serial_dma.rs b/examples/serial_dma.rs
index bf580dbc..d90b4aa8 100644
--- a/examples/serial_dma.rs
+++ b/examples/serial_dma.rs
@@ -20,12 +20,12 @@ fn main() -> ! {
     // This is a workaround, so that the debugger will not disconnect
     // imidiatly on asm::wfi();
     // https://github.com/probe-rs/probe-rs/issues/350#issuecomment-740550519
-    dp.DBGMCU.cr.modify(|_, w| {
+    dp.DBGMCU.cr().modify(|_, w| {
         w.dbg_sleep().set_bit();
         w.dbg_standby().set_bit();
         w.dbg_stop().set_bit()
     });
-    dp.RCC.ahbenr.modify(|_, w| w.dma1en().enabled());
+    dp.RCC.ahbenr().modify(|_, w| w.dma1en().enabled());
 
     let mut rcc = dp.RCC.constrain();
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
diff --git a/src/adc.rs b/src/adc.rs
index 13f6b0e1..67ef6af3 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -33,7 +33,7 @@ use crate::{
     Switch,
 };
 
-use crate::pac::{adc1_2, adc1_2::ccr::CKMODE_A};
+use crate::pac::{adc1_2, adc1_2::ccr::CKMODE};
 
 #[cfg(feature = "enumset")]
 use enumset::{EnumSet, EnumSetType};
@@ -273,7 +273,7 @@ macro_rules! sp_pins {
                     // (Adc<ADC1, Disabled>, Adc<ADC2, Disabled>)
                     _adcs: &mut <Common as CommonInstance>::Childs,
                 ) -> Self {
-                    common_adc.reg.ccr.modify(|_, w| w.$en().enabled());
+                    common_adc.reg.ccr().modify(|_, w| w.$en().enabled());
                     Self { _adc: PhantomData }
                 }
             }
@@ -342,14 +342,14 @@ where
     #[must_use]
     #[inline]
     pub fn data_register(&self) -> u16 {
-        self.reg.dr.read().rdata().bits()
+        self.reg.dr().read().rdata().bits()
     }
 
     /// Returns the address of the ADC data register. Primarily useful for configuring DMA.
     // TODO(Sh3Rm4n): Check against and integrate to DMA
     #[inline]
     pub fn data_register_address(&self) -> u32 {
-        core::ptr::addr_of!(self.reg.dr) as u32
+        self.reg.dr().as_ptr() as u32
     }
 
     /// Manually start a conversion sequence.
@@ -358,7 +358,7 @@ where
     /// * The conversion mode is configured via [`Adc::set_conversion_mode`].
     #[inline]
     pub fn start_conversion(&mut self) {
-        self.reg.cr.modify(|_, w| w.adstart().start_conversion());
+        self.reg.cr().modify(|_, w| w.adstart().start_conversion());
     }
 
     /// Configure and convert the [`Adc`] instance into [`OneShot`] mode.
@@ -391,26 +391,26 @@ where
         // 1. Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is ongoing. If
         //    required, stop any regular and injected conversion ongoing by setting ADSTP=1 and
         //    JADSTP=1 and then wait until ADSTP=0 and JADSTP=0
-        if self.reg.cr.read().aden().bit()
-            && (self.reg.cr.read().adstart().bit() || self.reg.cr.read().jadstart().bit())
+        if self.reg.cr().read().aden().bit()
+            && (self.reg.cr().read().adstart().bit() || self.reg.cr().read().jadstart().bit())
         {
-            self.reg.cr.modify(|_, w| w.adstp().stop_conversion());
+            self.reg.cr().modify(|_, w| w.adstp().stop_conversion());
             // In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both
             // regular and injected conversions (do not use JADSTP)
-            if !self.reg.cfgr.read().jauto().is_enabled() {
-                self.reg.cr.modify(|_, w| w.jadstp().stop_conversion());
+            if !self.reg.cfgr().read().jauto().is_enabled() {
+                self.reg.cr().modify(|_, w| w.jadstp().stop_conversion());
             }
-            while self.reg.cr.read().adstp().bit() || self.reg.cr.read().jadstp().bit() {}
+            while self.reg.cr().read().adstp().bit() || self.reg.cr().read().jadstp().bit() {}
         }
 
         // Software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0
         // and JADSTART=0 (which ensures that no conversion is ongoing)
-        if self.reg.cr.read().aden().is_enabled() {
+        if self.reg.cr().read().aden().is_enabled() {
             // 2. Disable ADC
             // TODO(Sh3Rm4n): Use w.aaddis().disable() once https://github.com/stm32-rs/stm32-rs/pull/699 is merged
-            self.reg.cr.modify(|_, w| w.addis().set_bit());
+            self.reg.cr().modify(|_, w| w.addis().set_bit());
             // 3. Wait for ADC being disabled
-            while self.reg.cr.read().aden().is_enabled() {}
+            while self.reg.cr().read().aden().is_enabled() {}
         }
 
         Adc {
@@ -461,12 +461,12 @@ where
         // ADRDY=1 was set.
         // This assumption is true, if the peripheral was initially enabled through
         // this method.
-        if !self.reg.cr.read().aden().is_enabled() {
+        if !self.reg.cr().read().aden().is_enabled() {
             // Set ADEN=1
-            self.reg.cr.modify(|_, w| w.aden().enabled());
+            self.reg.cr().modify(|_, w| w.aden().enabled());
             // Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be
             // done using the associated interrupt (setting ADRDYIE=1).
-            while self.reg.isr.read().adrdy().is_not_ready() {}
+            while self.reg.isr().read().adrdy().is_not_ready() {}
         }
 
         Adc {
@@ -497,10 +497,10 @@ where
         self.configure_voltage_regulator(Switch::On, clocks);
 
         self.reg
-            .cr
+            .cr()
             .modify(|_, w| w.adcaldif().single_ended().adcal().calibration());
 
-        while self.reg.cr.read().adcal().is_calibration() {}
+        while self.reg.cr().read().adcal().is_calibration() {}
 
         // ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle after the ADCAL bit is
         // cleared by hardware
@@ -518,13 +518,13 @@ where
 
     /// Enable the interal voltage generator Blocks until regulator is enabled.
     fn configure_voltage_regulator(&mut self, toggle: impl Into<Switch>, clocks: &Clocks) {
-        let already_on = self.reg.cr.read().advregen().is_enabled();
+        let already_on = self.reg.cr().read().advregen().is_enabled();
         let toggle = toggle.into();
-        self.reg.cr.modify(|_, w| w.advregen().intermediate());
-        self.reg.cr.modify(|_, w| {
+        self.reg.cr().modify(|_, w| w.advregen().intermediate());
+        self.reg.cr().modify(|_, w| {
             w.advregen().variant(match toggle {
-                Switch::On => adc1::cr::ADVREGEN_A::Enabled,
-                Switch::Off => adc1::cr::ADVREGEN_A::Disabled,
+                Switch::On => adc1::cr::ADVREGEN::Enabled,
+                Switch::Off => adc1::cr::ADVREGEN::Disabled,
             })
         });
         if toggle == Switch::On && !already_on {
@@ -549,19 +549,19 @@ where
     /// Get the current overrun mode.
     #[inline]
     pub fn overrun_mode(&self) -> config::OverrunMode {
-        self.reg.cfgr.read().ovrmod().variant().into()
+        self.reg.cfgr().read().ovrmod().variant().into()
     }
 
     /// Get the sampling resolution.
     #[inline]
     pub fn resolution(&self) -> config::Resolution {
-        self.reg.cfgr.read().res().variant().into()
+        self.reg.cfgr().read().res().variant().into()
     }
 
     /// Get the current configured data alignment.
     #[inline]
     pub fn data_alignment(&self) -> config::DataAlignment {
-        self.reg.cfgr.read().align().variant().into()
+        self.reg.cfgr().read().align().variant().into()
     }
 
     /// Get the current configured external trigger.
@@ -569,39 +569,39 @@ where
     /// If no (valid) trigger is set, return `None`
     #[inline]
     pub fn external_trigger(&self) -> Option<config::ExternalTrigger> {
-        use adc1::cfgr::{EXTEN_A, EXTSEL_A};
+        use adc1::cfgr::{EXTEN, EXTSEL};
         use config::ExternalTrigger;
-        let cfgr = self.reg.cfgr.read();
+        let cfgr = self.reg.cfgr().read();
 
         match (cfgr.exten().variant(), cfgr.extsel().variant()) {
-            (EXTEN_A::Disabled, _) | (_, None) => None,
+            (EXTEN::Disabled, _) | (_, None) => None,
             (edge, Some(ext)) => {
                 let edge = match edge {
-                    EXTEN_A::Disabled => {
+                    EXTEN::Disabled => {
                         // SAFETY: This arm can not be reached, because of the
-                        // (EXTEN_A::DISABLED, _) arm above.
+                        // (EXTEN::DISABLED, _) arm above.
                         unsafe { unreachable_unchecked() }
                     }
-                    EXTEN_A::RisingEdge => config::TriggerMode::RisingEdge,
-                    EXTEN_A::FallingEdge => config::TriggerMode::FallingEdge,
-                    EXTEN_A::BothEdges => config::TriggerMode::BothEdges,
+                    EXTEN::RisingEdge => config::TriggerMode::RisingEdge,
+                    EXTEN::FallingEdge => config::TriggerMode::FallingEdge,
+                    EXTEN::BothEdges => config::TriggerMode::BothEdges,
                 };
 
                 Some(match ext {
-                    EXTSEL_A::HrtimAdctrg1 => ExternalTrigger::HrtimAdcTrg1(edge),
-                    EXTSEL_A::HrtimAdctrg3 => ExternalTrigger::HrtimAdcTrg3(edge),
-                    EXTSEL_A::Tim1Cc1 => ExternalTrigger::Tim1Cc1(edge),
-                    EXTSEL_A::Tim1Cc2 => ExternalTrigger::Tim1Cc2(edge),
-                    EXTSEL_A::Tim1Cc3 => ExternalTrigger::Tim1Cc3(edge),
-                    EXTSEL_A::Tim2Cc2 => ExternalTrigger::Tim2Cc2(edge),
-                    EXTSEL_A::Tim3Trgo => ExternalTrigger::Tim3Trgo(edge),
-                    EXTSEL_A::Exti11 => ExternalTrigger::Exti11(edge),
-                    EXTSEL_A::Tim1Trgo => ExternalTrigger::Tim1Trgo(edge),
-                    EXTSEL_A::Tim1Trgo2 => ExternalTrigger::Tim1Trgo2(edge),
-                    EXTSEL_A::Tim2Trgo => ExternalTrigger::Tim2Trgo(edge),
-                    EXTSEL_A::Tim6Trgo => ExternalTrigger::Tim6Trgo(edge),
-                    EXTSEL_A::Tim15Trgo => ExternalTrigger::Tim15Trgo(edge),
-                    EXTSEL_A::Tim3Cc4 => ExternalTrigger::Tim3Cc4(edge),
+                    EXTSEL::HrtimAdctrg1 => ExternalTrigger::HrtimAdcTrg1(edge),
+                    EXTSEL::HrtimAdctrg3 => ExternalTrigger::HrtimAdcTrg3(edge),
+                    EXTSEL::Tim1Cc1 => ExternalTrigger::Tim1Cc1(edge),
+                    EXTSEL::Tim1Cc2 => ExternalTrigger::Tim1Cc2(edge),
+                    EXTSEL::Tim1Cc3 => ExternalTrigger::Tim1Cc3(edge),
+                    EXTSEL::Tim2Cc2 => ExternalTrigger::Tim2Cc2(edge),
+                    EXTSEL::Tim3Trgo => ExternalTrigger::Tim3Trgo(edge),
+                    EXTSEL::Exti11 => ExternalTrigger::Exti11(edge),
+                    EXTSEL::Tim1Trgo => ExternalTrigger::Tim1Trgo(edge),
+                    EXTSEL::Tim1Trgo2 => ExternalTrigger::Tim1Trgo2(edge),
+                    EXTSEL::Tim2Trgo => ExternalTrigger::Tim2Trgo(edge),
+                    EXTSEL::Tim6Trgo => ExternalTrigger::Tim6Trgo(edge),
+                    EXTSEL::Tim15Trgo => ExternalTrigger::Tim15Trgo(edge),
+                    EXTSEL::Tim3Cc4 => ExternalTrigger::Tim3Cc4(edge),
                 })
             }
         }
@@ -610,33 +610,33 @@ where
     /// Return the conversion mode the peripheral is currently operating in.
     #[inline]
     pub fn conversion_mode(&self) -> config::ConversionMode {
-        use adc1::cfgr::{CONT_A, DISCEN_A};
-        let cfgr = self.reg.cfgr.read();
+        use adc1::cfgr::{CONT, DISCEN};
+        let cfgr = self.reg.cfgr().read();
 
         match (
             cfgr.cont().variant(),
             cfgr.discen().variant(),
             cfgr.discnum().bits(),
         ) {
-            (CONT_A::Single, DISCEN_A::Disabled, _) => config::ConversionMode::Single,
-            (CONT_A::Continuous, DISCEN_A::Disabled, _) => config::ConversionMode::Continuous,
+            (CONT::Single, DISCEN::Disabled, _) => config::ConversionMode::Single,
+            (CONT::Continuous, DISCEN::Disabled, _) => config::ConversionMode::Continuous,
             // It is not possible to have both discontinuous mode and continuous mode enabled. In this
             // case (if DISCEN=1, CONT=1), the ADC behaves as if continuous mode was disabled.
             // [RM0316 15.3.20]
-            (_, DISCEN_A::Enabled, n) => config::ConversionMode::Discontinuous(n),
+            (_, DISCEN::Enabled, n) => config::ConversionMode::Discontinuous(n),
         }
     }
 
     /// Get the current configured DMA mode.
     #[inline]
     pub fn dma_mode(&self) -> config::DmaMode {
-        use adc1::cfgr::{DMACFG_A, DMAEN_A};
+        use adc1::cfgr::{DMACFG, DMAEN};
 
-        let cfgr = self.reg.cfgr.read();
+        let cfgr = self.reg.cfgr().read();
         match (cfgr.dmaen().variant(), cfgr.dmacfg().variant()) {
-            (DMAEN_A::Disabled, _) => config::DmaMode::Disabled,
-            (DMAEN_A::Enabled, DMACFG_A::OneShot) => config::DmaMode::OneShot,
-            (DMAEN_A::Enabled, DMACFG_A::Circular) => config::DmaMode::Circular,
+            (DMAEN::Disabled, _) => config::DmaMode::Disabled,
+            (DMAEN::Enabled, DMACFG::OneShot) => config::DmaMode::OneShot,
+            (DMAEN::Enabled, DMACFG::Circular) => config::DmaMode::Circular,
         }
     }
 
@@ -671,7 +671,7 @@ where
     /// * Alternativly a conversino stop is signaled via the [`Event::EndOfConversion`] event.
     #[inline]
     pub fn is_conversion_ongoing(&self) -> bool {
-        self.reg.cr.read().adstart().is_active()
+        self.reg.cr().read().adstart().is_active()
     }
 
     /// Get the [`channel::Id`] at a specific [`config::Sequence`] position.
@@ -690,22 +690,22 @@ where
     pub fn channel_sequence(&self, sequence: config::Sequence) ->  Option<channel::Id> {
         // Set the channel in the right sequence field
         match sequence {
-            config::Sequence::One      => self.reg.sqr1.read().sq1().bits().try_into().ok(),
-            config::Sequence::Two      => self.reg.sqr1.read().sq2().bits().try_into().ok(),
-            config::Sequence::Three    => self.reg.sqr1.read().sq3().bits().try_into().ok(),
-            config::Sequence::Four     => self.reg.sqr1.read().sq4().bits().try_into().ok(),
-            config::Sequence::Five     => self.reg.sqr2.read().sq5().bits().try_into().ok(),
-            config::Sequence::Six      => self.reg.sqr2.read().sq6().bits().try_into().ok(),
-            config::Sequence::Seven    => self.reg.sqr2.read().sq7().bits().try_into().ok(),
-            config::Sequence::Eight    => self.reg.sqr2.read().sq8().bits().try_into().ok(),
-            config::Sequence::Nine     => self.reg.sqr2.read().sq9().bits().try_into().ok(),
-            config::Sequence::Ten      => self.reg.sqr3.read().sq10().bits().try_into().ok(),
-            config::Sequence::Eleven   => self.reg.sqr3.read().sq11().bits().try_into().ok(),
-            config::Sequence::Twelve   => self.reg.sqr3.read().sq12().bits().try_into().ok(),
-            config::Sequence::Thirteen => self.reg.sqr3.read().sq13().bits().try_into().ok(),
-            config::Sequence::Fourteen => self.reg.sqr3.read().sq14().bits().try_into().ok(),
-            config::Sequence::Fifteen  => self.reg.sqr4.read().sq15().bits().try_into().ok(),
-            config::Sequence::Sixteen  => self.reg.sqr4.read().sq16().bits().try_into().ok(),
+            config::Sequence::One      => self.reg.sqr1().read().sq1().bits().try_into().ok(),
+            config::Sequence::Two      => self.reg.sqr1().read().sq2().bits().try_into().ok(),
+            config::Sequence::Three    => self.reg.sqr1().read().sq3().bits().try_into().ok(),
+            config::Sequence::Four     => self.reg.sqr1().read().sq4().bits().try_into().ok(),
+            config::Sequence::Five     => self.reg.sqr2().read().sq5().bits().try_into().ok(),
+            config::Sequence::Six      => self.reg.sqr2().read().sq6().bits().try_into().ok(),
+            config::Sequence::Seven    => self.reg.sqr2().read().sq7().bits().try_into().ok(),
+            config::Sequence::Eight    => self.reg.sqr2().read().sq8().bits().try_into().ok(),
+            config::Sequence::Nine     => self.reg.sqr2().read().sq9().bits().try_into().ok(),
+            config::Sequence::Ten      => self.reg.sqr3().read().sq10().bits().try_into().ok(),
+            config::Sequence::Eleven   => self.reg.sqr3().read().sq11().bits().try_into().ok(),
+            config::Sequence::Twelve   => self.reg.sqr3().read().sq12().bits().try_into().ok(),
+            config::Sequence::Thirteen => self.reg.sqr3().read().sq13().bits().try_into().ok(),
+            config::Sequence::Fourteen => self.reg.sqr3().read().sq14().bits().try_into().ok(),
+            config::Sequence::Fifteen  => self.reg.sqr4().read().sq15().bits().try_into().ok(),
+            config::Sequence::Sixteen  => self.reg.sqr4().read().sq16().bits().try_into().ok(),
         }
     }
 
@@ -719,25 +719,25 @@ where
         // Set the sample time for the channel
         match channel {
             #[cfg(feature = "gpio-f373")]
-            channel::Id::Zero => self.adc.smpr1.read().smp0().variant().into(),
-            channel::Id::One => self.reg.smpr1.read().smp1().variant().into(),
-            channel::Id::Two => self.reg.smpr1.read().smp2().variant().into(),
-            channel::Id::Three => self.reg.smpr1.read().smp3().variant().into(),
-            channel::Id::Four => self.reg.smpr1.read().smp4().variant().into(),
-            channel::Id::Five => self.reg.smpr1.read().smp5().variant().into(),
-            channel::Id::Six => self.reg.smpr1.read().smp6().variant().into(),
-            channel::Id::Seven => self.reg.smpr1.read().smp7().variant().into(),
-            channel::Id::Eight => self.reg.smpr1.read().smp8().variant().into(),
-            channel::Id::Nine => self.reg.smpr1.read().smp9().variant().into(),
-            channel::Id::Ten => self.reg.smpr2.read().smp10().variant().into(),
-            channel::Id::Eleven => self.reg.smpr2.read().smp11().variant().into(),
-            channel::Id::Twelve => self.reg.smpr2.read().smp12().variant().into(),
-            channel::Id::Thirteen => self.reg.smpr2.read().smp13().variant().into(),
-            channel::Id::Fourteen => self.reg.smpr2.read().smp14().variant().into(),
-            channel::Id::Fifteen => self.reg.smpr2.read().smp15().variant().into(),
-            channel::Id::Sixteen => self.reg.smpr2.read().smp16().variant().into(),
-            channel::Id::Seventeen => self.reg.smpr2.read().smp17().variant().into(),
-            channel::Id::Eighteen => self.reg.smpr2.read().smp18().variant().into(),
+            channel::Id::Zero => self.adc.smpr1().read().smp0().variant().into(),
+            channel::Id::One => self.reg.smpr1().read().smp1().variant().into(),
+            channel::Id::Two => self.reg.smpr1().read().smp2().variant().into(),
+            channel::Id::Three => self.reg.smpr1().read().smp3().variant().into(),
+            channel::Id::Four => self.reg.smpr1().read().smp4().variant().into(),
+            channel::Id::Five => self.reg.smpr1().read().smp5().variant().into(),
+            channel::Id::Six => self.reg.smpr1().read().smp6().variant().into(),
+            channel::Id::Seven => self.reg.smpr1().read().smp7().variant().into(),
+            channel::Id::Eight => self.reg.smpr1().read().smp8().variant().into(),
+            channel::Id::Nine => self.reg.smpr1().read().smp9().variant().into(),
+            channel::Id::Ten => self.reg.smpr2().read().smp10().variant().into(),
+            channel::Id::Eleven => self.reg.smpr2().read().smp11().variant().into(),
+            channel::Id::Twelve => self.reg.smpr2().read().smp12().variant().into(),
+            channel::Id::Thirteen => self.reg.smpr2().read().smp13().variant().into(),
+            channel::Id::Fourteen => self.reg.smpr2().read().smp14().variant().into(),
+            channel::Id::Fifteen => self.reg.smpr2().read().smp15().variant().into(),
+            channel::Id::Sixteen => self.reg.smpr2().read().smp16().variant().into(),
+            channel::Id::Seventeen => self.reg.smpr2().read().smp17().variant().into(),
+            channel::Id::Eighteen => self.reg.smpr2().read().smp18().variant().into(),
             // #[cfg(not(feature = "gpio-f373"))]
             // // SAFETY: We know, that channel IDs will not exceed 18, see [`crate::adc::channel`]
             // _ => unsafe { unreachable_unchecked() },
@@ -747,7 +747,7 @@ where
     /// Returns the total number of conversions in a regular channel sequence.
     #[inline]
     pub fn sequence_length(&self) -> config::Sequence {
-        match self.reg.sqr1.read().l().bits().try_into() {
+        match self.reg.sqr1().read().l().bits().try_into() {
             Ok(seq) => seq,
             // SAFETY: We are directly reading from the register, which can't give
             // use back invalid values, so this should never be called.
@@ -765,17 +765,17 @@ where
     #[inline]
     pub fn is_interrupt_configured(&self, event: Event) -> bool {
         match event {
-            Event::AdcReady => self.reg.ier.read().adrdyie().is_enabled(),
-            Event::EndOfSamplingPhase => self.reg.ier.read().eosmpie().is_enabled(),
-            Event::EndOfConversion => self.reg.ier.read().eocie().is_enabled(),
-            Event::EndOfSequence => self.reg.ier.read().eosie().is_enabled(),
-            Event::Overrun => self.reg.ier.read().ovrie().is_enabled(),
-            Event::InjectedChannelEndOfConversion => self.reg.ier.read().jeocie().is_enabled(),
-            Event::InjectedChannelEndOfSequence => self.reg.ier.read().jeosie().is_enabled(),
-            Event::AnalogWatchdog1 => self.reg.ier.read().awd1ie().is_enabled(),
-            Event::AnalogWatchdog2 => self.reg.ier.read().awd2ie().is_enabled(),
-            Event::AnalogWatchdog3 => self.reg.ier.read().awd3ie().is_enabled(),
-            Event::InjectedContextQueueOverfow => self.reg.ier.read().jqovfie().is_enabled(),
+            Event::AdcReady => self.reg.ier().read().adrdyie().is_enabled(),
+            Event::EndOfSamplingPhase => self.reg.ier().read().eosmpie().is_enabled(),
+            Event::EndOfConversion => self.reg.ier().read().eocie().is_enabled(),
+            Event::EndOfSequence => self.reg.ier().read().eosie().is_enabled(),
+            Event::Overrun => self.reg.ier().read().ovrie().is_enabled(),
+            Event::InjectedChannelEndOfConversion => self.reg.ier().read().jeocie().is_enabled(),
+            Event::InjectedChannelEndOfSequence => self.reg.ier().read().jeosie().is_enabled(),
+            Event::AnalogWatchdog1 => self.reg.ier().read().awd1ie().is_enabled(),
+            Event::AnalogWatchdog2 => self.reg.ier().read().awd2ie().is_enabled(),
+            Event::AnalogWatchdog3 => self.reg.ier().read().awd3ie().is_enabled(),
+            Event::InjectedContextQueueOverfow => self.reg.ier().read().jqovfie().is_enabled(),
         }
     }
 
@@ -798,7 +798,7 @@ where
     /// Check if an interrupt event happend.
     #[inline]
     pub fn is_event_triggered(&self, event: Event) -> bool {
-        let isr = self.reg.isr.read();
+        let isr = self.reg.isr().read();
         match event {
             Event::AdcReady => isr.adrdy().is_ready(),
             Event::EndOfSamplingPhase => isr.eosmp().is_ended(),
@@ -874,21 +874,25 @@ where
     /// Set the overrun mode
     #[inline]
     pub fn set_overrun_mode(&mut self, mode: config::OverrunMode) {
-        self.reg.cfgr.modify(|_, w| w.ovrmod().variant(mode.into()));
+        self.reg
+            .cfgr()
+            .modify(|_, w| w.ovrmod().variant(mode.into()));
     }
 
     /// Sets the sampling resolution.
     #[inline]
     pub fn set_resolution(&mut self, resolution: config::Resolution) {
         self.reg
-            .cfgr
+            .cfgr()
             .modify(|_, w| w.res().variant(resolution.into()));
     }
 
     /// Sets the data register alignment
     #[inline]
     pub fn set_data_alignment(&mut self, align: config::DataAlignment) {
-        self.reg.cfgr.modify(|_, w| w.align().variant(align.into()));
+        self.reg
+            .cfgr()
+            .modify(|_, w| w.align().variant(align.into()));
     }
 
     // TODO(Sh3Rm4n): setting offset might be useful, see RM0316 15.3.26
@@ -904,7 +908,7 @@ where
         // Only allowed to write when no conversion is ongoing
         self.stop_conversion();
 
-        self.reg.cfgr.modify(|_, w| {
+        self.reg.cfgr().modify(|_, w| {
             if let Some(ext) = trigger {
                 w.extsel().variant(ext.into()).exten().variant(ext.into())
             } else {
@@ -925,7 +929,7 @@ where
     #[inline]
     pub fn set_conversion_mode(&mut self, conversion_mode: config::ConversionMode) {
         // TODO: If we don't support 0, to what mode should the periperhal be set?
-        self.reg.cfgr.modify(|_, w| {
+        self.reg.cfgr().modify(|_, w| {
             w.discen()
                 .variant(conversion_mode.into())
                 .cont()
@@ -934,8 +938,8 @@ where
 
         if let config::ConversionMode::Discontinuous(n) = conversion_mode {
             self.reg
-                .cfgr
-                .modify(|_, w| w.discnum().bits(if n < 0b111 { n } else { 0b111 }));
+                .cfgr()
+                .modify(|_, w| w.discnum().set(if n < 0b111 { n } else { 0b111 }));
         }
     }
 
@@ -943,15 +947,15 @@ where
     // TODO: Check against DMA, so that it is working
     #[inline]
     pub fn set_dma_mode(&mut self, dma: config::DmaMode) {
-        use adc1::cfgr::{DMACFG_A, DMAEN_A};
+        use adc1::cfgr::{DMACFG, DMAEN};
         let (en, mode) = match dma {
-            config::DmaMode::Disabled => (DMAEN_A::Disabled, DMACFG_A::OneShot),
-            config::DmaMode::OneShot => (DMAEN_A::Enabled, DMACFG_A::OneShot),
-            config::DmaMode::Circular => (DMAEN_A::Enabled, DMACFG_A::Circular),
+            config::DmaMode::Disabled => (DMAEN::Disabled, DMACFG::OneShot),
+            config::DmaMode::OneShot => (DMAEN::Enabled, DMACFG::OneShot),
+            config::DmaMode::Circular => (DMAEN::Enabled, DMACFG::Circular),
         };
 
         self.reg
-            .cfgr
+            .cfgr()
             .modify(|_, w| w.dmaen().variant(en).dmacfg().variant(mode));
     }
 
@@ -976,10 +980,10 @@ where
     pub fn stop_conversion(&mut self) {
         // If no conversion is ongoing, this may lead to the stop bit never beeing reset?
         if self.is_conversion_ongoing() {
-            self.reg.cr.modify(|_, w| w.adstp().stop_conversion());
+            self.reg.cr().modify(|_, w| w.adstp().stop_conversion());
         }
 
-        while self.reg.cr.read().adstp().bit_is_set() {}
+        while self.reg.cr().read().adstp().bit_is_set() {}
     }
 
     /// Wraps [`Adc::set_channel_sequence_position`] to be able to take a pin.
@@ -1028,23 +1032,23 @@ where
         // SAFETY: the channel.into() implementation ensures that those are valid values
         unsafe {
             match sequence {
-                config::Sequence::One      => self.reg.sqr1.modify(|_, w| w.sq1().bits(channel.into())),
-                config::Sequence::Two      => self.reg.sqr1.modify(|_, w| w.sq2().bits(channel.into())),
-                config::Sequence::Three    => self.reg.sqr1.modify(|_, w| w.sq3().bits(channel.into())),
-                config::Sequence::Four     => self.reg.sqr1.modify(|_, w| w.sq4().bits(channel.into())),
-                config::Sequence::Five     => self.reg.sqr2.modify(|_, w| w.sq5().bits(channel.into())),
-                config::Sequence::Six      => self.reg.sqr2.modify(|_, w| w.sq6().bits(channel.into())),
-                config::Sequence::Seven    => self.reg.sqr2.modify(|_, w| w.sq7().bits(channel.into())),
-                config::Sequence::Eight    => self.reg.sqr2.modify(|_, w| w.sq8().bits(channel.into())),
-                config::Sequence::Nine     => self.reg.sqr2.modify(|_, w| w.sq9().bits(channel.into())),
-                config::Sequence::Ten      => self.reg.sqr3.modify(|_, w| w.sq10().bits(channel.into())),
-                config::Sequence::Eleven   => self.reg.sqr3.modify(|_, w| w.sq11().bits(channel.into())),
-                config::Sequence::Twelve   => self.reg.sqr3.modify(|_, w| w.sq12().bits(channel.into())),
-                config::Sequence::Thirteen => self.reg.sqr3.modify(|_, w| w.sq13().bits(channel.into())),
-                config::Sequence::Fourteen => self.reg.sqr3.modify(|_, w| w.sq14().bits(channel.into())),
-                config::Sequence::Fifteen  => self.reg.sqr4.modify(|_, w| w.sq15().bits(channel.into())),
-                config::Sequence::Sixteen  => self.reg.sqr4.modify(|_, w| w.sq16().bits(channel.into())),
-            }
+                config::Sequence::One      => self.reg.sqr1().modify(|_, w| w.sq1().bits(channel.into())),
+                config::Sequence::Two      => self.reg.sqr1().modify(|_, w| w.sq2().bits(channel.into())),
+                config::Sequence::Three    => self.reg.sqr1().modify(|_, w| w.sq3().bits(channel.into())),
+                config::Sequence::Four     => self.reg.sqr1().modify(|_, w| w.sq4().bits(channel.into())),
+                config::Sequence::Five     => self.reg.sqr2().modify(|_, w| w.sq5().bits(channel.into())),
+                config::Sequence::Six      => self.reg.sqr2().modify(|_, w| w.sq6().bits(channel.into())),
+                config::Sequence::Seven    => self.reg.sqr2().modify(|_, w| w.sq7().bits(channel.into())),
+                config::Sequence::Eight    => self.reg.sqr2().modify(|_, w| w.sq8().bits(channel.into())),
+                config::Sequence::Nine     => self.reg.sqr2().modify(|_, w| w.sq9().bits(channel.into())),
+                config::Sequence::Ten      => self.reg.sqr3().modify(|_, w| w.sq10().bits(channel.into())),
+                config::Sequence::Eleven   => self.reg.sqr3().modify(|_, w| w.sq11().bits(channel.into())),
+                config::Sequence::Twelve   => self.reg.sqr3().modify(|_, w| w.sq12().bits(channel.into())),
+                config::Sequence::Thirteen => self.reg.sqr3().modify(|_, w| w.sq13().bits(channel.into())),
+                config::Sequence::Fourteen => self.reg.sqr3().modify(|_, w| w.sq14().bits(channel.into())),
+                config::Sequence::Fifteen  => self.reg.sqr4().modify(|_, w| w.sq15().bits(channel.into())),
+                config::Sequence::Sixteen  => self.reg.sqr4().modify(|_, w| w.sq16().bits(channel.into())),
+            };
         }
     }
 
@@ -1065,28 +1069,28 @@ where
         // Set the sample time for the channel
         match channel {
             #[cfg(feature = "gpio-f373")]
-            channel::Id::Zero     => self.adc.smpr1.modify(|_, w| w.smp0().variant(sample_time.into())),
-            channel::Id::One      => self.reg.smpr1.modify(|_, w| w.smp1().variant(sample_time.into())),
-            channel::Id::Two      => self.reg.smpr1.modify(|_, w| w.smp2().variant(sample_time.into())),
-            channel::Id::Three    => self.reg.smpr1.modify(|_, w| w.smp3().variant(sample_time.into())),
-            channel::Id::Four     => self.reg.smpr1.modify(|_, w| w.smp4().variant(sample_time.into())),
-            channel::Id::Five     => self.reg.smpr1.modify(|_, w| w.smp5().variant(sample_time.into())),
-            channel::Id::Six      => self.reg.smpr1.modify(|_, w| w.smp6().variant(sample_time.into())),
-            channel::Id::Seven    => self.reg.smpr1.modify(|_, w| w.smp7().variant(sample_time.into())),
-            channel::Id::Eight    => self.reg.smpr1.modify(|_, w| w.smp8().variant(sample_time.into())),
-            channel::Id::Nine     => self.reg.smpr1.modify(|_, w| w.smp9().variant(sample_time.into())),
-            channel::Id::Ten      => self.reg.smpr2.modify(|_, w| w.smp10().variant(sample_time.into())),
-            channel::Id::Eleven   => self.reg.smpr2.modify(|_, w| w.smp11().variant(sample_time.into())),
-            channel::Id::Twelve   => self.reg.smpr2.modify(|_, w| w.smp12().variant(sample_time.into())),
-            channel::Id::Thirteen => self.reg.smpr2.modify(|_, w| w.smp13().variant(sample_time.into())),
-            channel::Id::Fourteen => self.reg.smpr2.modify(|_, w| w.smp14().variant(sample_time.into())),
-            channel::Id::Fifteen  => self.reg.smpr2.modify(|_, w| w.smp15().variant(sample_time.into())),
-            channel::Id::Sixteen  => self.reg.smpr2.modify(|_, w| w.smp16().variant(sample_time.into())),
-            channel::Id::Seventeen => self.reg.smpr2.modify(|_, w| w.smp17().variant(sample_time.into())),
-            channel::Id::Eighteen => self.reg.smpr2.modify(|_, w| w.smp18().variant(sample_time.into())),
+            channel::Id::Zero     => self.adc.smpr1().modify(|_, w| w.smp0().variant(sample_time.into())),
+            channel::Id::One      => self.reg.smpr1().modify(|_, w| w.smp1().variant(sample_time.into())),
+            channel::Id::Two      => self.reg.smpr1().modify(|_, w| w.smp2().variant(sample_time.into())),
+            channel::Id::Three    => self.reg.smpr1().modify(|_, w| w.smp3().variant(sample_time.into())),
+            channel::Id::Four     => self.reg.smpr1().modify(|_, w| w.smp4().variant(sample_time.into())),
+            channel::Id::Five     => self.reg.smpr1().modify(|_, w| w.smp5().variant(sample_time.into())),
+            channel::Id::Six      => self.reg.smpr1().modify(|_, w| w.smp6().variant(sample_time.into())),
+            channel::Id::Seven    => self.reg.smpr1().modify(|_, w| w.smp7().variant(sample_time.into())),
+            channel::Id::Eight    => self.reg.smpr1().modify(|_, w| w.smp8().variant(sample_time.into())),
+            channel::Id::Nine     => self.reg.smpr1().modify(|_, w| w.smp9().variant(sample_time.into())),
+            channel::Id::Ten      => self.reg.smpr2().modify(|_, w| w.smp10().variant(sample_time.into())),
+            channel::Id::Eleven   => self.reg.smpr2().modify(|_, w| w.smp11().variant(sample_time.into())),
+            channel::Id::Twelve   => self.reg.smpr2().modify(|_, w| w.smp12().variant(sample_time.into())),
+            channel::Id::Thirteen => self.reg.smpr2().modify(|_, w| w.smp13().variant(sample_time.into())),
+            channel::Id::Fourteen => self.reg.smpr2().modify(|_, w| w.smp14().variant(sample_time.into())),
+            channel::Id::Fifteen  => self.reg.smpr2().modify(|_, w| w.smp15().variant(sample_time.into())),
+            channel::Id::Sixteen  => self.reg.smpr2().modify(|_, w| w.smp16().variant(sample_time.into())),
+            channel::Id::Seventeen => self.reg.smpr2().modify(|_, w| w.smp17().variant(sample_time.into())),
+            channel::Id::Eighteen => self.reg.smpr2().modify(|_, w| w.smp18().variant(sample_time.into())),
             // #[cfg(not(feature = "gpio-f373"))]
             // _ => () // Make it a no-op for channels which are not available.
-        }
+        };
     }
 
     /// Define the total number of conversions in the regular channel conversion sequence.
@@ -1095,7 +1099,7 @@ where
     /// the end of a single conversion of a "slot" is notfied via [`Event::EndOfConversion`].
     #[inline]
     pub fn set_sequence_length(&mut self, sequence: config::Sequence) {
-        self.reg.sqr1.modify(|_, w| w.l().bits(sequence.into()));
+        self.reg.sqr1().modify(|_, w| w.l().set(sequence.into()));
     }
 
     // TODO(Sh3Rm4n): Implement, when injection mode is implemented.
@@ -1124,22 +1128,22 @@ where
         let enable: Switch = enable.into();
         let enable: bool = enable.into();
         match event {
-            Event::AdcReady => self.reg.ier.modify(|_, w| w.adrdyie().bit(enable)),
-            Event::EndOfSamplingPhase => self.reg.ier.modify(|_, w| w.eosmpie().bit(enable)),
-            Event::EndOfConversion => self.reg.ier.modify(|_, w| w.eocie().bit(enable)),
-            Event::EndOfSequence => self.reg.ier.modify(|_, w| w.eosie().bit(enable)),
-            Event::Overrun => self.reg.ier.modify(|_, w| w.ovrie().bit(enable)),
+            Event::AdcReady => self.reg.ier().modify(|_, w| w.adrdyie().bit(enable)),
+            Event::EndOfSamplingPhase => self.reg.ier().modify(|_, w| w.eosmpie().bit(enable)),
+            Event::EndOfConversion => self.reg.ier().modify(|_, w| w.eocie().bit(enable)),
+            Event::EndOfSequence => self.reg.ier().modify(|_, w| w.eosie().bit(enable)),
+            Event::Overrun => self.reg.ier().modify(|_, w| w.ovrie().bit(enable)),
             Event::InjectedChannelEndOfConversion => {
-                self.reg.ier.modify(|_, w| w.jeocie().bit(enable));
+                self.reg.ier().modify(|_, w| w.jeocie().bit(enable))
             }
             Event::InjectedChannelEndOfSequence => {
-                self.reg.ier.modify(|_, w| w.jeosie().bit(enable));
+                self.reg.ier().modify(|_, w| w.jeosie().bit(enable))
             }
-            Event::AnalogWatchdog1 => self.reg.ier.modify(|_, w| w.awd1ie().bit(enable)),
-            Event::AnalogWatchdog2 => self.reg.ier.modify(|_, w| w.awd2ie().bit(enable)),
-            Event::AnalogWatchdog3 => self.reg.ier.modify(|_, w| w.awd3ie().bit(enable)),
+            Event::AnalogWatchdog1 => self.reg.ier().modify(|_, w| w.awd1ie().bit(enable)),
+            Event::AnalogWatchdog2 => self.reg.ier().modify(|_, w| w.awd2ie().bit(enable)),
+            Event::AnalogWatchdog3 => self.reg.ier().modify(|_, w| w.awd3ie().bit(enable)),
             Event::InjectedContextQueueOverfow => {
-                self.reg.ier.modify(|_, w| w.jqovfie().bit(enable));
+                self.reg.ier().modify(|_, w| w.jqovfie().bit(enable))
             }
         };
     }
@@ -1164,7 +1168,7 @@ where
     /// Clear the given interrupt event flag.
     #[inline]
     pub fn clear_event(&mut self, event: Event) {
-        self.reg.isr.write(|w| match event {
+        self.reg.isr().write(|w| match event {
             Event::AdcReady => w.adrdy().clear(),
             Event::EndOfSamplingPhase => w.eosmp().clear(),
             Event::EndOfConversion => w.eoc().clear(),
@@ -1183,7 +1187,7 @@ where
     #[inline]
     pub fn clear_events(&mut self) {
         // SAFETY: TO clear all events, write 1 to it.
-        self.reg.isr.write(|w| unsafe { w.bits(u32::MAX) });
+        self.reg.isr().write(|w| unsafe { w.bits(u32::MAX) });
     }
 }
 
@@ -1331,27 +1335,28 @@ where
         // methods.
 
         // self.set_pin_sequence_position(config::Sequence::One, pin);
-        self.reg.sqr1.modify(|_, w|
+        self.reg.sqr1().modify(|_, w|
                 // SAFETY: channel().into() ensure the right channel value
                 unsafe { w.sq1().bits(Pin::channel().into()) });
 
         // Wait for the sequence to complete
 
         // self.clear_events();
-        self.reg.isr.reset();
+        self.reg.isr().reset();
         // self.start_conversion();
-        self.reg.cr.modify(|_, w| w.adstart().start_conversion());
+        self.reg.cr().modify(|_, w| w.adstart().start_conversion());
         // while !self.is_event_triggered(Event::EndOfConversion)
         //     && !self.is_event_triggered(Event::EndOfSequence)
         // {}
-        while !self.reg.isr.read().eoc().is_complete() && !self.reg.isr.read().eos().is_complete() {
-        }
+        while !self.reg.isr().read().eoc().is_complete()
+            && !self.reg.isr().read().eos().is_complete()
+        {}
         // self.clear_events();
-        self.reg.isr.reset();
+        self.reg.isr().reset();
 
         // Resolve this method overwrite.
         // self.data_register().into()
-        Ok(self.reg.dr.read().rdata().bits().into())
+        Ok(self.reg.dr().read().rdata().bits().into())
     }
 }
 
@@ -1440,7 +1445,6 @@ macro_rules! adc_common {
     ($(
         $ADCX_Y:ident: (
             $ADC_CHILDS:ty,
-            $ADCXYPRES_A:ident,
             $adcXYen:ident,
             $adcXYpres:ident
         ),
@@ -1457,17 +1461,22 @@ macro_rules! adc_common {
 
                     // No clock can be set, so we have to fallback to a default.
                     if self.clock(clocks).is_none() {
-                        self.ccr.modify(|_, w| w
-                            .ckmode().variant(CKMODE_A::SyncDiv1)
+                        self.ccr().modify(|_, w| w
+                            .ckmode().variant(CKMODE::SyncDiv1)
                         );
                     };
                 }
 
                 fn clock(&self, clocks: &Clocks) -> Option<Hertz> {
-                    use crate::pac::rcc::cfgr2::$ADCXYPRES_A;
+                    #[cfg(feature = "svd-f301")]
+                    use crate::pac::rcc::cfgr2::ADC1PRES as PRES;
+
+                    #[cfg(not(feature = "svd-f301"))]
+                    use crate::pac::rcc::cfgr2::ADC12PRES as PRES;
+
                     use crate::pac::RCC;
                     // SAFETY: atomic read with no side effects
-                    let adc_pres = unsafe { &(*RCC::ptr()).cfgr2.read().$adcXYpres() };
+                    let adc_pres = unsafe { &(*RCC::ptr()).cfgr2().read().$adcXYpres() };
                     // let common_adc = unsafe { &(*Self::SharedInstance::ptr()) };
 
                     // FIXME(Sh3Rm4n): ADC_PRES is not clocking the peripheral?
@@ -1477,31 +1486,31 @@ macro_rules! adc_common {
                         Some(pllclk) if !adc_pres.is_no_clock()  => {
                             pllclk
                                 / match adc_pres.variant() {
-                                    Some($ADCXYPRES_A::Div1) => 1,
-                                    Some($ADCXYPRES_A::Div2) => 2,
-                                    Some($ADCXYPRES_A::Div4) => 4,
-                                    Some($ADCXYPRES_A::Div6) => 6,
-                                    Some($ADCXYPRES_A::Div8) => 8,
-                                    Some($ADCXYPRES_A::Div10) => 10,
-                                    Some($ADCXYPRES_A::Div12) => 12,
-                                    Some($ADCXYPRES_A::Div16) => 16,
-                                    Some($ADCXYPRES_A::Div32) => 32,
-                                    Some($ADCXYPRES_A::Div64) => 64,
-                                    Some($ADCXYPRES_A::Div128) => 128,
-                                    Some($ADCXYPRES_A::Div256) => 256,
-                                    Some($ADCXYPRES_A::NoClock) | None => 1,
+                                    Some(PRES::Div1) => 1,
+                                    Some(PRES::Div2) => 2,
+                                    Some(PRES::Div4) => 4,
+                                    Some(PRES::Div6) => 6,
+                                    Some(PRES::Div8) => 8,
+                                    Some(PRES::Div10) => 10,
+                                    Some(PRES::Div12) => 12,
+                                    Some(PRES::Div16) => 16,
+                                    Some(PRES::Div32) => 32,
+                                    Some(PRES::Div64) => 64,
+                                    Some(PRES::Div128) => 128,
+                                    Some(PRES::Div256) => 256,
+                                    Some(PRES::NoClock) | None => 1,
                                 }
                         }
                         _ => {
                             clocks.sysclk()
-                                / match self.ccr.read().ckmode().variant() {
-                                    CKMODE_A::SyncDiv1 => 1,
-                                    CKMODE_A::SyncDiv2 => 2,
-                                    CKMODE_A::SyncDiv4 => 4,
+                                / match self.ccr().read().ckmode().variant() {
+                                    CKMODE::SyncDiv1 => 1,
+                                    CKMODE::SyncDiv2 => 2,
+                                    CKMODE::SyncDiv4 => 4,
                                     // Asynchronous should be enabled if PLL is on. If this line of
                                     // code is reached PLL is off. Indicate that, so fallbacks can
                                     // be set.
-                                    CKMODE_A::Asynchronous => return None,
+                                    CKMODE::Asynchronous => return None,
                                 }
                         }
                     })
@@ -1516,7 +1525,6 @@ macro_rules! adc_common {
                 $(
                     [<ADC $X _ $Y>]: (
                         (pac::[<ADC $X>], pac::[<ADC $Y>]),
-                        [<ADC $X $Y PRES_A>],
                         [<adc $X $Y en>],
                         [<adc $X $Y pres>]
                     ),
@@ -1532,7 +1540,6 @@ macro_rules! adc_common {
                 $(
                     $ADC: (
                         (pac::[<ADC $X>], pac::[<ADC $Y>]),
-                        [<ADC $X $Y PRES_A>],
                         [<adc $X $Y en>],
                         [<adc $X $Y pres>]
                     ),
@@ -1547,7 +1554,6 @@ macro_rules! adc_common {
                 $(
                     [<ADC $X _ $Y>]: (
                         pac::[<ADC $A>],
-                        [<ADC $X PRES_A>],
                         [<adc $X en>],
                         [<adc $X pres>]
                     ),
@@ -1566,7 +1572,6 @@ cfg_if::cfg_if! {
         adc!([(1, 1, 2, Interrupt::ADC1_2)]);
     }
 }
-
 // TODO(Sh3Rm4n):
 // * stm32f373 will become complicated, because no ADC1_2
 
diff --git a/src/adc/config.rs b/src/adc/config.rs
index 35ed0738..8a892fe5 100644
--- a/src/adc/config.rs
+++ b/src/adc/config.rs
@@ -29,7 +29,7 @@
 //! adc::set_align(config::Align::Right);
 //! ```
 
-use crate::pac::adc1::{cfgr, smpr1::SMP1_A, smpr2::SMP10_A};
+use crate::pac::adc1::{cfgr, smpr1::SMP1, smpr2::SMP10};
 use core::convert::TryFrom;
 
 /// The place in the sequence a given channel should be captured.
@@ -54,7 +54,7 @@ use core::convert::TryFrom;
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[allow(missing_docs)]
 pub enum Sequence {
-    One,
+    One = 0,
     Two,
     Three,
     Four,
@@ -166,24 +166,24 @@ pub enum Resolution {
     Six,
 }
 
-impl From<Resolution> for cfgr::RES_A {
+impl From<Resolution> for cfgr::RES {
     fn from(r: Resolution) -> Self {
         match r {
-            Resolution::Twelve => cfgr::RES_A::Bits12,
-            Resolution::Ten => cfgr::RES_A::Bits10,
-            Resolution::Eight => cfgr::RES_A::Bits8,
-            Resolution::Six => cfgr::RES_A::Bits6,
+            Resolution::Twelve => cfgr::RES::Bits12,
+            Resolution::Ten => cfgr::RES::Bits10,
+            Resolution::Eight => cfgr::RES::Bits8,
+            Resolution::Six => cfgr::RES::Bits6,
         }
     }
 }
 
-impl From<cfgr::RES_A> for Resolution {
-    fn from(r: cfgr::RES_A) -> Self {
+impl From<cfgr::RES> for Resolution {
+    fn from(r: cfgr::RES) -> Self {
         match r {
-            cfgr::RES_A::Bits12 => Resolution::Twelve,
-            cfgr::RES_A::Bits10 => Resolution::Ten,
-            cfgr::RES_A::Bits8 => Resolution::Eight,
-            cfgr::RES_A::Bits6 => Resolution::Six,
+            cfgr::RES::Bits12 => Resolution::Twelve,
+            cfgr::RES::Bits10 => Resolution::Ten,
+            cfgr::RES::Bits8 => Resolution::Eight,
+            cfgr::RES::Bits6 => Resolution::Six,
         }
     }
 }
@@ -239,28 +239,28 @@ pub enum ExternalTrigger {
     Tim3Cc4(TriggerMode),
 }
 
-impl From<ExternalTrigger> for cfgr::EXTSEL_A {
+impl From<ExternalTrigger> for cfgr::EXTSEL {
     fn from(et: ExternalTrigger) -> Self {
         match et {
-            ExternalTrigger::Tim1Cc1(_) => cfgr::EXTSEL_A::Tim1Cc1,
-            ExternalTrigger::Tim1Cc2(_) => cfgr::EXTSEL_A::Tim1Cc2,
-            ExternalTrigger::Tim1Cc3(_) => cfgr::EXTSEL_A::Tim1Cc3,
-            ExternalTrigger::Tim2Cc2(_) => cfgr::EXTSEL_A::Tim2Cc2,
-            ExternalTrigger::Tim3Trgo(_) => cfgr::EXTSEL_A::Tim3Trgo,
-            ExternalTrigger::Exti11(_) => cfgr::EXTSEL_A::Exti11,
-            ExternalTrigger::HrtimAdcTrg1(_) => cfgr::EXTSEL_A::HrtimAdctrg1,
-            ExternalTrigger::HrtimAdcTrg3(_) => cfgr::EXTSEL_A::HrtimAdctrg3,
-            ExternalTrigger::Tim1Trgo(_) => cfgr::EXTSEL_A::Tim1Trgo,
-            ExternalTrigger::Tim1Trgo2(_) => cfgr::EXTSEL_A::Tim1Trgo2,
-            ExternalTrigger::Tim2Trgo(_) => cfgr::EXTSEL_A::Tim2Trgo,
-            ExternalTrigger::Tim6Trgo(_) => cfgr::EXTSEL_A::Tim6Trgo,
-            ExternalTrigger::Tim15Trgo(_) => cfgr::EXTSEL_A::Tim15Trgo,
-            ExternalTrigger::Tim3Cc4(_) => cfgr::EXTSEL_A::Tim3Cc4,
+            ExternalTrigger::Tim1Cc1(_) => cfgr::EXTSEL::Tim1Cc1,
+            ExternalTrigger::Tim1Cc2(_) => cfgr::EXTSEL::Tim1Cc2,
+            ExternalTrigger::Tim1Cc3(_) => cfgr::EXTSEL::Tim1Cc3,
+            ExternalTrigger::Tim2Cc2(_) => cfgr::EXTSEL::Tim2Cc2,
+            ExternalTrigger::Tim3Trgo(_) => cfgr::EXTSEL::Tim3Trgo,
+            ExternalTrigger::Exti11(_) => cfgr::EXTSEL::Exti11,
+            ExternalTrigger::HrtimAdcTrg1(_) => cfgr::EXTSEL::HrtimAdctrg1,
+            ExternalTrigger::HrtimAdcTrg3(_) => cfgr::EXTSEL::HrtimAdctrg3,
+            ExternalTrigger::Tim1Trgo(_) => cfgr::EXTSEL::Tim1Trgo,
+            ExternalTrigger::Tim1Trgo2(_) => cfgr::EXTSEL::Tim1Trgo2,
+            ExternalTrigger::Tim2Trgo(_) => cfgr::EXTSEL::Tim2Trgo,
+            ExternalTrigger::Tim6Trgo(_) => cfgr::EXTSEL::Tim6Trgo,
+            ExternalTrigger::Tim15Trgo(_) => cfgr::EXTSEL::Tim15Trgo,
+            ExternalTrigger::Tim3Cc4(_) => cfgr::EXTSEL::Tim3Cc4,
         }
     }
 }
 
-impl From<ExternalTrigger> for cfgr::EXTEN_A {
+impl From<ExternalTrigger> for cfgr::EXTEN {
     fn from(et: ExternalTrigger) -> Self {
         match et {
             ExternalTrigger::Tim1Cc1(n)
@@ -301,12 +301,12 @@ pub enum TriggerMode {
     BothEdges,
 }
 
-impl From<TriggerMode> for cfgr::EXTEN_A {
+impl From<TriggerMode> for cfgr::EXTEN {
     fn from(tm: TriggerMode) -> Self {
         match tm {
-            TriggerMode::RisingEdge => cfgr::EXTEN_A::RisingEdge,
-            TriggerMode::FallingEdge => cfgr::EXTEN_A::FallingEdge,
-            TriggerMode::BothEdges => cfgr::EXTEN_A::BothEdges,
+            TriggerMode::RisingEdge => cfgr::EXTEN::RisingEdge,
+            TriggerMode::FallingEdge => cfgr::EXTEN::FallingEdge,
+            TriggerMode::BothEdges => cfgr::EXTEN::BothEdges,
         }
     }
 }
@@ -335,20 +335,20 @@ pub enum DataAlignment {
     Left,
 }
 
-impl From<DataAlignment> for cfgr::ALIGN_A {
+impl From<DataAlignment> for cfgr::ALIGN {
     fn from(a: DataAlignment) -> Self {
         match a {
-            DataAlignment::Right => cfgr::ALIGN_A::Right,
-            DataAlignment::Left => cfgr::ALIGN_A::Left,
+            DataAlignment::Right => cfgr::ALIGN::Right,
+            DataAlignment::Left => cfgr::ALIGN::Left,
         }
     }
 }
 
-impl From<cfgr::ALIGN_A> for DataAlignment {
-    fn from(a: cfgr::ALIGN_A) -> Self {
+impl From<cfgr::ALIGN> for DataAlignment {
+    fn from(a: cfgr::ALIGN) -> Self {
         match a {
-            cfgr::ALIGN_A::Right => DataAlignment::Right,
-            cfgr::ALIGN_A::Left => DataAlignment::Left,
+            cfgr::ALIGN::Right => DataAlignment::Right,
+            cfgr::ALIGN::Left => DataAlignment::Left,
         }
     }
 }
@@ -435,20 +435,20 @@ pub enum OverrunMode {
     Overwrite,
 }
 
-impl From<cfgr::OVRMOD_A> for OverrunMode {
-    fn from(a: cfgr::OVRMOD_A) -> Self {
+impl From<cfgr::OVRMOD> for OverrunMode {
+    fn from(a: cfgr::OVRMOD) -> Self {
         match a {
-            cfgr::OVRMOD_A::Preserve => OverrunMode::Preserve,
-            cfgr::OVRMOD_A::Overwrite => OverrunMode::Overwrite,
+            cfgr::OVRMOD::Preserve => OverrunMode::Preserve,
+            cfgr::OVRMOD::Overwrite => OverrunMode::Overwrite,
         }
     }
 }
 
-impl From<OverrunMode> for cfgr::OVRMOD_A {
+impl From<OverrunMode> for cfgr::OVRMOD {
     fn from(a: OverrunMode) -> Self {
         match a {
-            OverrunMode::Preserve => cfgr::OVRMOD_A::Preserve,
-            OverrunMode::Overwrite => cfgr::OVRMOD_A::Overwrite,
+            OverrunMode::Preserve => cfgr::OVRMOD::Preserve,
+            OverrunMode::Overwrite => cfgr::OVRMOD::Overwrite,
         }
     }
 }
@@ -542,62 +542,62 @@ impl From<SampleTime> for f32 {
     }
 }
 
-impl From<SampleTime> for SMP1_A {
+impl From<SampleTime> for SMP1 {
     fn from(t: SampleTime) -> Self {
         match t {
-            SampleTime::Cycles1C5 => Self::Cycles15,
-            SampleTime::Cycles2C5 => Self::Cycles25,
-            SampleTime::Cycles4C5 => Self::Cycles45,
-            SampleTime::Cycles7C5 => Self::Cycles75,
-            SampleTime::Cycles19C5 => Self::Cycles195,
-            SampleTime::Cycles61C5 => Self::Cycles615,
-            SampleTime::Cycles181C5 => Self::Cycles1815,
-            SampleTime::Cycles601C5 => Self::Cycles6015,
+            SampleTime::Cycles1C5 => Self::Cycles1_5,
+            SampleTime::Cycles2C5 => Self::Cycles2_5,
+            SampleTime::Cycles4C5 => Self::Cycles4_5,
+            SampleTime::Cycles7C5 => Self::Cycles7_5,
+            SampleTime::Cycles19C5 => Self::Cycles19_5,
+            SampleTime::Cycles61C5 => Self::Cycles61_5,
+            SampleTime::Cycles181C5 => Self::Cycles181_5,
+            SampleTime::Cycles601C5 => Self::Cycles601_5,
         }
     }
 }
 
-impl From<SampleTime> for SMP10_A {
+impl From<SampleTime> for SMP10 {
     fn from(t: SampleTime) -> Self {
         match t {
-            SampleTime::Cycles1C5 => Self::Cycles15,
-            SampleTime::Cycles2C5 => Self::Cycles25,
-            SampleTime::Cycles4C5 => Self::Cycles45,
-            SampleTime::Cycles7C5 => Self::Cycles75,
-            SampleTime::Cycles19C5 => Self::Cycles195,
-            SampleTime::Cycles61C5 => Self::Cycles615,
-            SampleTime::Cycles181C5 => Self::Cycles1815,
-            SampleTime::Cycles601C5 => Self::Cycles6015,
+            SampleTime::Cycles1C5 => Self::Cycles1_5,
+            SampleTime::Cycles2C5 => Self::Cycles2_5,
+            SampleTime::Cycles4C5 => Self::Cycles4_5,
+            SampleTime::Cycles7C5 => Self::Cycles7_5,
+            SampleTime::Cycles19C5 => Self::Cycles19_5,
+            SampleTime::Cycles61C5 => Self::Cycles61_5,
+            SampleTime::Cycles181C5 => Self::Cycles181_5,
+            SampleTime::Cycles601C5 => Self::Cycles601_5,
         }
     }
 }
 
-impl From<SMP1_A> for SampleTime {
-    fn from(t: SMP1_A) -> Self {
+impl From<SMP1> for SampleTime {
+    fn from(t: SMP1) -> Self {
         match t {
-            SMP1_A::Cycles15 => Self::Cycles1C5,
-            SMP1_A::Cycles25 => Self::Cycles2C5,
-            SMP1_A::Cycles45 => Self::Cycles4C5,
-            SMP1_A::Cycles75 => Self::Cycles7C5,
-            SMP1_A::Cycles195 => Self::Cycles19C5,
-            SMP1_A::Cycles615 => Self::Cycles61C5,
-            SMP1_A::Cycles1815 => Self::Cycles181C5,
-            SMP1_A::Cycles6015 => Self::Cycles601C5,
+            SMP1::Cycles1_5 => Self::Cycles1C5,
+            SMP1::Cycles2_5 => Self::Cycles2C5,
+            SMP1::Cycles4_5 => Self::Cycles4C5,
+            SMP1::Cycles7_5 => Self::Cycles7C5,
+            SMP1::Cycles19_5 => Self::Cycles19C5,
+            SMP1::Cycles61_5 => Self::Cycles61C5,
+            SMP1::Cycles181_5 => Self::Cycles181C5,
+            SMP1::Cycles601_5 => Self::Cycles601C5,
         }
     }
 }
 
-impl From<SMP10_A> for SampleTime {
-    fn from(t: SMP10_A) -> Self {
+impl From<SMP10> for SampleTime {
+    fn from(t: SMP10) -> Self {
         match t {
-            SMP10_A::Cycles15 => Self::Cycles1C5,
-            SMP10_A::Cycles25 => Self::Cycles2C5,
-            SMP10_A::Cycles45 => Self::Cycles4C5,
-            SMP10_A::Cycles75 => Self::Cycles7C5,
-            SMP10_A::Cycles195 => Self::Cycles19C5,
-            SMP10_A::Cycles615 => Self::Cycles61C5,
-            SMP10_A::Cycles1815 => Self::Cycles181C5,
-            SMP10_A::Cycles6015 => Self::Cycles601C5,
+            SMP10::Cycles1_5 => Self::Cycles1C5,
+            SMP10::Cycles2_5 => Self::Cycles2C5,
+            SMP10::Cycles4_5 => Self::Cycles4C5,
+            SMP10::Cycles7_5 => Self::Cycles7C5,
+            SMP10::Cycles19_5 => Self::Cycles19C5,
+            SMP10::Cycles61_5 => Self::Cycles61C5,
+            SMP10::Cycles181_5 => Self::Cycles181C5,
+            SMP10::Cycles601_5 => Self::Cycles601C5,
         }
     }
 }
@@ -776,7 +776,7 @@ pub enum ConversionMode {
     // Scan,
 }
 
-impl From<ConversionMode> for cfgr::CONT_A {
+impl From<ConversionMode> for cfgr::CONT {
     fn from(mode: ConversionMode) -> Self {
         match mode {
             ConversionMode::Single | ConversionMode::Discontinuous(_) => Self::Single,
@@ -785,7 +785,7 @@ impl From<ConversionMode> for cfgr::CONT_A {
     }
 }
 
-impl From<ConversionMode> for cfgr::DISCEN_A {
+impl From<ConversionMode> for cfgr::DISCEN {
     fn from(mode: ConversionMode) -> Self {
         match mode {
             ConversionMode::Single | ConversionMode::Continuous => Self::Disabled,
@@ -794,11 +794,11 @@ impl From<ConversionMode> for cfgr::DISCEN_A {
     }
 }
 
-impl From<cfgr::CONT_A> for ConversionMode {
-    fn from(mode: cfgr::CONT_A) -> Self {
+impl From<cfgr::CONT> for ConversionMode {
+    fn from(mode: cfgr::CONT) -> Self {
         match mode {
-            cfgr::CONT_A::Single => ConversionMode::Single,
-            cfgr::CONT_A::Continuous => ConversionMode::Continuous,
+            cfgr::CONT::Single => ConversionMode::Single,
+            cfgr::CONT::Continuous => ConversionMode::Continuous,
         }
     }
 }
diff --git a/src/dac.rs b/src/dac.rs
index a7e7b45e..8ebe6ee1 100644
--- a/src/dac.rs
+++ b/src/dac.rs
@@ -18,7 +18,7 @@ impl Dac {
         DAC1::reset(apb1);
 
         // Enable channel 1.
-        regs.cr.modify(|_, w| w.en1().set_bit());
+        regs.cr().modify(|_, w| w.en1().set_bit());
 
         Self { regs }
     }
@@ -27,7 +27,7 @@ impl Dac {
     ///
     /// Only the low 12 bits of `data` will be used, the rest is ignored.
     pub fn write_data(&mut self, data: u16) {
-        self.regs.dhr12r1.write(|w| {
+        self.regs.dhr12r1().write(|w| {
             #[allow(unused_unsafe)]
             // SAFETY: Direct write to register for easier sharing between different stm32f3xx svd
             // generated API
diff --git a/src/dma.rs b/src/dma.rs
index 01f771c9..addc8253 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -211,11 +211,11 @@ pub enum Increment {
     Disable,
 }
 
-impl From<Increment> for cr::PINC_A {
+impl From<Increment> for cr::PINC {
     fn from(inc: Increment) -> Self {
         match inc {
-            Increment::Enable => cr::PINC_A::Enabled,
-            Increment::Disable => cr::PINC_A::Disabled,
+            Increment::Enable => cr::PINC::Enabled,
+            Increment::Disable => cr::PINC::Disabled,
         }
     }
 }
@@ -234,13 +234,13 @@ pub enum Priority {
     VeryHigh,
 }
 
-impl From<Priority> for cr::PL_A {
+impl From<Priority> for cr::PL {
     fn from(prio: Priority) -> Self {
         match prio {
-            Priority::Low => cr::PL_A::Low,
-            Priority::Medium => cr::PL_A::Medium,
-            Priority::High => cr::PL_A::High,
-            Priority::VeryHigh => cr::PL_A::VeryHigh,
+            Priority::Low => cr::PL::Low,
+            Priority::Medium => cr::PL::Medium,
+            Priority::High => cr::PL::High,
+            Priority::VeryHigh => cr::PL::VeryHigh,
         }
     }
 }
@@ -255,11 +255,11 @@ pub enum Direction {
     FromPeripheral,
 }
 
-impl From<Direction> for cr::DIR_A {
+impl From<Direction> for cr::DIR {
     fn from(dir: Direction) -> Self {
         match dir {
-            Direction::FromMemory => cr::DIR_A::FromMemory,
-            Direction::FromPeripheral => cr::DIR_A::FromPeripheral,
+            Direction::FromMemory => cr::DIR::FromMemory,
+            Direction::FromPeripheral => cr::DIR::FromPeripheral,
         }
     }
 }
@@ -302,10 +302,10 @@ pub trait Channel: private::Channel {
     /// Reset the control registers of this channel.
     /// This stops any ongoing transfers.
     fn reset(&mut self) {
-        self.ch().cr.reset();
-        self.ch().ndtr.reset();
-        self.ch().par.reset();
-        self.ch().mar.reset();
+        self.ch().cr().reset();
+        self.ch().ndtr().reset();
+        self.ch().par().reset();
+        self.ch().mar().reset();
         self.clear_event(Event::Any);
     }
 
@@ -327,9 +327,9 @@ pub trait Channel: private::Channel {
 
         // SAFETY: If the caller does ensure, that address is valid address, this should be safe
         unsafe {
-            self.ch().par.write(|w| w.pa().bits(address));
+            self.ch().par().write(|w| w.pa().bits(address));
         }
-        self.ch().cr.modify(|_, w| w.pinc().variant(inc.into()));
+        self.ch().cr().modify(|_, w| w.pinc().variant(inc.into()));
     }
 
     /// Set the base address of the memory area from/to which
@@ -350,9 +350,9 @@ pub trait Channel: private::Channel {
 
         // SAFETY: If the caller does ensure, that address is valid address, this should be safe
         unsafe {
-            self.ch().mar.write(|w| w.ma().bits(address));
+            self.ch().mar().write(|w| w.ma().bits(address));
         }
-        self.ch().cr.modify(|_, w| w.minc().variant(inc.into()));
+        self.ch().cr().modify(|_, w| w.minc().variant(inc.into()));
     }
 
     /// Set the number of words to transfer.
@@ -365,7 +365,9 @@ pub trait Channel: private::Channel {
     fn set_transfer_length(&mut self, len: u16) {
         crate::assert!(!self.is_enabled());
 
-        self.ch().ndtr.write(|w| w.ndt().bits(len));
+        unsafe {
+            self.ch().ndtr().write(|w| w.ndt().bits(len));
+        }
     }
 
     /// Set the word size.
@@ -374,7 +376,7 @@ pub trait Channel: private::Channel {
     ///
     /// Panics if the word size is not one of 8, 16, or 32 bits.
     fn set_word_size<W>(&mut self) {
-        use cr::PSIZE_A::{Bits16, Bits32, Bits8};
+        use cr::PSIZE::{Bits16, Bits32, Bits8};
 
         let psize = match mem::size_of::<W>() {
             1 => Bits8,
@@ -386,7 +388,7 @@ pub trait Channel: private::Channel {
             _ => defmt::panic!("unsupported word size"),
         };
 
-        self.ch().cr.modify(|_, w| {
+        self.ch().cr().modify(|_, w| {
             w.psize().variant(psize);
             w.msize().variant(psize)
         });
@@ -395,27 +397,27 @@ pub trait Channel: private::Channel {
     /// Set the priority level of this channel
     fn set_priority_level(&mut self, priority: Priority) {
         let pl = priority.into();
-        self.ch().cr.modify(|_, w| w.pl().variant(pl));
+        self.ch().cr().modify(|_, w| w.pl().variant(pl));
     }
 
     /// Set the transfer direction
     fn set_direction(&mut self, direction: Direction) {
         let dir = direction.into();
-        self.ch().cr.modify(|_, w| w.dir().variant(dir));
+        self.ch().cr().modify(|_, w| w.dir().variant(dir));
     }
 
     /// Enable or disable the interrupt for the specified [`Event`].
     fn configure_intterupt(&mut self, event: Event, enable: bool) {
         match event {
-            Event::HalfTransfer => self.ch().cr.modify(|_, w| w.htie().bit(enable)),
-            Event::TransferComplete => self.ch().cr.modify(|_, w| w.tcie().bit(enable)),
-            Event::TransferError => self.ch().cr.modify(|_, w| w.teie().bit(enable)),
-            Event::Any => self.ch().cr.modify(|_, w| {
+            Event::HalfTransfer => self.ch().cr().modify(|_, w| w.htie().bit(enable)),
+            Event::TransferComplete => self.ch().cr().modify(|_, w| w.tcie().bit(enable)),
+            Event::TransferError => self.ch().cr().modify(|_, w| w.teie().bit(enable)),
+            Event::Any => self.ch().cr().modify(|_, w| {
                 w.htie().bit(enable);
                 w.tcie().bit(enable);
                 w.teie().bit(enable)
             }),
-        }
+        };
     }
 
     /// Enable the interrupt for the given [`Event`].
@@ -431,17 +433,17 @@ pub trait Channel: private::Channel {
     /// Start a transfer
     fn enable(&mut self) {
         self.clear_event(Event::Any);
-        self.ch().cr.modify(|_, w| w.en().enabled());
+        self.ch().cr().modify(|_, w| w.en().enabled());
     }
 
     /// Stop the current transfer
     fn disable(&mut self) {
-        self.ch().cr.modify(|_, w| w.en().disabled());
+        self.ch().cr().modify(|_, w| w.en().disabled());
     }
 
     /// Is there a transfer in progress on this channel?
     fn is_enabled(&self) -> bool {
-        self.ch().cr.read().en().is_enabled()
+        self.ch().cr().read().en().is_enabled()
     }
 }
 
@@ -460,9 +462,8 @@ macro_rules! dma {
         $DMAx:ident, $dmax:ident, $dmaxen:ident,
         channels: {
             $( $Ci:ident: (
+                $i:literal,
                 $chi:ident,
-                $htifi:ident, $tcifi:ident, $teifi:ident, $gifi:ident,
-                $chtifi:ident, $ctcifi:ident, $cteifi:ident, $cgifi:ident
             ), )+
         },
     ) => {
@@ -517,30 +518,30 @@ macro_rules! dma {
                     impl private::Channel for $Ci {
                         fn ch(&self) -> &pac::dma1::CH {
                             // SAFETY: $Ci grants exclusive access to this register
-                            unsafe { &(*$DMAx::ptr()).$chi }
+                            unsafe { &(*$DMAx::ptr()).ch($i) }
                         }
                     }
 
                     impl Channel for $Ci {
                         fn is_event_triggered(&self, event: Event) -> bool {
                             // SAFETY: atomic read
-                            let flags = unsafe { (*$DMAx::ptr()).isr.read() };
+                            let flags = unsafe { (*$DMAx::ptr()).isr().read() };
                             match event {
-                                Event::HalfTransfer => flags.$htifi().bit_is_set(),
-                                Event::TransferComplete => flags.$tcifi().bit_is_set(),
-                                Event::TransferError => flags.$teifi().bit_is_set(),
-                                Event::Any => flags.$gifi().bit_is_set(),
+                                Event::HalfTransfer => flags.htif($i).bit_is_set(),
+                                Event::TransferComplete => flags.tcif($i).bit_is_set(),
+                                Event::TransferError => flags.teif($i).bit_is_set(),
+                                Event::Any => flags.gif($i).bit_is_set(),
                             }
                         }
 
                         fn clear_event(&mut self, event: Event) {
                             // SAFETY: atomic write to a stateless register
                             unsafe {
-                                (*$DMAx::ptr()).ifcr.write(|w| match event {
-                                    Event::HalfTransfer => w.$chtifi().set_bit(),
-                                    Event::TransferComplete => w.$ctcifi().set_bit(),
-                                    Event::TransferError => w.$cteifi().set_bit(),
-                                    Event::Any => w.$cgifi().set_bit(),
+                                (*$DMAx::ptr()).ifcr().write(|w| match event {
+                                    Event::HalfTransfer => w.chtif($i).set_bit(),
+                                    Event::TransferComplete => w.ctcif($i).set_bit(),
+                                    Event::TransferError => w.cteif($i).set_bit(),
+                                    Event::Any => w.cgif($i).set_bit(),
                                 });
                             }
                         }
@@ -556,17 +557,9 @@ macro_rules! dma {
                 [<DMA $X>], [<dma $X>], [<dma $X en>],
                 channels: {
                     $(
-                        [<C $C>]:
-			(
+                        [<C $C>]: (
+                            $C,
                             [<ch $C>],
-                            [<htif $C>],
-                            [<tcif $C>],
-                            [<teif $C>],
-                            [<gif $C>],
-                            [<chtif $C>],
-                            [<ctcif $C>],
-                            [<cteif $C>],
-                            [<cgif $C>]
                         ),
                     )+
                 },
diff --git a/src/flash.rs b/src/flash.rs
index 31600b61..e7400c5f 100644
--- a/src/flash.rs
+++ b/src/flash.rs
@@ -42,6 +42,6 @@ impl ACR {
     #[allow(clippy::unused_self)]
     pub(crate) fn acr(&mut self) -> &flash::ACR {
         // SAFETY: This proxy grants exclusive access to this register
-        unsafe { &(*FLASH::ptr()).acr }
+        unsafe { &(*FLASH::ptr()).acr() }
     }
 }
diff --git a/src/gpio.rs b/src/gpio.rs
index 81ba0fdb..e1dfe482 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -556,7 +556,7 @@ where
 #[cfg(feature = "svd-f373")]
 macro_rules! reg_for_cpu {
     ($exti:expr, $xr:ident) => {
-        $exti.$xr
+        $exti.$xr()
     };
 }
 
@@ -565,7 +565,7 @@ macro_rules! reg_for_cpu {
 macro_rules! reg_for_cpu {
     ($exti:expr, $xr:ident) => {
         paste::paste! {
-            $exti.[<$xr 1>]
+            $exti.[<$xr 1>]()
         }
     };
 }
@@ -753,24 +753,24 @@ macro_rules! gpio_trait {
             impl GpioRegExt for crate::pac::$gpioy::RegisterBlock {
                 #[inline(always)]
                 fn is_low(&self, i: u8) -> bool {
-                    self.idr.read().bits() & (1 << i) == 0
+                    self.idr().read().idr(i).is_low()
                 }
 
                 #[inline(always)]
                 fn is_set_low(&self, i: u8) -> bool {
-                    self.odr.read().bits() & (1 << i) == 0
+                    self.odr().read().odr(i).is_low()
                 }
 
                 #[inline(always)]
                 fn set_high(&self, i: u8) {
                     // SAFETY: atomic write to a stateless register
-                    unsafe { self.bsrr.write(|w| w.bits(1 << i)) };
+                    self.bsrr().write(|w| w.bs(i).set_bit());
                 }
 
                 #[inline(always)]
                 fn set_low(&self, i: u8) {
                     // SAFETY: atomic write to a stateless register
-                    unsafe { self.bsrr.write(|w| w.bits(1 << (16 + i))) };
+                    self.bsrr().write(|w| w.br(i).set_bit());
                 }
             }
         )+
@@ -794,7 +794,7 @@ macro_rules! r_trait {
                     let value = $gpioy::$xr::$enum::$VARIANT as u32;
                     // SAFETY: The &mut abstracts all accesses to the register itself,
                     // which makes sure that this register accesss is exclusive
-                    unsafe { crate::modify_at!((*$GPIOX::ptr()).$xr, $bitwidth, i, value) };
+                    unsafe { crate::modify_at!((*$GPIOX::ptr()).$xr(), $bitwidth, i, value) };
                 }
             )+
         }
@@ -935,7 +935,7 @@ macro_rules! gpio {
                     const BITWIDTH: u8 = 4;
                     // SAFETY: the abstraction of AFRL should ensure exclusive access in addition
                     // to the &mut exclusive reference
-                    unsafe { crate::modify_at!((*$GPIOX::ptr()).afrh, BITWIDTH, i - 8, x as u32) };
+                    unsafe { crate::modify_at!((*$GPIOX::ptr()).afrh(), BITWIDTH, i - 8, x as u32) };
                 }
             }
 
@@ -948,7 +948,7 @@ macro_rules! gpio {
                     const BITWIDTH: u8 = 4;
                     // SAFETY: the abstraction of AFRL should ensure exclusive access in addition
                     // to the &mut exclusive reference
-                    unsafe { crate::modify_at!((*$GPIOX::ptr()).afrl, BITWIDTH, i, x as u32) };
+                    unsafe { crate::modify_at!((*$GPIOX::ptr()).afrl(), BITWIDTH, i, x as u32) };
                 }
             }
 
@@ -956,7 +956,7 @@ macro_rules! gpio {
             pub struct MODER(());
 
             r_trait! {
-                ($GPIOX, $gpioy::moder::MODER15_A, 2);
+                ($GPIOX, $gpioy::moder::MODER0, 2);
                 impl Moder for MODER {
                     fn input { Input }
                     fn output { Output }
@@ -969,7 +969,7 @@ macro_rules! gpio {
             pub struct OSPEEDR(());
 
             r_trait! {
-                ($GPIOX, $gpioy::ospeedr::OSPEEDR15_A, 2);
+                ($GPIOX, $gpioy::ospeedr::OSPEEDR0, 2);
                 impl Ospeedr for OSPEEDR {
                     fn low { LowSpeed }
                     fn medium { MediumSpeed }
@@ -981,7 +981,7 @@ macro_rules! gpio {
             pub struct OTYPER(());
 
             r_trait! {
-                ($GPIOX, $gpioy::otyper::OT15_A, 1);
+                ($GPIOX, $gpioy::otyper::OT0, 1);
                 impl Otyper for OTYPER {
                     fn push_pull { PushPull }
                     fn open_drain { OpenDrain }
@@ -992,7 +992,7 @@ macro_rules! gpio {
             pub struct PUPDR(());
 
             r_trait! {
-                ($GPIOX, $gpioy::pupdr::PUPDR15_A, 2);
+                ($GPIOX, $gpioy::pupdr::PUPDR0, 2);
                 impl Pupdr for PUPDR {
                     fn floating { Floating }
                     fn pull_up { PullUp }
diff --git a/src/i2c.rs b/src/i2c.rs
index b456944f..32a4997c 100644
--- a/src/i2c.rs
+++ b/src/i2c.rs
@@ -11,7 +11,7 @@ use core::{convert::TryFrom, ops::Deref};
 use crate::{
     gpio::{gpioa, gpiob, OpenDrain, AF4},
     hal::blocking::i2c::{Read, Write, WriteRead},
-    pac::{i2c1::RegisterBlock, rcc::cfgr3::I2C1SW_A, I2C1, RCC},
+    pac::{i2c1::RegisterBlock, rcc::cfgr3::I2C1SW, I2C1, RCC},
     rcc::{self, Clocks},
     time::{
         fixed_point::FixedPoint,
@@ -91,8 +91,8 @@ pub struct I2c<I2C, PINS> {
 macro_rules! busy_wait {
     ($i2c:expr, $flag:ident, $variant:ident) => {
         loop {
-            let isr = $i2c.isr.read();
-            let icr = &$i2c.icr;
+            let isr = $i2c.isr().read();
+            let icr = &$i2c.icr();
 
             if isr.arlo().is_lost() {
                 icr.write(|w| w.arlocf().clear());
@@ -101,7 +101,7 @@ macro_rules! busy_wait {
                 icr.write(|w| w.berrcf().clear());
                 return Err(Error::Bus);
             } else if isr.nackf().is_nack() {
-                while $i2c.isr.read().stopf().is_no_stop() {}
+                while $i2c.isr().read().stopf().is_no_stop() {}
                 icr.write(|w| w.nackcf().clear());
                 icr.write(|w| w.stopcf().clear());
                 return Err(Error::Nack);
@@ -190,21 +190,21 @@ impl<I2C, SCL, SDA> I2c<I2C, (SCL, SDA)> {
 
         // Configure for "fast mode" (400 KHz)
         // NOTE(write): writes all non-reserved bits.
-        i2c.timingr.write(|w| {
+        i2c.timingr().write(|w| {
             w.presc()
-                .bits(crate::unwrap!(u8::try_from(presc)))
+                .set(crate::unwrap!(u8::try_from(presc)))
                 .sdadel()
-                .bits(crate::unwrap!(u8::try_from(sdadel)))
+                .set(crate::unwrap!(u8::try_from(sdadel)))
                 .scldel()
-                .bits(crate::unwrap!(u8::try_from(scldel)))
+                .set(crate::unwrap!(u8::try_from(scldel)))
                 .scll()
-                .bits(scl_low)
+                .set(scl_low)
                 .sclh()
-                .bits(scl_high)
+                .set(scl_high)
         });
 
         // Enable the peripheral
-        i2c.cr1.modify(|_, w| w.pe().set_bit());
+        i2c.cr1().modify(|_, w| w.pe().set_bit());
 
         Self { i2c, pins }
     }
@@ -238,7 +238,7 @@ where
         crate::assert!(!buffer.is_empty());
 
         // Detect Bus busy
-        if self.i2c.isr.read().busy().is_busy() {
+        if self.i2c.isr().read().busy().is_busy() {
             return Err(Error::Busy);
         }
 
@@ -247,15 +247,14 @@ where
         // Process 255 bytes at a time
         for (i, buffer) in buffer.chunks_mut(0xFF).enumerate() {
             // Prepare to receive `bytes`
-            self.i2c.cr2.modify(|_, w| {
+            self.i2c.cr2().modify(|_, w| {
                 if i == 0 {
                     w.add10().bit7();
-                    w.sadd()
-                        .bits(u16::from(crate::unwrap!(addr.checked_shl(1))));
+                    w.sadd().set(u16::from(crate::unwrap!(addr.checked_shl(1))));
                     w.rd_wrn().read();
                     w.start().start();
                 }
-                w.nbytes().bits(crate::unwrap!(u8::try_from(buffer.len())));
+                w.nbytes().set(crate::unwrap!(u8::try_from(buffer.len())));
                 if i == end {
                     w.reload().completed().autoend().automatic()
                 } else {
@@ -267,7 +266,7 @@ where
                 // Wait until we have received something
                 busy_wait!(self.i2c, rxne, is_not_empty);
 
-                *byte = self.i2c.rxdr.read().rxdata().bits();
+                *byte = self.i2c.rxdr().read().rxdata().bits();
             }
 
             if i != end {
@@ -280,7 +279,7 @@ where
         // Wait until the last transmission is finished
         busy_wait!(self.i2c, stopf, is_stop);
 
-        self.i2c.icr.write(|w| w.stopcf().clear());
+        self.i2c.icr().write(|w| w.stopcf().clear());
 
         Ok(())
     }
@@ -294,18 +293,17 @@ where
 
     fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
         // Detect Bus busy
-        if self.i2c.isr.read().busy().is_busy() {
+        if self.i2c.isr().read().busy().is_busy() {
             return Err(Error::Busy);
         }
 
         if bytes.is_empty() {
             // 0 byte write
-            self.i2c.cr2.modify(|_, w| {
+            self.i2c.cr2().modify(|_, w| {
                 w.add10().bit7();
-                w.sadd()
-                    .bits(u16::from(crate::unwrap!(addr.checked_shl(1))));
+                w.sadd().set(u16::from(crate::unwrap!(addr.checked_shl(1))));
                 w.rd_wrn().write();
-                w.nbytes().bits(0);
+                w.nbytes().set(0);
                 w.reload().completed();
                 w.autoend().automatic();
                 w.start().start()
@@ -316,15 +314,14 @@ where
             // Process 255 bytes at a time
             for (i, bytes) in bytes.chunks(0xFF).enumerate() {
                 // Prepare to send `bytes`
-                self.i2c.cr2.modify(|_, w| {
+                self.i2c.cr2().modify(|_, w| {
                     if i == 0 {
                         w.add10().bit7();
-                        w.sadd()
-                            .bits(u16::from(crate::unwrap!(addr.checked_shl(1))));
+                        w.sadd().set(u16::from(crate::unwrap!(addr.checked_shl(1))));
                         w.rd_wrn().write();
                         w.start().start();
                     }
-                    w.nbytes().bits(crate::unwrap!(u8::try_from(bytes.len())));
+                    w.nbytes().set(crate::unwrap!(u8::try_from(bytes.len())));
                     if i == end {
                         w.reload().completed().autoend().automatic()
                     } else {
@@ -339,7 +336,7 @@ where
 
                     // Put byte on the wire
                     // NOTE(write): Writes all non-reserved bits.
-                    self.i2c.txdr.write(|w| w.txdata().bits(*byte));
+                    self.i2c.txdr().write(|w| w.txdata().set(*byte));
                 }
 
                 if i != end {
@@ -353,7 +350,7 @@ where
         // Wait until the last transmission is finished
         busy_wait!(self.i2c, stopf, is_stop);
 
-        self.i2c.icr.write(|w| w.stopcf().clear());
+        self.i2c.icr().write(|w| w.stopcf().clear());
 
         Ok(())
     }
@@ -369,7 +366,7 @@ where
         crate::assert!(!bytes.is_empty() && !buffer.is_empty());
 
         // Detect Bus busy
-        if self.i2c.isr.read().busy().is_busy() {
+        if self.i2c.isr().read().busy().is_busy() {
             return Err(Error::Busy);
         }
 
@@ -378,15 +375,14 @@ where
         // Process 255 bytes at a time
         for (i, bytes) in bytes.chunks(0xFF).enumerate() {
             // Prepare to send `bytes`
-            self.i2c.cr2.modify(|_, w| {
+            self.i2c.cr2().modify(|_, w| {
                 if i == 0 {
                     w.add10().bit7();
-                    w.sadd()
-                        .bits(u16::from(crate::unwrap!(addr.checked_shl(1))));
+                    w.sadd().set(u16::from(crate::unwrap!(addr.checked_shl(1))));
                     w.rd_wrn().write();
                     w.start().start();
                 }
-                w.nbytes().bits(crate::unwrap!(u8::try_from(bytes.len())));
+                w.nbytes().set(crate::unwrap!(u8::try_from(bytes.len())));
                 if i == end {
                     w.reload().completed().autoend().software()
                 } else {
@@ -401,7 +397,7 @@ where
 
                 // Put byte on the wire
                 // NOTE(write): Writes all non-reserved bits.
-                self.i2c.txdr.write(|w| w.txdata().bits(*byte));
+                self.i2c.txdr().write(|w| w.txdata().set(*byte));
             }
 
             if i != end {
@@ -420,15 +416,14 @@ where
         // Process 255 bytes at a time
         for (i, buffer) in buffer.chunks_mut(0xFF).enumerate() {
             // Prepare to receive `bytes`
-            self.i2c.cr2.modify(|_, w| {
+            self.i2c.cr2().modify(|_, w| {
                 if i == 0 {
                     w.add10().bit7();
-                    w.sadd()
-                        .bits(u16::from(crate::unwrap!(addr.checked_shl(1))));
+                    w.sadd().set(u16::from(crate::unwrap!(addr.checked_shl(1))));
                     w.rd_wrn().read();
                     w.start().start();
                 }
-                w.nbytes().bits(crate::unwrap!(u8::try_from(buffer.len())));
+                w.nbytes().set(crate::unwrap!(u8::try_from(buffer.len())));
                 if i == end {
                     w.reload().completed().autoend().automatic()
                 } else {
@@ -440,7 +435,7 @@ where
                 // Wait until we have received something
                 busy_wait!(self.i2c, rxne, is_not_empty);
 
-                *byte = self.i2c.rxdr.read().rxdata().bits();
+                *byte = self.i2c.rxdr().read().rxdata().bits();
             }
 
             if i != end {
@@ -453,7 +448,7 @@ where
         // Wait until the last transmission is finished
         busy_wait!(self.i2c, stopf, is_stop);
 
-        self.i2c.icr.write(|w| w.stopcf().clear());
+        self.i2c.icr().write(|w| w.stopcf().clear());
 
         Ok(())
     }
@@ -473,9 +468,9 @@ macro_rules! i2c {
             impl Instance for $I2CX {
                 fn clock(clocks: &Clocks) -> Hertz {
                     // SAFETY: atomic read of valid pointer with no side effects
-                    match unsafe { (*RCC::ptr()).cfgr3.read().$i2cXsw().variant() } {
-                        I2C1SW_A::Hsi => crate::rcc::HSI,
-                        I2C1SW_A::Sysclk => clocks.sysclk(),
+                    match unsafe { (*RCC::ptr()).cfgr3().read().$i2cXsw().variant() } {
+                        I2C1SW::Hsi => crate::rcc::HSI,
+                        I2C1SW::Sysclk => clocks.sysclk(),
                     }
                 }
             }
diff --git a/src/pwm.rs b/src/pwm.rs
index f2489fee..464badeb 100644
--- a/src/pwm.rs
+++ b/src/pwm.rs
@@ -298,7 +298,7 @@ macro_rules! pwm_timer_private {
             }
 
             // enable auto reload preloader
-            tim.cr1.modify(|_, w| w.arpe().set_bit());
+            tim.cr1().modify(|_, w| w.arpe().set_bit());
 
             // Set the "resolution" of the duty cycle (ticks before restarting at 0)
             // Oddly this is unsafe for some timers and not others
@@ -306,7 +306,7 @@ macro_rules! pwm_timer_private {
             // NOTE(write): not all timers are documented in stm32f3, thus marked unsafe.
             // This write uses all bits of this register so there are no unknown side effects.
             #[allow(unused_unsafe)]
-            tim.arr.write(|w| unsafe {
+            tim.arr().write(|w| unsafe {
                 w.arr().bits(res)
             });
 
@@ -317,18 +317,18 @@ macro_rules! pwm_timer_private {
             let clock_freq = clocks.$pclkz().0 * if clocks.ppre1() == 1 { 1 } else { 2 };
             let prescale_factor = clock_freq / res as u32 / freq.integer();
             // NOTE(write): uses all bits of this register.
-            tim.psc.write(|w| w.psc().bits(prescale_factor as u16 - 1));
+            tim.psc().write(|w| w.psc().set(prescale_factor as u16 - 1));
 
             // Make the settings reload immediately
             // NOTE(write): write to a state-less register.
-            tim.egr.write(|w| w.ug().set_bit());
+            tim.egr().write(|w| w.ug().set_bit());
 
             // Enable outputs (STM32 Break Timer Specific)
             #[allow(clippy::redundant_closure_call)]
             $enable_break_timer(&tim);
 
             // Enable the Timer
-            tim.cr1.modify(|_, w| w.cen().set_bit());
+            tim.cr1().modify(|_, w| w.cen().set_bit());
 
             // TODO: Passing in the constructor is a bit silly,
             // is there an alternative approach to get this to repeat,
@@ -359,7 +359,7 @@ macro_rules! pwm_timer_with_break {
             $TIMx,
             $res,
             $pclkz,
-            |tim: &$TIMx| tim.bdtr.modify(|_, w| w.moe().set_bit()),
+            |tim: &$TIMx| tim.bdtr().modify(|_, w| w.moe().set_bit()),
             [$($TIMx_CHy),+],
             [$($x),+]
         );
@@ -544,7 +544,7 @@ macro_rules! pwm_pin_for_pwm_channel_private {
             fn disable(&mut self) {
                 unsafe {
                     (*$TIMx::ptr())
-                        .ccer
+                        .ccer()
                         .modify(|_, w| w.$ccx_enable().clear_bit());
                 }
             }
@@ -552,13 +552,13 @@ macro_rules! pwm_pin_for_pwm_channel_private {
             fn enable(&mut self) {
                 unsafe {
                     (*$TIMx::ptr())
-                        .ccer
+                        .ccer()
                         .modify(|_, w| w.$ccx_enable().set_bit());
                 }
             }
 
             fn get_max_duty(&self) -> Self::Duty {
-                unsafe { (*$TIMx::ptr()).arr.read().arr().bits() }
+                unsafe { (*$TIMx::ptr()).arr().read().arr().bits() }
             }
 
             fn get_duty(&self) -> Self::Duty {
diff --git a/src/rcc.rs b/src/rcc.rs
index 382a2059..414d5872 100644
--- a/src/rcc.rs
+++ b/src/rcc.rs
@@ -169,14 +169,14 @@ macro_rules! bus_struct {
                 fn enr(&self) -> &rcc::$EN {
                     // FIXME: this should still be shared carefully
                     // SAFETY: this proxy grants exclusive access to this register
-                    unsafe { &(*RCC::ptr()).$en }
+                    unsafe { &(*RCC::ptr()).$en() }
                 }
 
                 #[allow(unused)]
                 fn rstr(&self) -> &rcc::$RST {
                     // FIXME: this should still be shared carefully
                     // SAFETY: this proxy grants exclusive access to this register
-                    unsafe { &(*RCC::ptr()).$rst }
+                    unsafe { &(*RCC::ptr()).$rst() }
                 }
             }
         )+
@@ -334,7 +334,7 @@ mod usb_clocking {
         hse: Option<u32>,
         pclk1: u32,
         pll_config: &Option<PllConfig>,
-    ) -> (cfgr::USBPRE_A, bool) {
+    ) -> (cfgr::USBPRE, bool) {
         // the USB clock is only valid if an external crystal is used, the PLL is enabled, and the
         // PLL output frequency is a supported one.
         // usbpre == false: divide clock by 1.5, otherwise no division
@@ -343,16 +343,16 @@ mod usb_clocking {
         // problems. [RM0316 32.5.2]
         if pclk1 >= 10_000_000 {
             match (usb_ok, sysclk) {
-                (true, 72_000_000) => (cfgr::USBPRE_A::Div15, true),
-                (true, 48_000_000) => (cfgr::USBPRE_A::Div1, true),
-                _ => (cfgr::USBPRE_A::Div1, false),
+                (true, 72_000_000) => (cfgr::USBPRE::Div1_5, true),
+                (true, 48_000_000) => (cfgr::USBPRE::Div1, true),
+                _ => (cfgr::USBPRE::Div1, false),
             }
         } else {
-            (cfgr::USBPRE_A::Div1, false)
+            (cfgr::USBPRE::Div1, false)
         }
     }
 
-    pub(crate) fn set_usbpre(w: &mut cfgr::W, usb_prescale: cfgr::USBPRE_A) -> &mut cfgr::W {
+    pub(crate) fn set_usbpre(w: &mut cfgr::W, usb_prescale: cfgr::USBPRE) -> &mut cfgr::W {
         w.usbpre().variant(usb_prescale)
     }
 }
@@ -368,7 +368,7 @@ impl BDCR {
     #[must_use]
     pub(crate) fn bdcr(&mut self) -> &rcc::BDCR {
         // SAFETY: this proxy grants exclusive access to this register
-        unsafe { &(*RCC::ptr()).bdcr }
+        unsafe { &(*RCC::ptr()).bdcr() }
     }
 }
 
@@ -408,9 +408,9 @@ impl Default for CFGR {
 }
 
 pub(crate) struct PllConfig {
-    src: cfgr::PLLSRC_A,
-    mul: cfgr::PLLMUL_A,
-    div: Option<cfgr2::PREDIV_A>,
+    src: cfgr::PLLSRC,
+    mul: cfgr::PLLMUL,
+    div: Option<cfgr2::PREDIV>,
 }
 
 /// Determine the [greatest common divisor](https://en.wikipedia.org/wiki/Greatest_common_divisor)
@@ -428,46 +428,46 @@ fn gcd(mut a: u32, mut b: u32) -> u32 {
 }
 
 /// Convert pll multiplier into equivalent register field type
-fn into_pll_mul(mul: u8) -> cfgr::PLLMUL_A {
+fn into_pll_mul(mul: u8) -> cfgr::PLLMUL {
     match mul {
-        2 => cfgr::PLLMUL_A::Mul2,
-        3 => cfgr::PLLMUL_A::Mul3,
-        4 => cfgr::PLLMUL_A::Mul4,
-        5 => cfgr::PLLMUL_A::Mul5,
-        6 => cfgr::PLLMUL_A::Mul6,
-        7 => cfgr::PLLMUL_A::Mul7,
-        8 => cfgr::PLLMUL_A::Mul8,
-        9 => cfgr::PLLMUL_A::Mul9,
-        10 => cfgr::PLLMUL_A::Mul10,
-        11 => cfgr::PLLMUL_A::Mul11,
-        12 => cfgr::PLLMUL_A::Mul12,
-        13 => cfgr::PLLMUL_A::Mul13,
-        14 => cfgr::PLLMUL_A::Mul14,
-        15 => cfgr::PLLMUL_A::Mul15,
-        16 => cfgr::PLLMUL_A::Mul16,
+        2 => cfgr::PLLMUL::Mul2,
+        3 => cfgr::PLLMUL::Mul3,
+        4 => cfgr::PLLMUL::Mul4,
+        5 => cfgr::PLLMUL::Mul5,
+        6 => cfgr::PLLMUL::Mul6,
+        7 => cfgr::PLLMUL::Mul7,
+        8 => cfgr::PLLMUL::Mul8,
+        9 => cfgr::PLLMUL::Mul9,
+        10 => cfgr::PLLMUL::Mul10,
+        11 => cfgr::PLLMUL::Mul11,
+        12 => cfgr::PLLMUL::Mul12,
+        13 => cfgr::PLLMUL::Mul13,
+        14 => cfgr::PLLMUL::Mul14,
+        15 => cfgr::PLLMUL::Mul15,
+        16 => cfgr::PLLMUL::Mul16,
         _ => crate::unreachable!(),
     }
 }
 
 /// Convert pll divisor into equivalent register field type
-fn into_pre_div(div: u8) -> cfgr2::PREDIV_A {
+fn into_pre_div(div: u8) -> cfgr2::PREDIV {
     match div {
-        1 => cfgr2::PREDIV_A::Div1,
-        2 => cfgr2::PREDIV_A::Div2,
-        3 => cfgr2::PREDIV_A::Div3,
-        4 => cfgr2::PREDIV_A::Div4,
-        5 => cfgr2::PREDIV_A::Div5,
-        6 => cfgr2::PREDIV_A::Div6,
-        7 => cfgr2::PREDIV_A::Div7,
-        8 => cfgr2::PREDIV_A::Div8,
-        9 => cfgr2::PREDIV_A::Div9,
-        10 => cfgr2::PREDIV_A::Div10,
-        11 => cfgr2::PREDIV_A::Div11,
-        12 => cfgr2::PREDIV_A::Div12,
-        13 => cfgr2::PREDIV_A::Div13,
-        14 => cfgr2::PREDIV_A::Div14,
-        15 => cfgr2::PREDIV_A::Div15,
-        16 => cfgr2::PREDIV_A::Div16,
+        1 => cfgr2::PREDIV::Div1,
+        2 => cfgr2::PREDIV::Div2,
+        3 => cfgr2::PREDIV::Div3,
+        4 => cfgr2::PREDIV::Div4,
+        5 => cfgr2::PREDIV::Div5,
+        6 => cfgr2::PREDIV::Div6,
+        7 => cfgr2::PREDIV::Div7,
+        8 => cfgr2::PREDIV::Div8,
+        9 => cfgr2::PREDIV::Div9,
+        10 => cfgr2::PREDIV::Div10,
+        11 => cfgr2::PREDIV::Div11,
+        12 => cfgr2::PREDIV::Div12,
+        13 => cfgr2::PREDIV::Div13,
+        14 => cfgr2::PREDIV::Div14,
+        15 => cfgr2::PREDIV::Div15,
+        16 => cfgr2::PREDIV::Div16,
         _ => crate::unreachable!(),
     }
 }
@@ -653,9 +653,9 @@ impl CFGR {
         crate::assert!(sysclk <= 72_000_000);
 
         let pll_src = if self.hse.is_some() {
-            cfgr::PLLSRC_A::HseDivPrediv
+            cfgr::PLLSRC::HseDivPrediv
         } else {
-            cfgr::PLLSRC_A::HsiDiv2
+            cfgr::PLLSRC::HsiDiv2
         };
 
         // Convert into register bit field types
@@ -720,9 +720,9 @@ impl CFGR {
         // Select hardware clock source of the PLL
         // TODO Check whether HSI_DIV2 could be useful
         let pll_src = if self.hse.is_some() {
-            cfgr::PLLSRC_A::HseDivPrediv
+            cfgr::PLLSRC::HseDivPrediv
         } else {
-            cfgr::PLLSRC_A::HseDivPrediv
+            cfgr::PLLSRC::HseDivPrediv
         };
 
         // Convert into register bit field types
@@ -748,7 +748,7 @@ impl CFGR {
     /// This function does only chose the PLL if needed, otherwise it will use the oscillator clock as system clock.
     ///
     /// Calls [`CFGR::calc_pll`] internally.
-    fn get_sysclk(&self) -> (u32, cfgr::SW_A, Option<PllConfig>) {
+    fn get_sysclk(&self) -> (u32, cfgr::SW, Option<PllConfig>) {
         // If a sysclk is given, check if the PLL has to be used,
         // else select the system clock source, which is either HSI or HSE.
         match (self.sysclk, self.hse) {
@@ -758,20 +758,20 @@ impl CFGR {
             // directly from neither the internal rc (8 Mhz)  nor the external
             // Oscillator (max 32 Mhz), without using the PLL.
             (Some(sysclk), Some(hse)) if sysclk == hse && self.pll_bypass => {
-                (hse, cfgr::SW_A::Hse, None)
+                (hse, cfgr::SW::Hse, None)
             }
             // No need to use the PLL
             (Some(sysclk), None) if sysclk == HSI.integer() && self.pll_bypass => {
-                (HSI.integer(), cfgr::SW_A::Hsi, None)
+                (HSI.integer(), cfgr::SW::Hsi, None)
             }
             (Some(sysclk), _) => {
                 let (sysclk, pll_config) = self.calc_pll(sysclk);
-                (sysclk, cfgr::SW_A::Pll, Some(pll_config))
+                (sysclk, cfgr::SW::Pll, Some(pll_config))
             }
             // Use HSE as system clock
-            (None, Some(hse)) => (hse, cfgr::SW_A::Hse, None),
+            (None, Some(hse)) => (hse, cfgr::SW::Hse, None),
             // Use HSI as system clock
-            (None, None) => (HSI.integer(), cfgr::SW_A::Hsi, None),
+            (None, None) => (HSI.integer(), cfgr::SW::Hsi, None),
         }
     }
 
@@ -791,17 +791,17 @@ impl CFGR {
 
         let (hpre_bits, hpre) =
             self.hclk
-                .map_or((cfgr::HPRE_A::Div1, 1), |hclk| match sysclk / hclk {
+                .map_or((cfgr::HPRE::Div1, 1), |hclk| match sysclk / hclk {
                     0 => crate::unreachable!(),
-                    1 => (cfgr::HPRE_A::Div1, 1),
-                    2 => (cfgr::HPRE_A::Div2, 2),
-                    3..=5 => (cfgr::HPRE_A::Div4, 4),
-                    6..=11 => (cfgr::HPRE_A::Div8, 8),
-                    12..=39 => (cfgr::HPRE_A::Div16, 16),
-                    40..=95 => (cfgr::HPRE_A::Div64, 64),
-                    96..=191 => (cfgr::HPRE_A::Div128, 128),
-                    192..=383 => (cfgr::HPRE_A::Div256, 256),
-                    _ => (cfgr::HPRE_A::Div512, 512),
+                    1 => (cfgr::HPRE::Div1, 1),
+                    2 => (cfgr::HPRE::Div2, 2),
+                    3..=5 => (cfgr::HPRE::Div4, 4),
+                    6..=11 => (cfgr::HPRE::Div8, 8),
+                    12..=39 => (cfgr::HPRE::Div16, 16),
+                    40..=95 => (cfgr::HPRE::Div64, 64),
+                    96..=191 => (cfgr::HPRE::Div128, 128),
+                    192..=383 => (cfgr::HPRE::Div256, 256),
+                    _ => (cfgr::HPRE::Div512, 512),
                 });
 
         let hclk: u32 = sysclk / hpre;
@@ -810,13 +810,13 @@ impl CFGR {
 
         let (mut ppre1_bits, mut ppre1) =
             self.pclk1
-                .map_or((cfgr::PPRE1_A::Div1, 1), |pclk1| match hclk / pclk1 {
+                .map_or((cfgr::PPRE1::Div1, 1), |pclk1| match hclk / pclk1 {
                     0 => crate::unreachable!(),
-                    1 => (cfgr::PPRE1_A::Div1, 1),
-                    2 => (cfgr::PPRE1_A::Div2, 2),
-                    3..=5 => (cfgr::PPRE1_A::Div4, 4),
-                    6..=11 => (cfgr::PPRE1_A::Div8, 8),
-                    _ => (cfgr::PPRE1_A::Div16, 16),
+                    1 => (cfgr::PPRE1::Div1, 1),
+                    2 => (cfgr::PPRE1::Div2, 2),
+                    3..=5 => (cfgr::PPRE1::Div4, 4),
+                    6..=11 => (cfgr::PPRE1::Div8, 8),
+                    _ => (cfgr::PPRE1::Div16, 16),
                 });
 
         let mut pclk1 = hclk / u32::from(ppre1);
@@ -826,7 +826,7 @@ impl CFGR {
         // As hclk highest value is 72.MHz()
         // dividing by 2 should always be sufficient
         if self.pclk1.is_none() && pclk1 > 36_000_000 {
-            ppre1_bits = cfgr::PPRE1_A::Div2;
+            ppre1_bits = cfgr::PPRE1::Div2;
             ppre1 = 2;
             pclk1 = hclk / u32::from(ppre1);
         }
@@ -835,13 +835,13 @@ impl CFGR {
 
         let (ppre2_bits, ppre2) =
             self.pclk2
-                .map_or((cfgr::PPRE2_A::Div1, 1), |pclk2| match hclk / pclk2 {
+                .map_or((cfgr::PPRE1::Div1, 1), |pclk2| match hclk / pclk2 {
                     0 => crate::unreachable!(),
-                    1 => (cfgr::PPRE2_A::Div1, 1),
-                    2 => (cfgr::PPRE2_A::Div2, 2),
-                    3..=5 => (cfgr::PPRE2_A::Div4, 4),
-                    6..=11 => (cfgr::PPRE2_A::Div8, 8),
-                    _ => (cfgr::PPRE2_A::Div16, 16),
+                    1 => (cfgr::PPRE1::Div1, 1),
+                    2 => (cfgr::PPRE1::Div2, 2),
+                    3..=5 => (cfgr::PPRE1::Div4, 4),
+                    6..=11 => (cfgr::PPRE1::Div8, 8),
+                    _ => (cfgr::PPRE1::Div16, 16),
                 });
 
         let pclk2 = hclk / u32::from(ppre2);
@@ -868,18 +868,18 @@ impl CFGR {
 
         // enable HSE and wait for it to be ready
         if self.hse.is_some() {
-            rcc.cr.modify(|_, w| {
+            rcc.cr().modify(|_, w| {
                 w.hsebyp().bit(self.hse_bypass);
                 w.csson().bit(self.css);
                 w.hseon().on()
             });
 
-            while rcc.cr.read().hserdy().is_not_ready() {}
+            while rcc.cr().read().hserdy().is_not_ready() {}
         }
 
         // enable PLL and wait for it to be ready
         if let Some(pll_config) = pll_config {
-            rcc.cfgr.modify(|_, w| {
+            rcc.cfgr().modify(|_, w| {
                 w.pllmul()
                     .variant(pll_config.mul)
                     .pllsrc()
@@ -887,16 +887,16 @@ impl CFGR {
             });
 
             if let Some(pll_div) = pll_config.div {
-                rcc.cfgr2.modify(|_, w| w.prediv().variant(pll_div));
+                rcc.cfgr2().modify(|_, w| w.prediv().variant(pll_div));
             };
 
-            rcc.cr.modify(|_, w| w.pllon().on());
+            rcc.cr().modify(|_, w| w.pllon().on());
 
-            while rcc.cr.read().pllrdy().is_not_ready() {}
+            while rcc.cr().read().pllrdy().is_not_ready() {}
         };
 
         // set prescalers and clock source
-        rcc.cfgr.modify(|_, w| {
+        rcc.cfgr().modify(|_, w| {
             usb_clocking::set_usbpre(w, usbpre);
 
             w.ppre2()
diff --git a/src/rtc.rs b/src/rtc.rs
index d6d41a97..c79e8709 100644
--- a/src/rtc.rs
+++ b/src/rtc.rs
@@ -64,9 +64,9 @@ impl Rtc {
         enable(bdcr);
         result.set_24h_fmt();
 
-        result.rtc.prer.modify(|_, w| {
-            w.prediv_s().bits(prediv_s);
-            w.prediv_a().bits(prediv_a)
+        result.rtc.prer().modify(|_, w| {
+            w.prediv_s().set(prediv_s);
+            w.prediv_a().set(prediv_a)
         });
 
         result
@@ -74,17 +74,17 @@ impl Rtc {
 
     /// Sets calendar clock to 24 hr format
     pub fn set_24h_fmt(&mut self) {
-        self.rtc.cr.modify(|_, w| w.fmt().set_bit());
+        self.rtc.cr().modify(|_, w| w.fmt().set_bit());
     }
     /// Sets calendar clock to 12 hr format
     pub fn set_12h_fmt(&mut self) {
-        self.rtc.cr.modify(|_, w| w.fmt().clear_bit());
+        self.rtc.cr().modify(|_, w| w.fmt().clear_bit());
     }
 
     /// Reads current hour format selection
     #[must_use]
     pub fn is_24h_fmt(&self) -> bool {
-        self.rtc.cr.read().fmt().bit()
+        self.rtc.cr().read().fmt().bit()
     }
 
     /// Get access to the underlying register block.
@@ -115,20 +115,20 @@ impl Rtc {
         F: FnMut(&mut RTC),
     {
         // Disable write protection
-        self.rtc.wpr.write(|w| w.key().bits(0xCA));
-        self.rtc.wpr.write(|w| w.key().bits(0x53));
+        self.rtc.wpr().write(|w| w.key().set(0xCA));
+        self.rtc.wpr().write(|w| w.key().set(0x53));
         // Enter init mode
-        let isr = self.rtc.isr.read();
+        let isr = self.rtc.isr().read();
         if isr.initf().bit_is_clear() {
-            self.rtc.isr.modify(|_, w| w.init().set_bit());
-            while self.rtc.isr.read().initf().bit_is_clear() {}
+            self.rtc.isr().modify(|_, w| w.init().set_bit());
+            while self.rtc.isr().read().initf().bit_is_clear() {}
         }
         // Invoke closure
         closure(&mut self.rtc);
         // Exit init mode
-        self.rtc.isr.modify(|_, w| w.init().clear_bit());
+        self.rtc.isr().modify(|_, w| w.init().clear_bit());
         // wait for last write to be done
-        while !self.rtc.isr.read().initf().bit_is_clear() {}
+        while !self.rtc.isr().read().initf().bit_is_clear() {}
     }
 }
 
@@ -147,22 +147,22 @@ impl DateTimeAccess for Rtc {
         let (minutes_tens, minutes_units) = bcd2_encode(date.minute())?;
         let (second_tens, second_units) = bcd2_encode(date.second())?;
 
-        self.rtc.dr.write(|w| {
-            w.dt().bits(day_tens);
-            w.du().bits(day_units);
+        self.rtc.dr().write(|w| {
+            w.dt().set(day_tens);
+            w.du().set(day_units);
             w.mt().bit(month_tens > 0);
-            w.mu().bits(month_units);
-            w.yt().bits(year_tens);
-            w.yu().bits(year_units)
+            w.mu().set(month_units);
+            w.yt().set(year_tens);
+            w.yu().set(year_units)
         });
 
-        self.rtc.tr.write(|w| {
-            w.ht().bits(hour_tens);
-            w.hu().bits(hour_units);
-            w.mnt().bits(minutes_tens);
-            w.mnu().bits(minutes_units);
-            w.st().bits(second_tens);
-            w.su().bits(second_units);
+        self.rtc.tr().write(|w| {
+            w.ht().set(hour_tens);
+            w.hu().set(hour_units);
+            w.mnt().set(minutes_tens);
+            w.mnu().set(minutes_units);
+            w.st().set(second_tens);
+            w.su().set(second_units);
             w.pm().clear_bit()
         });
 
@@ -196,13 +196,14 @@ impl Rtcc for Rtc {
         let (hour_tens, hour_units) = bcd2_encode(time.hour())?;
         let (minutes_tens, minutes_units) = bcd2_encode(time.minute())?;
         let (seconds_tens, seconds_units) = bcd2_encode(time.second())?;
-        self.rtc.tr.write(|w| {
-            w.ht().bits(hour_tens);
-            w.hu().bits(hour_units);
-            w.mnt().bits(minutes_tens);
-            w.mnu().bits(minutes_units);
-            w.st().bits(seconds_tens);
-            w.su().bits(seconds_units);
+
+        self.rtc.tr().write(|w| {
+            w.ht().set(hour_tens);
+            w.hu().set(hour_units);
+            w.mnt().set(minutes_tens);
+            w.mnu().set(minutes_units);
+            w.st().set(seconds_tens);
+            w.su().set(seconds_units);
             w.pm().clear_bit()
         });
 
@@ -215,8 +216,8 @@ impl Rtcc for Rtc {
         }
         let (seconds_tens, seconds_units) = bcd2_encode(u32::from(seconds))?;
         self.modify(|rtc| {
-            rtc.tr
-                .modify(|_, w| w.st().bits(seconds_tens).su().bits(seconds_units));
+            rtc.tr()
+                .modify(|_, w| w.st().set(seconds_tens).su().set(seconds_units));
         });
 
         Ok(())
@@ -228,8 +229,8 @@ impl Rtcc for Rtc {
         }
         let (minutes_tens, minutes_units) = bcd2_encode(u32::from(minutes))?;
         self.modify(|rtc| {
-            rtc.tr
-                .modify(|_, w| w.mnt().bits(minutes_tens).mnu().bits(minutes_units));
+            rtc.tr()
+                .modify(|_, w| w.mnt().set(minutes_tens).mnu().set(minutes_units));
         });
 
         Ok(())
@@ -243,8 +244,8 @@ impl Rtcc for Rtc {
         }
 
         self.rtc
-            .tr
-            .modify(|_, w| w.ht().bits(hour_tens).hu().bits(hour_units));
+            .tr()
+            .modify(|_, w| w.ht().set(hour_tens).hu().set(hour_units));
 
         Ok(())
     }
@@ -254,7 +255,9 @@ impl Rtcc for Rtc {
             return Err(Error::InvalidInputData);
         }
         // SAFETY: check above ensures, that the weekday number is in the valid range (0x01 - 0x07)
-        self.modify(|rtc| rtc.dr.modify(|_, w| unsafe { w.wdu().bits(weekday) }));
+        self.modify(|rtc| unsafe {
+            rtc.dr().modify(|_, w| w.wdu().bits(weekday));
+        });
 
         Ok(())
     }
@@ -265,8 +268,8 @@ impl Rtcc for Rtc {
         }
         let (day_tens, day_units) = bcd2_encode(u32::from(day))?;
         self.modify(|rtc| {
-            rtc.dr
-                .modify(|_, w| w.dt().bits(day_tens).du().bits(day_units));
+            rtc.dr()
+                .modify(|_, w| w.dt().set(day_tens).du().set(day_units));
         });
 
         Ok(())
@@ -278,8 +281,8 @@ impl Rtcc for Rtc {
         }
         let (month_tens, month_units) = bcd2_encode(u32::from(month))?;
         self.modify(|rtc| {
-            rtc.dr
-                .modify(|_, w| w.mt().bit(month_tens > 0).mu().bits(month_units));
+            rtc.dr()
+                .modify(|_, w| w.mt().bit(month_tens > 0).mu().set(month_units));
         });
 
         Ok(())
@@ -290,7 +293,10 @@ impl Rtcc for Rtc {
             return Err(Error::InvalidInputData);
         }
         let (year_tens, yu) = bcd2_encode(u32::from(year))?;
-        self.modify(|rtc| rtc.dr.modify(|_, w| w.yt().bits(year_tens).yu().bits(yu)));
+
+        self.modify(|rtc| {
+            rtc.dr().modify(|_, w| w.yt().set(year_tens).yu().set(yu));
+        });
 
         Ok(())
     }
@@ -303,32 +309,32 @@ impl Rtcc for Rtc {
         let (month_tens, month_units) = bcd2_encode(date.month())?;
         let (day_tens, day_units) = bcd2_encode(date.day())?;
 
-        self.rtc.dr.write(|w| {
-            w.dt().bits(day_tens);
-            w.du().bits(day_units);
+        self.rtc.dr().write(|w| {
+            w.dt().set(day_tens);
+            w.du().set(day_units);
             w.mt().bit(month_tens > 0);
-            w.mu().bits(month_units);
-            w.yt().bits(year_tens);
-            w.yu().bits(yu)
+            w.mu().set(month_units);
+            w.yt().set(year_tens);
+            w.yu().set(yu)
         });
 
         Ok(())
     }
 
     fn seconds(&mut self) -> Result<u8, Self::Error> {
-        let tr = self.rtc.tr.read();
+        let tr = self.rtc.tr().read();
         let seconds = bcd2_decode(tr.st().bits(), tr.su().bits());
         u8::try_from(seconds).map_err(|_| Error::InvalidRtcData)
     }
 
     fn minutes(&mut self) -> Result<u8, Self::Error> {
-        let tr = self.rtc.tr.read();
+        let tr = self.rtc.tr().read();
         let minutes = bcd2_decode(tr.mnt().bits(), tr.mnu().bits());
         u8::try_from(minutes).map_err(|_| Error::InvalidRtcData)
     }
 
     fn hours(&mut self) -> Result<Hours, Self::Error> {
-        let tr = self.rtc.tr.read();
+        let tr = self.rtc.tr().read();
         let hours = bcd2_decode(tr.ht().bits(), tr.hu().bits());
         let hours = u8::try_from(hours).map_err(|_| Error::InvalidRtcData)?;
         if self.is_24h_fmt() {
@@ -351,26 +357,26 @@ impl Rtcc for Rtc {
     }
 
     fn weekday(&mut self) -> Result<u8, Self::Error> {
-        let dr = self.rtc.dr.read();
+        let dr = self.rtc.dr().read();
         let weekday = bcd2_decode(dr.wdu().bits(), 0x00);
         u8::try_from(weekday).map_err(|_| Error::InvalidRtcData)
     }
 
     fn day(&mut self) -> Result<u8, Self::Error> {
-        let dr = self.rtc.dr.read();
+        let dr = self.rtc.dr().read();
         let day = bcd2_decode(dr.dt().bits(), dr.du().bits());
         u8::try_from(day).map_err(|_| Error::InvalidRtcData)
     }
 
     fn month(&mut self) -> Result<u8, Self::Error> {
-        let dr = self.rtc.dr.read();
+        let dr = self.rtc.dr().read();
         let month_tens = u8::from(dr.mt().bit());
         let month = bcd2_decode(month_tens, dr.mu().bits());
         u8::try_from(month).map_err(|_| Error::InvalidRtcData)
     }
 
     fn year(&mut self) -> Result<u16, Self::Error> {
-        let dr = self.rtc.dr.read();
+        let dr = self.rtc.dr().read();
         let year = bcd2_decode(dr.yt().bits(), dr.yu().bits());
         u16::try_from(year).map_err(|_| Error::InvalidRtcData)
     }
@@ -438,14 +444,14 @@ fn enable_lse(bdcr: &mut BDCR, bypass: bool) {
 fn unlock(apb1: &mut APB1, pwr: &mut PWR) {
     // Enable the backup interface by setting PWREN
     PWR::enable(apb1);
-    pwr.cr.modify(|_, w| {
+    pwr.cr().modify(|_, w| {
         w
             // Enable access to the backup registers
             .dbp()
             .set_bit()
     });
 
-    while pwr.cr.read().dbp().bit_is_clear() {}
+    while pwr.cr().read().dbp().bit_is_clear() {}
 }
 
 fn enable(bdcr: &mut BDCR) {
diff --git a/src/serial.rs b/src/serial.rs
index 7af493f4..a53a11dc 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -17,8 +17,8 @@ use crate::{
     gpio::{gpioa, gpiob, gpioc, AF7},
     hal::{blocking, serial, serial::Write},
     pac::{
-        rcc::cfgr3::USART1SW_A,
-        usart1::{cr1::M_A, cr1::PCE_A, cr1::PS_A, RegisterBlock},
+        rcc::cfgr3::USART1SW,
+        usart1::{cr1::M, cr1::PCE, cr1::PS, RegisterBlock},
         Interrupt, USART1, USART2, USART3,
     },
     rcc::{self, Clocks},
@@ -361,14 +361,14 @@ where
         Usart::reset(apb);
         // Disable USART because some configuration bits could only be written
         // in this state.
-        usart.cr1.modify(|_, w| w.ue().disabled());
+        usart.cr1().modify(|_, w| w.ue().disabled());
 
         let brr = Usart::clock(&clocks).integer() / config.baudrate.integer();
         crate::assert!(brr >= 16, "impossible baud rate");
-        usart.brr.write(|w| {
-            w.brr().bits(
+        usart.brr().write(|w| unsafe {
+            w.brr().set(
                 // SAFETY: safe because of assert before
-                unsafe { u16::try_from(brr).unwrap_unchecked() },
+                u16::try_from(brr).unwrap_unchecked(),
             )
         });
 
@@ -377,15 +377,15 @@ where
         // and partiy bits together so the actual amount depends on the parity
         // selection.
         let (m0, ps, pce) = match config.parity {
-            Parity::None => (M_A::Bit8, PS_A::Even, PCE_A::Disabled),
-            Parity::Even => (M_A::Bit9, PS_A::Even, PCE_A::Enabled),
-            Parity::Odd => (M_A::Bit9, PS_A::Odd, PCE_A::Enabled),
+            Parity::None => (M::Bit8, PS::Even, PCE::Disabled),
+            Parity::Even => (M::Bit9, PS::Even, PCE::Enabled),
+            Parity::Odd => (M::Bit9, PS::Odd, PCE::Enabled),
         };
 
         usart
-            .cr2
+            .cr2()
             .modify(|_, w| w.stop().variant(config.stopbits.into()));
-        usart.cr1.modify(|_, w| {
+        usart.cr1().modify(|_, w| {
             w.ps().variant(ps); // set parity mode
             w.pce().variant(pce); // enable parity checking/generation
             w.m().variant(m0); // set data bits
@@ -394,7 +394,7 @@ where
         });
 
         // Finally enable the configured UART.
-        usart.cr1.modify(|_, w| w.ue().enabled());
+        usart.cr1().modify(|_, w| w.ue().enabled());
 
         Self { usart, pins }
     }
@@ -415,7 +415,7 @@ where
     /// Releases the USART peripheral and associated pins
     pub fn free(self) -> (Usart, (Tx, Rx)) {
         self.usart
-            .cr1
+            .cr1()
             .modify(|_, w| w.ue().disabled().re().disabled().te().disabled());
         (self.usart, self.pins)
     }
@@ -440,11 +440,11 @@ where
     /// trait implementation.
     #[doc(alias = "RDR")]
     pub fn read_data_register(&self) -> Option<u8> {
-        if self.usart.isr.read().busy().bit_is_set() {
+        if self.usart.isr().read().busy().bit_is_set() {
             return None;
         }
         #[allow(clippy::cast_possible_truncation)]
-        Some(self.usart.rdr.read().rdr().bits() as u8)
+        Some(self.usart.rdr().read().rdr().bits() as u8)
     }
 
     /// Check if the USART peripheral is busy.
@@ -452,7 +452,7 @@ where
     /// This can be useful to block on to synchronize between peripheral and CPU
     /// because of the asynchronous nature of the peripheral.
     pub fn is_busy(&mut self) -> bool {
-        self.usart.isr.read().busy().bit_is_set()
+        self.usart.isr().read().busy().bit_is_set()
     }
 
     /// Obtain the associated interrupt number for the serial peripheral.
@@ -497,22 +497,24 @@ where
         let enable: Switch = enable.into();
         let enable: bool = enable.into();
         match event {
-            Event::TransmitDataRegisterEmtpy => self.usart.cr1.modify(|_, w| w.txeie().bit(enable)),
-            Event::CtsInterrupt => self.usart.cr3.modify(|_, w| w.ctsie().bit(enable)),
-            Event::TransmissionComplete => self.usart.cr1.modify(|_, w| w.tcie().bit(enable)),
+            Event::TransmitDataRegisterEmtpy => {
+                self.usart.cr1().modify(|_, w| w.txeie().bit(enable))
+            }
+            Event::CtsInterrupt => self.usart.cr3().modify(|_, w| w.ctsie().bit(enable)),
+            Event::TransmissionComplete => self.usart.cr1().modify(|_, w| w.tcie().bit(enable)),
             Event::ReceiveDataRegisterNotEmpty => {
-                self.usart.cr1.modify(|_, w| w.rxneie().bit(enable));
+                self.usart.cr1().modify(|_, w| w.rxneie().bit(enable))
             }
-            Event::ParityError => self.usart.cr1.modify(|_, w| w.peie().bit(enable)),
-            Event::LinBreak => self.usart.cr2.modify(|_, w| w.lbdie().bit(enable)),
+            Event::ParityError => self.usart.cr1().modify(|_, w| w.peie().bit(enable)),
+            Event::LinBreak => self.usart.cr2().modify(|_, w| w.lbdie().bit(enable)),
             Event::NoiseError | Event::OverrunError | Event::FramingError => {
-                self.usart.cr3.modify(|_, w| w.eie().bit(enable));
+                self.usart.cr3().modify(|_, w| w.eie().bit(enable))
             }
-            Event::Idle => self.usart.cr1.modify(|_, w| w.idleie().bit(enable)),
-            Event::CharacterMatch => self.usart.cr1.modify(|_, w| w.cmie().bit(enable)),
-            Event::ReceiverTimeout => self.usart.cr1.modify(|_, w| w.rtoie().bit(enable)),
-            // Event::EndOfBlock => self.usart.cr1.modify(|_, w| w.eobie().bit(enable)),
-            // Event::WakeupFromStopMode => self.usart.cr3.modify(|_, w| w.wufie().bit(enable)),
+            Event::Idle => self.usart.cr1().modify(|_, w| w.idleie().bit(enable)),
+            Event::CharacterMatch => self.usart.cr1().modify(|_, w| w.cmie().bit(enable)),
+            Event::ReceiverTimeout => self.usart.cr1().modify(|_, w| w.rtoie().bit(enable)),
+            // Event::EndOfBlock => self.usart.cr1().modify(|_, w| w.eobie().bit(enable)),
+            // Event::WakeupFromStopMode => self.usart.cr3().modify(|_, w| w.wufie().bit(enable)),
         };
     }
 
@@ -536,20 +538,20 @@ where
     #[inline]
     pub fn is_interrupt_configured(&self, event: Event) -> bool {
         match event {
-            Event::TransmitDataRegisterEmtpy => self.usart.cr1.read().txeie().is_enabled(),
-            Event::CtsInterrupt => self.usart.cr3.read().ctsie().is_enabled(),
-            Event::TransmissionComplete => self.usart.cr1.read().tcie().is_enabled(),
-            Event::ReceiveDataRegisterNotEmpty => self.usart.cr1.read().rxneie().is_enabled(),
-            Event::ParityError => self.usart.cr1.read().peie().is_enabled(),
-            Event::LinBreak => self.usart.cr2.read().lbdie().is_enabled(),
+            Event::TransmitDataRegisterEmtpy => self.usart.cr1().read().txeie().is_enabled(),
+            Event::CtsInterrupt => self.usart.cr3().read().ctsie().is_enabled(),
+            Event::TransmissionComplete => self.usart.cr1().read().tcie().is_enabled(),
+            Event::ReceiveDataRegisterNotEmpty => self.usart.cr1().read().rxneie().is_enabled(),
+            Event::ParityError => self.usart.cr1().read().peie().is_enabled(),
+            Event::LinBreak => self.usart.cr2().read().lbdie().is_enabled(),
             Event::NoiseError | Event::OverrunError | Event::FramingError => {
-                self.usart.cr3.read().eie().is_enabled()
+                self.usart.cr3().read().eie().is_enabled()
             }
-            Event::Idle => self.usart.cr1.read().idleie().is_enabled(),
-            Event::CharacterMatch => self.usart.cr1.read().cmie().is_enabled(),
-            Event::ReceiverTimeout => self.usart.cr1.read().rtoie().is_enabled(),
-            // Event::EndOfBlock => self.usart.cr1.read().eobie().is_enabled(),
-            // Event::WakeupFromStopMode => self.usart.cr3.read().wufie().is_enabled(),
+            Event::Idle => self.usart.cr1().read().idleie().is_enabled(),
+            Event::CharacterMatch => self.usart.cr1().read().cmie().is_enabled(),
+            Event::ReceiverTimeout => self.usart.cr1().read().rtoie().is_enabled(),
+            // Event::EndOfBlock => self.usart.cr1().read().eobie().is_enabled(),
+            // Event::WakeupFromStopMode => self.usart.cr3().read().wufie().is_enabled(),
         }
     }
 
@@ -572,7 +574,7 @@ where
     /// Check if an interrupt event happend.
     #[inline]
     pub fn is_event_triggered(&self, event: Event) -> bool {
-        let isr = self.usart.isr.read();
+        let isr = self.usart.isr().read();
         match event {
             Event::TransmitDataRegisterEmtpy => isr.txe().bit(),
             Event::CtsInterrupt => isr.ctsif().bit(),
@@ -619,7 +621,7 @@ where
     /// Clear the given interrupt event flag.
     #[inline]
     pub fn clear_event(&mut self, event: Event) {
-        self.usart.icr.write(|w| match event {
+        self.usart.icr().write(|w| match event {
             Event::CtsInterrupt => w.ctscf().clear(),
             Event::TransmissionComplete => w.tccf().clear(),
             Event::OverrunError => w.orecf().clear(),
@@ -634,7 +636,7 @@ where
             // Event::WakeupFromStopMode => w.wucf().clear(),
             Event::ReceiveDataRegisterNotEmpty => {
                 // Flush the register data queue, so that this even will not be thrown again.
-                self.usart.rqr.write(|w| w.rxfrq().set_bit());
+                self.usart.rqr().write(|w| w.rxfrq().set_bit());
                 w
             }
             // Do nothing with this event (only useful for Smartcard, which is not
@@ -647,7 +649,7 @@ where
     #[inline]
     pub fn clear_events(&mut self) {
         // SAFETY: This atomic write clears all flags and ignores the reserverd bit fields.
-        self.usart.icr.write(|w| unsafe { w.bits(u32::MAX) });
+        self.usart.icr().write(|w| unsafe { w.bits(u32::MAX) });
     }
 
     /// Enable or disable overrun detection
@@ -659,10 +661,10 @@ where
     #[doc(alias = "OVRDIS")]
     #[inline]
     pub fn detect_overrun(&mut self, enable: bool) {
-        let uart_enabled = self.usart.cr1.read().ue().bit();
-        self.usart.cr1.modify(|_, w| w.ue().disabled());
-        self.usart.cr3.modify(|_, w| w.ovrdis().bit(!enable));
-        self.usart.cr1.modify(|_, w| w.ue().bit(uart_enabled));
+        let uart_enabled = self.usart.cr1().read().ue().bit();
+        self.usart.cr1().modify(|_, w| w.ue().disabled());
+        self.usart.cr3().modify(|_, w| w.ovrdis().bit(!enable));
+        self.usart.cr1().modify(|_, w| w.ue().bit(uart_enabled));
     }
 
     /// Configuring the UART to match each received character,
@@ -673,15 +675,15 @@ where
     pub fn set_match_character(&mut self, char: u8) {
         // Note: This bit field can only be written when reception is disabled (RE = 0) or the
         // USART is disabled
-        let enabled = self.usart.cr1.read().ue().bit_is_set();
-        self.usart.cr1.modify(|_, w| w.ue().disabled());
-        self.usart.cr2.modify(|_, w| w.add().bits(char));
-        self.usart.cr1.modify(|_, w| w.ue().bit(enabled));
+        let enabled = self.usart.cr1().read().ue().bit_is_set();
+        self.usart.cr1().modify(|_, w| w.ue().disabled());
+        self.usart.cr2().modify(|_, w| w.add().set(char));
+        self.usart.cr1().modify(|_, w| w.ue().bit(enabled));
     }
 
     /// Read out the configured match character.
     pub fn match_character(&self) -> u8 {
-        self.usart.cr2.read().add().bits()
+        self.usart.cr2().read().add().bits()
     }
 }
 
@@ -707,10 +709,10 @@ where
     /// - Values higher than 24 bits are truncated to 24 bit max (`16_777_216`).
     pub fn set_receiver_timeout(&mut self, value: Option<u32>) {
         if let Some(value) = value {
-            self.usart.cr2.modify(|_, w| w.rtoen().enabled());
-            self.usart.rtor.modify(|_, w| w.rto().bits(value));
+            self.usart.cr2().modify(|_, w| w.rtoen().enabled());
+            self.usart.rtor().modify(|_, w| w.rto().set(value));
         } else {
-            self.usart.cr2.modify(|_, w| w.rtoen().disabled());
+            self.usart.cr2().modify(|_, w| w.rtoen().disabled());
         }
     }
 
@@ -721,8 +723,8 @@ where
     ///
     /// - If the value is None, the receiver timeout feature is disabled.
     pub fn receiver_timeout(&self) -> Option<u32> {
-        if self.usart.cr2.read().rtoen().is_enabled() {
-            Some(self.usart.rtor.read().rto().bits())
+        if self.usart.cr2().read().rtoen().is_enabled() {
+            Some(self.usart.rtor().read().rto().bits())
         } else {
             None
         }
@@ -735,19 +737,19 @@ fn eh_read<Usart>(usart: &mut Usart) -> nb::Result<u8, Error>
 where
     Usart: Instance,
 {
-    let isr = usart.isr.read();
+    let isr = usart.isr().read();
 
     Err(if isr.pe().bit_is_set() {
-        usart.icr.write(|w| w.pecf().clear());
+        usart.icr().write(|w| w.pecf().clear());
         nb::Error::Other(Error::Parity)
     } else if isr.fe().bit_is_set() {
-        usart.icr.write(|w| w.fecf().clear());
+        usart.icr().write(|w| w.fecf().clear());
         nb::Error::Other(Error::Framing)
     } else if isr.nf().bit_is_set() {
-        usart.icr.write(|w| w.ncf().clear());
+        usart.icr().write(|w| w.ncf().clear());
         nb::Error::Other(Error::Noise)
     } else if isr.ore().bit_is_set() {
-        usart.icr.write(|w| w.orecf().clear());
+        usart.icr().write(|w| w.orecf().clear());
         // Flush the receive data
         //
         // Imagine a case of an overrun, where 2 or more bytes have been received by the hardware
@@ -774,11 +776,11 @@ where
         // To mitigate this and have an implementation without these surprises flush the RDR
         // register. This leads to loosing a theoretically still receivable data byte! But at least
         // no cleanup is needed, after an overrun is called.
-        usart.rqr.write(|w| w.rxfrq().set_bit());
+        usart.rqr().write(|w| w.rxfrq().set_bit());
         nb::Error::Other(Error::Overrun)
     } else if isr.rxne().bit_is_set() {
         #[allow(clippy::cast_possible_truncation)]
-        return Ok(usart.rdr.read().bits() as u8);
+        return Ok(usart.rdr().read().bits() as u8);
     } else {
         nb::Error::WouldBlock
     })
@@ -823,7 +825,7 @@ where
     type Error = Infallible;
 
     fn flush(&mut self) -> nb::Result<(), Infallible> {
-        if self.usart.isr.read().tc().bit_is_set() {
+        if self.usart.isr().read().tc().bit_is_set() {
             Ok(())
         } else {
             Err(nb::Error::WouldBlock)
@@ -831,8 +833,8 @@ where
     }
 
     fn write(&mut self, byte: u8) -> nb::Result<(), Infallible> {
-        if self.usart.isr.read().txe().bit_is_set() {
-            self.usart.tdr.write(|w| w.tdr().bits(u16::from(byte)));
+        if self.usart.isr().read().txe().bit_is_set() {
+            self.usart.tdr().write(|w| w.tdr().set(u16::from(byte)));
             Ok(())
         } else {
             Err(nb::Error::WouldBlock)
@@ -869,10 +871,8 @@ where
     {
         // SAFETY: RDR is valid peripheral address, safe to dereference and pass to the DMA
         unsafe {
-            channel.set_peripheral_address(
-                core::ptr::addr_of!(self.usart.rdr) as u32,
-                dma::Increment::Disable,
-            );
+            channel
+                .set_peripheral_address(self.usart.rdr().as_ptr() as u32, dma::Increment::Disable);
         };
 
         dma::Transfer::start_write(buffer, channel, self)
@@ -887,10 +887,8 @@ where
     {
         // SAFETY: TDR is valid peripheral address, safe to dereference and pass to the DMA
         unsafe {
-            channel.set_peripheral_address(
-                core::ptr::addr_of!(self.usart.tdr) as u32,
-                dma::Increment::Disable,
-            );
+            channel
+                .set_peripheral_address(self.usart.tdr().as_ptr() as u32, dma::Increment::Disable);
         };
 
         dma::Transfer::start_read(buffer, channel, self)
@@ -903,13 +901,13 @@ where
 {
     fn enable_dma(&mut self) {
         self.usart
-            .cr3
+            .cr3()
             .modify(|_, w| w.dmar().enabled().dmat().enabled());
     }
 
     fn disable_dma(&mut self) {
         self.usart
-            .cr3
+            .cr3()
             .modify(|_, w| w.dmar().disabled().dmat().disabled());
     }
 }
@@ -1022,11 +1020,11 @@ macro_rules! usart_var_clock {
             impl Instance for $USARTX {
                 fn clock(clocks: &Clocks) -> Hertz {
                     // SAFETY: The read instruction of the RCC.cfgr3 register should be atomic
-                    match unsafe {(*RCC::ptr()).cfgr3.read().$usartXsw().variant()} {
-                        USART1SW_A::Pclk => <$USARTX as rcc::BusClock>::clock(clocks),
-                        USART1SW_A::Hsi => crate::rcc::HSI,
-                        USART1SW_A::Sysclk => clocks.sysclk(),
-                        USART1SW_A::Lse => crate::rcc::LSE,
+                    match unsafe {(*RCC::ptr()).cfgr3().read().$usartXsw().variant()} {
+                        USART1SW::Pclk => <$USARTX as rcc::BusClock>::clock(clocks),
+                        USART1SW::Hsi => crate::rcc::HSI,
+                        USART1SW::Sysclk => clocks.sysclk(),
+                        USART1SW::Lse => crate::rcc::LSE,
                     }
                 }
             }
@@ -1056,7 +1054,7 @@ cfg_if::cfg_if! {
         feature = "stm32f334x8",
     ))] {
         // USART1 is accessed through APB2,
-        // but USART1SW_A::PCLK will connect its phy to PCLK1.
+        // but USART1SW::PCLK will connect its phy to PCLK1.
         usart_var_clock!(1);
         // These are uart peripherals, where the only clock source
         // is the PCLK (peripheral clock).
diff --git a/src/serial/config.rs b/src/serial/config.rs
index 197170dd..22ba8684 100644
--- a/src/serial/config.rs
+++ b/src/serial/config.rs
@@ -1,11 +1,11 @@
 //! Types for configuring a serial interface.
 
-use crate::pac::usart1::cr2::STOP_A;
+use crate::pac::usart1::cr2::STOP;
 use crate::time::rate::{Baud, Extensions};
 
 /// Stop Bit configuration parameter for serial.
 ///
-/// Wrapper around [`STOP_A`]
+/// Wrapper around [`STOP`]
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum StopBits {
@@ -19,24 +19,24 @@ pub enum StopBits {
     Stop2,
 }
 
-impl From<StopBits> for STOP_A {
+impl From<StopBits> for STOP {
     fn from(stopbit: StopBits) -> Self {
         match stopbit {
-            StopBits::Stop0P5 => STOP_A::Stop0p5,
-            StopBits::Stop1 => STOP_A::Stop1,
-            StopBits::Stop1P5 => STOP_A::Stop1p5,
-            StopBits::Stop2 => STOP_A::Stop2,
+            StopBits::Stop0P5 => STOP::Stop0p5,
+            StopBits::Stop1 => STOP::Stop1,
+            StopBits::Stop1P5 => STOP::Stop1p5,
+            StopBits::Stop2 => STOP::Stop2,
         }
     }
 }
 
-impl From<STOP_A> for StopBits {
-    fn from(stopbit: STOP_A) -> Self {
+impl From<STOP> for StopBits {
+    fn from(stopbit: STOP) -> Self {
         match stopbit {
-            STOP_A::Stop0p5 => StopBits::Stop0P5,
-            STOP_A::Stop1 => StopBits::Stop1,
-            STOP_A::Stop1p5 => StopBits::Stop1P5,
-            STOP_A::Stop2 => StopBits::Stop2,
+            STOP::Stop0p5 => StopBits::Stop0P5,
+            STOP::Stop1 => StopBits::Stop1,
+            STOP::Stop1p5 => StopBits::Stop1P5,
+            STOP::Stop2 => StopBits::Stop2,
         }
     }
 }
diff --git a/src/spi.rs b/src/spi.rs
index bf2e2b08..9a960fe9 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -15,7 +15,7 @@ pub use crate::hal::spi::{Mode, Phase, Polarity};
 use crate::pac::SPI4;
 use crate::pac::{
     self, spi1,
-    spi1::cr2::{DS_A, FRXTH_A},
+    spi1::cr2::{DS, FRXTH},
     Interrupt, SPI1, SPI2, SPI3,
 };
 
@@ -24,7 +24,6 @@ use crate::{
     rcc::{self, Clocks},
     time::rate,
 };
-use num_traits::{AsPrimitive, PrimInt};
 
 /// SPI error
 #[derive(Copy, Clone, PartialEq, Eq, Debug)]
@@ -157,18 +156,18 @@ cfg_if::cfg_if! {
 pub trait Word {
     /// Returns the register configuration
     /// to set the word size
-    fn register_config() -> (FRXTH_A, DS_A);
+    fn register_config() -> (FRXTH, DS);
 }
 
 impl Word for u8 {
-    fn register_config() -> (FRXTH_A, DS_A) {
-        (FRXTH_A::Quarter, DS_A::EightBit)
+    fn register_config() -> (FRXTH, DS) {
+        (FRXTH::Quarter, DS::EightBit)
     }
 }
 
 impl Word for u16 {
-    fn register_config() -> (FRXTH_A, DS_A) {
-        (FRXTH_A::Half, DS_A::SixteenBit)
+    fn register_config() -> (FRXTH, DS) {
+        (FRXTH::Half, DS::SixteenBit)
     }
 }
 
@@ -219,7 +218,7 @@ impl<SPI, Sck, Miso, Mosi, WORD> Spi<SPI, (Sck, Miso, Mosi), WORD> {
         SPI::reset(apb);
 
         let (frxth, ds) = WORD::register_config();
-        spi.cr2.write(|w| {
+        spi.cr2().write(|w| {
             w.frxth().variant(frxth);
             w.ds().variant(ds);
             // Slave Select output disabled
@@ -236,7 +235,7 @@ impl<SPI, Sck, Miso, Mosi, WORD> Spi<SPI, (Sck, Miso, Mosi), WORD> {
         // SSI: set nss high = master mode
         // CRCEN: hardware CRC calculation disabled
         // BIDIMODE: 2 line unidirectional (full duplex)
-        spi.cr1.write(|w| {
+        spi.cr1().write(|w| {
             w.mstr().master();
 
             match config.mode.phase {
@@ -298,26 +297,26 @@ where
 {
     /// Change the baud rate of the SPI
     pub fn reclock(&mut self, freq: impl Into<rate::Generic<u32>>, clocks: Clocks) {
-        self.spi.cr1.modify(|_, w| w.spe().disabled());
+        self.spi.cr1().modify(|_, w| w.spe().disabled());
 
-        self.spi.cr1.modify(|_, w| {
+        self.spi.cr1().modify(|_, w| {
             w.br().variant(Self::compute_baud_rate(clocks, freq.into()));
             w.spe().enabled()
         });
     }
 
-    fn compute_baud_rate(clocks: Clocks, freq: rate::Generic<u32>) -> spi1::cr1::BR_A {
-        use spi1::cr1::BR_A;
+    fn compute_baud_rate(clocks: Clocks, freq: rate::Generic<u32>) -> spi1::cr1::BR {
+        use spi1::cr1::BR;
         match SPI::clock(&clocks).0 / (freq.integer() * *freq.scaling_factor()) {
             0 => crate::unreachable!(),
-            1..=2 => BR_A::Div2,
-            3..=5 => BR_A::Div4,
-            6..=11 => BR_A::Div8,
-            12..=23 => BR_A::Div16,
-            24..=39 => BR_A::Div32,
-            40..=95 => BR_A::Div64,
-            96..=191 => BR_A::Div128,
-            _ => BR_A::Div256,
+            1..=2 => BR::Div2,
+            3..=5 => BR::Div4,
+            6..=11 => BR::Div8,
+            12..=23 => BR::Div16,
+            24..=39 => BR::Div32,
+            40..=95 => BR::Div64,
+            96..=191 => BR::Div128,
+            _ => BR::Div256,
         }
     }
 
@@ -331,6 +330,34 @@ where
     }
 }
 
+/// A trait for types that can be used as SPI words
+///
+/// This is typically [u8] and [u16]
+pub trait SpiWord {
+    /// Read word from SPI data register
+    fn read(r: &impl Instance) -> Self;
+
+    /// Write word to SPI data register
+    fn write(r: &impl Instance, data: Self);
+}
+
+macro_rules! impl_spi_word {
+    ($t:ty, $dr:ident) => {
+        impl SpiWord for $t {
+            fn read(r: &impl Instance) -> Self {
+                r.$dr().read().bits()
+            }
+
+            fn write(r: &impl Instance, data: Self) {
+                r.$dr().write(|w| w.dr().set(data));
+            }
+        }
+    };
+}
+
+impl_spi_word!(u16, dr);
+impl_spi_word!(u8, dr8);
+
 impl<SPI, Sck, Miso, Mosi, Word> FullDuplex<Word> for Spi<SPI, (Sck, Miso, Mosi), Word>
 where
     SPI: Instance,
@@ -338,13 +365,12 @@ where
     // SckPin could technically be omitted, though not advisable.
     Miso: MisoPin<SPI>,
     Mosi: MosiPin<SPI>,
-    Word: PrimInt + Into<u32> + 'static,
-    u32: AsPrimitive<Word>,
+    Word: SpiWord,
 {
     type Error = Error;
 
     fn read(&mut self) -> nb::Result<Word, Error> {
-        let sr = self.spi.sr.read();
+        let sr = self.spi.sr().read();
 
         Err(if sr.ovr().is_overrun() {
             nb::Error::Other(Error::Overrun)
@@ -353,9 +379,8 @@ where
         } else if sr.crcerr().is_no_match() {
             nb::Error::Other(Error::Crc)
         } else if sr.rxne().is_not_empty() {
-            let read_ptr = core::ptr::addr_of!(self.spi.dr) as *const Word;
             // SAFETY: Read from register owned by this Spi struct
-            let value = unsafe { core::ptr::read_volatile(read_ptr) };
+            let value = SpiWord::read(&self.spi);
             return Ok(value);
         } else {
             nb::Error::WouldBlock
@@ -363,7 +388,7 @@ where
     }
 
     fn send(&mut self, word: Word) -> nb::Result<(), Error> {
-        let sr = self.spi.sr.read();
+        let sr = self.spi.sr().read();
 
         Err(if sr.ovr().is_overrun() {
             nb::Error::Other(Error::Overrun)
@@ -372,9 +397,8 @@ where
         } else if sr.crcerr().is_no_match() {
             nb::Error::Other(Error::Crc)
         } else if sr.txe().is_empty() {
-            let write_ptr = core::ptr::addr_of!(self.spi.dr) as *mut Word;
             // SAFETY: Write to register owned by this Spi struct
-            unsafe { core::ptr::write_volatile(write_ptr, word) };
+            SpiWord::write(&self.spi, word);
             return Ok(());
         } else {
             nb::Error::WouldBlock
@@ -387,8 +411,7 @@ where
     SPI: Instance,
     Miso: MisoPin<SPI>,
     Mosi: MosiPin<SPI>,
-    Word: PrimInt + Into<u32> + 'static,
-    u32: AsPrimitive<Word>,
+    Word: SpiWord,
 {
 }
 
@@ -397,8 +420,7 @@ where
     SPI: Instance,
     Miso: MisoPin<SPI>,
     Mosi: MosiPin<SPI>,
-    Word: PrimInt + Into<u32> + 'static,
-    u32: AsPrimitive<Word>,
+    Word: SpiWord,
 {
 }
 
diff --git a/src/syscfg.rs b/src/syscfg.rs
index f30928d5..18582cde 100644
--- a/src/syscfg.rs
+++ b/src/syscfg.rs
@@ -84,10 +84,10 @@ impl SysCfg {
         // without leveraging the safety of stm32f3 generated values.
         unsafe {
             match pin.index.index() {
-                0..=3 => crate::modify_at!(self.exticr1, BITWIDTH, index, extigpionr),
-                4..=7 => crate::modify_at!(self.exticr2, BITWIDTH, index, extigpionr),
-                8..=11 => crate::modify_at!(self.exticr3, BITWIDTH, index, extigpionr),
-                12..=15 => crate::modify_at!(self.exticr4, BITWIDTH, index, extigpionr),
+                0..=3 => crate::modify_at!(self.exticr1(), BITWIDTH, index, extigpionr),
+                4..=7 => crate::modify_at!(self.exticr2(), BITWIDTH, index, extigpionr),
+                8..=11 => crate::modify_at!(self.exticr3(), BITWIDTH, index, extigpionr),
+                12..=15 => crate::modify_at!(self.exticr4(), BITWIDTH, index, extigpionr),
                 _ => crate::unreachable!(),
             };
         }
diff --git a/src/timer.rs b/src/timer.rs
index 372b1bde..187876d4 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -392,57 +392,57 @@ macro_rules! timer {
         impl CommonRegisterBlock for crate::pac::$TIMX {
             #[inline]
             fn set_cr1_cen(&mut self, enable: bool) {
-                self.cr1.modify(|_, w| w.cen().bit(enable));
+                self.cr1().modify(|_, w| w.cen().bit(enable));
             }
 
             #[inline]
             fn is_cr1_cen_set(&mut self) -> bool {
-                self.cr1.read().cen().bit()
+                self.cr1().read().cen().bit()
             }
 
             #[inline]
             fn set_dier_uie(&mut self, enable: bool) {
-                self.dier.modify(|_, w| w.uie().bit(enable));
+                self.dier().modify(|_, w| w.uie().bit(enable));
             }
 
             #[inline]
             fn is_dier_uie_set(&self) -> bool {
-                self.dier.read().uie().bit()
+                self.dier().read().uie().bit()
             }
 
             #[inline]
             fn clear_sr_uief(&mut self) {
-                self.sr.modify(|_, w| w.uif().clear())
+                self.sr().modify(|_, w| w.uif().clear());
             }
 
             #[inline]
             fn clear_sr(&mut self) {
                 // SAFETY: This atomic write clears all flags and ignores the reserverd bit fields.
-                self.sr.write(|w| unsafe { w.bits(0) });
+                self.sr().write(|w| unsafe { w.bits(0) });
             }
 
             #[inline]
             fn is_sr_uief_set(&self) -> bool {
-                self.sr.read().uif().is_update_pending()
+                self.sr().read().uif().is_update_pending()
             }
 
             #[inline]
             fn set_egr_ug(&mut self) {
                 // NOTE(write): uses all bits in this register.
-                self.egr.write(|w| w.ug().update());
+                self.egr().write(|w| w.ug().update());
             }
 
             #[inline]
             fn set_psc(&mut self, psc: u16) {
                 // NOTE(write): uses all bits in this register.
-                self.psc.write(|w| w.psc().bits(psc));
+                self.psc().write(|w| w.psc().set(psc));
             }
 
             #[inline]
             fn set_arr(&mut self, arr: u16) {
                 #[allow(unused_unsafe)]
                 // SAFETY: For easier compatibility between timers write to whole register
-                self.arr.write(|w| unsafe { w.arr().bits(arr.into()) });
+                self.arr().write(|w| unsafe { w.arr().bits(arr.into()) });
             }
         }
     };
@@ -456,15 +456,15 @@ macro_rules! timer_var_clock {
                 #[inline]
                 fn clock(clocks: &Clocks) -> Hertz {
                     // SAFETY: Atomic read with no side-effects.
-                    match unsafe {(*RCC::ptr()).cfgr3.read().$timXsw().variant()} {
+                    match unsafe {(*RCC::ptr()).cfgr3().read().$timXsw().variant()} {
                         // PCLK2 is really the wrong name, as depending on the type of chip, it is
                         // pclk1 or pclk2. This distinction is however not made in stm32f3.
-                        crate::pac::rcc::cfgr3::TIM1SW_A::Pclk2 =>  {
+                        crate::pac::rcc::cfgr3::TIM1SW::Pclk2 =>  {
                             // Conditional mutliplier after APB prescaler is used.
                             // See RM0316 Fig 13.
                             <pac::$TIMX as rcc::BusTimerClock>::timer_clock(clocks)
                         }
-                        crate::pac::rcc::cfgr3::TIM1SW_A::Pll => {
+                        crate::pac::rcc::cfgr3::TIM1SW::Pll => {
                             if let Some(pllclk) = clocks.pllclk() {
                                 pllclk * 2
                             } else {
diff --git a/src/watchdog.rs b/src/watchdog.rs
index dd4fb807..85b78636 100644
--- a/src/watchdog.rs
+++ b/src/watchdog.rs
@@ -11,14 +11,14 @@ use embedded_time::fixed_point::FixedPoint;
 
 use crate::hal::watchdog::{Watchdog, WatchdogEnable};
 
-use crate::pac::{iwdg::pr::PR_A, DBGMCU, IWDG};
+use crate::pac::{iwdg::pr::PR, DBGMCU, IWDG};
 use crate::time::duration::Milliseconds;
 use crate::time::rate::Kilohertz;
 
 /// Frequency of the watchdog peripheral clock
 const LSI: Kilohertz = Kilohertz(40);
 // const MAX_PRESCALER: u8 = 0b0111;
-const MAX_PRESCALER: PR_A = PR_A::DivideBy256;
+const MAX_PRESCALER: PR = PR::DivideBy256;
 const MAX_RELOAD: u32 = 0x0FFF;
 
 /// Independent Watchdog Peripheral
@@ -41,15 +41,15 @@ impl fmt::Debug for IndependentWatchDog {
     }
 }
 
-fn into_division_value(psc: PR_A) -> u32 {
+fn into_division_value(psc: PR) -> u32 {
     match psc {
-        PR_A::DivideBy4 => 4,
-        PR_A::DivideBy8 => 8,
-        PR_A::DivideBy16 => 16,
-        PR_A::DivideBy32 => 32,
-        PR_A::DivideBy64 => 64,
-        PR_A::DivideBy128 => 128,
-        PR_A::DivideBy256 | PR_A::DivideBy256bis => 256,
+        PR::DivideBy4 => 4,
+        PR::DivideBy8 => 8,
+        PR::DivideBy16 => 16,
+        PR::DivideBy32 => 32,
+        PR::DivideBy64 => 64,
+        PR::DivideBy128 => 128,
+        PR::DivideBy256 => 256,
     }
 }
 
@@ -66,13 +66,13 @@ impl IndependentWatchDog {
 
     /// Set the watchdog to stop when a breakpoint is hit while debugging
     pub fn stop_on_debug(&self, dbg: &DBGMCU, stop: bool) {
-        dbg.apb1_fz.modify(|_, w| w.dbg_iwdg_stop().bit(stop));
+        dbg.apb1_fz().modify(|_, w| w.dbg_iwdg_stop().bit(stop));
     }
 
     /// Find and setup the next best prescaler and reload value for the selected timeout
     fn setup(&self, timeout: Milliseconds) {
         let mut reload: u32 =
-            timeout.integer().saturating_mul(LSI.integer()) / into_division_value(PR_A::DivideBy4);
+            timeout.integer().saturating_mul(LSI.integer()) / into_division_value(PR::DivideBy4);
 
         // Reload is potentially to high to be stored in the register.
         // The goal of this loop is to find the maximum possible reload value,
@@ -97,10 +97,10 @@ impl IndependentWatchDog {
             reload /= 2;
         }
 
-        self.access_registers(|iwdg| {
-            iwdg.pr.modify(|_, w| w.pr().bits(psc));
+        self.access_registers(|iwdg| unsafe {
+            iwdg.pr().modify(|_, w| w.pr().bits(psc));
             #[allow(clippy::cast_possible_truncation)]
-            iwdg.rlr.modify(|_, w| w.rl().bits(reload as u16));
+            iwdg.rlr().modify(|_, w| w.rl().set(reload as u16));
         });
 
         // NOTE: As the watchdog can not be stopped once started,
@@ -125,21 +125,27 @@ impl IndependentWatchDog {
     #[must_use]
     pub fn interval(&self) -> Milliseconds {
         // If the prescaler was changed wait until the change procedure is finished.
-        while self.iwdg.sr.read().pvu().bit() {}
+        while self.iwdg.sr().read().pvu().bit() {}
 
-        let psc = self.iwdg.pr.read().pr().variant();
-        let reload = self.iwdg.rlr.read().rl().bits();
+        let psc = self
+            .iwdg
+            .pr()
+            .read()
+            .pr()
+            .variant()
+            .unwrap_or(PR::DivideBy256);
+        let reload = self.iwdg.rlr().read().rl().bits();
 
         Milliseconds((into_division_value(psc) * u32::from(reload)) / LSI.integer())
     }
 
     fn access_registers<A, F: FnMut(&IWDG) -> A>(&self, mut f: F) -> A {
         // Unprotect write access to registers
-        self.iwdg.kr.write(|w| w.key().enable());
+        self.iwdg.kr().write(|w| w.key().unlock());
         let a = f(&self.iwdg);
 
         // Protect again
-        self.iwdg.kr.write(|w| w.key().reset());
+        self.iwdg.kr().write(|w| w.key().feed());
         a
     }
 }
@@ -150,12 +156,12 @@ impl WatchdogEnable for IndependentWatchDog {
     fn start<T: Into<Self::Time>>(&mut self, period: T) {
         self.setup(period.into());
 
-        self.iwdg.kr.write(|w| w.key().start());
+        self.iwdg.kr().write(|w| w.key().start());
     }
 }
 
 impl Watchdog for IndependentWatchDog {
     fn feed(&mut self) {
-        self.iwdg.kr.write(|w| w.key().reset());
+        self.iwdg.kr().write(|w| w.key().feed());
     }
 }
diff --git a/testsuite/tests/adc.rs b/testsuite/tests/adc.rs
index 87c17d51..35625d04 100644
--- a/testsuite/tests/adc.rs
+++ b/testsuite/tests/adc.rs
@@ -59,12 +59,12 @@ mod tests {
 
         // This is a workaround, so that the debugger will not disconnect imidiatly on asm::wfi();
         // https://github.com/probe-rs/probe-rs/issues/350#issuecomment-740550519
-        dp.DBGMCU.cr.modify(|_, w| {
+        dp.DBGMCU.cr().modify(|_, w| {
             w.dbg_sleep().set_bit();
             w.dbg_standby().set_bit();
             w.dbg_stop().set_bit()
         });
-        dp.RCC.ahbenr.modify(|_, w| w.dma1en().enabled());
+        dp.RCC.ahbenr().modify(|_, w| w.dma1en().enabled());
 
         let mut rcc = dp.RCC.constrain();
         let mut flash = dp.FLASH.constrain();
@@ -79,12 +79,12 @@ mod tests {
         // Slow down ADC
         unsafe {
             (*pac::RCC::ptr())
-                .cfgr2
-                .modify(|_, w| w.adc12pres().variant(pac::rcc::cfgr2::ADC12PRES_A::Div64))
+                .cfgr2()
+                .modify(|_, w| w.adc12pres().variant(pac::rcc::cfgr2::ADC12PRES::Div64))
         };
         dp.ADC1_2
-            .ccr
-            .modify(|_, w| w.ckmode().variant(pac::adc1_2::ccr::CKMODE_A::Asynchronous));
+            .ccr()
+            .modify(|_, w| w.ckmode().variant(pac::adc1_2::ccr::CKMODE::Asynchronous));
         let mut common_adc = CommonAdc::new(dp.ADC1_2, &clocks, &mut rcc.ahb);
 
         defmt::info!(
@@ -393,9 +393,9 @@ fn ADC1_2() {
     // SAFETY: Mutable access to the ADC1_2 peripheral, while knowing that
     // no-one can pre-empt the interrupt.
     let (eos, eoc) = unsafe {
-        let isr = &(*pac::ADC1::ptr()).isr.read();
+        let isr = &(*pac::ADC1::ptr()).isr().read();
         (*pac::ADC1::ptr())
-            .isr
+            .isr()
             .modify(|_, w| w.eos().clear().eoc().clear());
         (isr.eos(), isr.eoc())
     };