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stm32c071.mmap
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stm32c071.mmap
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0x40000000 A PERIPHERAL TIM2
0x40000000 B REGISTER CR1 (rw): TIM2 control register 1
0x40000000 C FIELD 00w01 CEN (rw): Counter enable
0x40000000 C FIELD 01w01 UDIS (rw): Update disable
0x40000000 C FIELD 02w01 URS (rw): Update request source
0x40000000 C FIELD 03w01 OPM (rw): One-pulse mode
0x40000000 C FIELD 04w01 DIR (rw): Direction
0x40000000 C FIELD 05w02 CMS (rw): Center-aligned mode selection
0x40000000 C FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40000000 C FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),
0x40000000 C FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40000004 B REGISTER CR2 (rw): TIM2 control register 2
0x40000004 C FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40000004 C FIELD 04w03 MMS (rw): Master mode selection
0x40000004 C FIELD 07w01 TI1S (rw): TI1 selection
0x40000008 B REGISTER SMCR (rw): TIM2 slave mode control register
0x40000008 C FIELD 00w03 SMS1 (rw): SMS[2:0]: Slave mode selection
0x40000008 C FIELD 03w01 OCCS (rw): OCREF clear selection
0x40000008 C FIELD 04w03 TS1 (rw): TS[2:0]: Trigger selection
0x40000008 C FIELD 07w01 MSM (rw): Master/Slave mode
0x40000008 C FIELD 08w04 ETF (rw): External trigger filter
0x40000008 C FIELD 12w02 ETPS (rw): External trigger prescaler
0x40000008 C FIELD 14w01 ECE (rw): External clock enable
0x40000008 C FIELD 15w01 ETP (rw): External trigger polarity
0x40000008 C FIELD 16w01 SMS2 (rw): SMS[3]
0x40000008 C FIELD 20w02 TS2 (rw): TS[4:3]
0x4000000C B REGISTER DIER (rw): TIM2 DMA/Interrupt enable register
0x4000000C C FIELD 00w01 UIE (rw): Update interrupt enable
0x4000000C C FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4000000C C FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x4000000C C FIELD 03w01 CC3IE (rw): Capture/Compare 3 interrupt enable
0x4000000C C FIELD 04w01 CC4IE (rw): Capture/Compare 4 interrupt enable
0x4000000C C FIELD 06w01 TIE (rw): Trigger interrupt enable
0x4000000C C FIELD 08w01 UDE (rw): Update DMA request enable
0x4000000C C FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x4000000C C FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x4000000C C FIELD 11w01 CC3DE (rw): Capture/Compare 3 DMA request enable
0x4000000C C FIELD 12w01 CC4DE (rw): Capture/Compare 4 DMA request enable
0x4000000C C FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40000010 B REGISTER SR (rw): TIM2 status register
0x40000010 C FIELD 00w01 UIF (rw): Update interrupt flag
0x40000010 C FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag
0x40000010 C FIELD 02w01 CC2IF (rw): Capture/Compare 2 interrupt flag
0x40000010 C FIELD 03w01 CC3IF (rw): Capture/Compare 3 interrupt flag
0x40000010 C FIELD 04w01 CC4IF (rw): Capture/Compare 4 interrupt flag
0x40000010 C FIELD 06w01 TIF (rw): Trigger interrupt flag
0x40000010 C FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag
0x40000010 C FIELD 10w01 CC2OF (rw): Capture/compare 2 overcapture flag
0x40000010 C FIELD 11w01 CC3OF (rw): Capture/Compare 3 overcapture flag
0x40000010 C FIELD 12w01 CC4OF (rw): Capture/Compare 4 overcapture flag
0x40000014 B REGISTER EGR (wo): TIM2 event generation register
0x40000014 C FIELD 00w01 UG (wo): Update generation
0x40000014 C FIELD 01w01 CC1G (wo): Capture/compare 1 generation
0x40000014 C FIELD 02w01 CC2G (wo): Capture/compare 2 generation
0x40000014 C FIELD 03w01 CC3G (wo): Capture/compare 3 generation
0x40000014 C FIELD 04w01 CC4G (wo): Capture/compare 4 generation
0x40000014 C FIELD 06w01 TG (wo): Trigger generation
0x40000018 B REGISTER CCMR1_Input (rw): TIM2 capture/compare mode register 1
0x40000018 B REGISTER CCMR1_Output (rw):
0x40000018 C FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40000018 C FIELD 00w02 CC1S (rw): Capture/Compare 1 selection
0x40000018 C FIELD 02w01 OC1FE (rw): Output compare 1 fast enable
0x40000018 C FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler
0x40000018 C FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40000018 C FIELD 04w03 OC1M (rw): OC1M[2:0]: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
0x40000018 C FIELD 04w04 IC1F (rw): Input capture 1 filter
0x40000018 C FIELD 07w01 OC1CE (rw): Output compare 1 clear enable
0x40000018 C FIELD 08w02 CC2S (rw): Capture/Compare 2 selection
0x40000018 C FIELD 08w02 CC2S (rw): Capture/compare 2 selection
0x40000018 C FIELD 10w01 OC2FE (rw): Output compare 2 fast enable
0x40000018 C FIELD 10w02 IC2PSC (rw): Input capture 2 prescaler
0x40000018 C FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40000018 C FIELD 12w03 OC2M (rw): OC2M[2:0]: Output compare 2 mode
0x40000018 C FIELD 12w04 IC2F (rw): Input capture 2 filter
0x40000018 C FIELD 15w01 OC2CE (rw): Output compare 2 clear enable
0x40000018 C FIELD 16w01 OC1M_3 (rw): OC1M[3]
0x40000018 C FIELD 24w01 OC2M_3 (rw): OC2M[3]
0x4000001C B REGISTER CCMR2_Input (rw): TIM2 capture/compare mode register 2
0x4000001C B REGISTER CCMR2_Output (rw):
0x4000001C C FIELD 00w02 CC3S (rw): Capture/Compare 3 selection
0x4000001C C FIELD 00w02 CC3S (rw): Capture/Compare 3 selection
0x4000001C C FIELD 02w01 OC3FE (rw): Output compare 3 fast enable
0x4000001C C FIELD 02w02 IC3PSC (rw): Input capture 3 prescaler
0x4000001C C FIELD 03w01 OC3PE (rw): Output compare 3 preload enable
0x4000001C C FIELD 04w03 OC3M (rw): OC3M[2:0]: Output compare 3 mode
0x4000001C C FIELD 04w04 IC3F (rw): Input capture 3 filter
0x4000001C C FIELD 07w01 OC3CE (rw): Output compare 3 clear enable
0x4000001C C FIELD 08w02 CC4S (rw): Capture/Compare 4 selection
0x4000001C C FIELD 08w02 CC4S (rw): Capture/Compare 4 selection
0x4000001C C FIELD 10w01 OC4FE (rw): Output compare 4 fast enable
0x4000001C C FIELD 10w02 IC4PSC (rw): Input capture 4 prescaler
0x4000001C C FIELD 11w01 OC4PE (rw): Output compare 4 preload enable
0x4000001C C FIELD 12w03 OC4M (rw): OC4M[2:0]: Output compare 4 mode
0x4000001C C FIELD 12w04 IC4F (rw): Input capture 4 filter
0x4000001C C FIELD 15w01 OC4CE (rw): Output compare 4 clear enable
0x4000001C C FIELD 16w01 OC3M_3 (rw): OC3M[3]
0x4000001C C FIELD 24w01 OC4M_3 (rw): OC4M[3]
0x40000020 B REGISTER CCER (rw): TIM2 capture/compare enable register
0x40000020 C FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable.
0x40000020 C FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity.
0x40000020 C FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity.
0x40000020 C FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable.
0x40000020 C FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity.
0x40000020 C FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity.
0x40000020 C FIELD 08w01 CC3E (rw): Capture/Compare 3 output enable.
0x40000020 C FIELD 09w01 CC3P (rw): Capture/Compare 3 output Polarity.
0x40000020 C FIELD 11w01 CC3NP (rw): Capture/Compare 3 output Polarity.
0x40000020 C FIELD 12w01 CC4E (rw): Capture/Compare 4 output enable.
0x40000020 C FIELD 13w01 CC4P (rw): Capture/Compare 4 output Polarity.
0x40000020 C FIELD 15w01 CC4NP (rw): Capture/Compare 4 output Polarity.
0x40000024 B REGISTER CNT (rw): TIM2 counter
0x40000024 B REGISTER CNT_remap (rw):
0x40000024 C FIELD 00w31 CNT (rw): Least significant part of counter value
0x40000024 C FIELD 00w32 CNT (rw): Least significant part of counter value
0x40000024 C FIELD 31w01 UIFCPY (rw): UIF Copy
0x40000028 B REGISTER PSC (rw): TIM2 prescaler
0x40000028 C FIELD 00w16 PSC (rw): Prescaler value
0x4000002C B REGISTER ARR (rw): TIM2 auto-reload register
0x4000002C C FIELD 00w32 ARR (rw): Low Auto-reload value
0x40000034 B REGISTER CCR1 (rw): TIM2 capture/compare register 1
0x40000034 C FIELD 00w32 CCR1 (rw): Low Capture/Compare 1 value
0x40000038 B REGISTER CCR2 (rw): TIM2 capture/compare register 2
0x40000038 C FIELD 00w32 CCR2 (rw): Low Capture/Compare 2 value
0x4000003C B REGISTER CCR3 (rw): TIM2 capture/compare register 3
0x4000003C C FIELD 00w32 CCR3 (rw): Low Capture/Compare value
0x40000040 B REGISTER CCR4 (rw): TIM2 capture/compare register 4
0x40000040 C FIELD 00w32 CCR4 (rw): Low Capture/Compare value
0x40000048 B REGISTER DCR (rw): TIM2 DMA control register
0x40000048 C FIELD 00w05 DBA (rw): DMA base address
0x40000048 C FIELD 08w05 DBL (rw): DMA burst length
0x4000004C B REGISTER DMAR (rw): TIM2 DMA address for full transfer
0x4000004C C FIELD 00w16 DMAB (rw): DMA register for burst accesses
0x40000060 B REGISTER AF1 (rw): TIM2 alternate function option register 1
0x40000060 C FIELD 14w04 ETRSEL (rw): ETR source selection
0x40000068 B REGISTER TISEL (rw): TIM2 timer input selection register
0x40000068 C FIELD 00w04 TI1SEL (rw): TI1[0] to TI1[15] input selection
0x40000068 C FIELD 08w04 TI2SEL (rw): TI2[0] to TI2[15] input selection
0x40000068 C FIELD 16w04 TI3SEL (rw): TI3[0] to TI3[15] input selection
0x40000400 A PERIPHERAL TIM3
0x40000400 B REGISTER CR1 (rw): TIM3 control register 1
0x40000400 C FIELD 00w01 CEN (rw): Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs.
0x40000400 C FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.
0x40000400 C FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller
0x40000400 C FIELD 03w01 OPM (rw): One-pulse mode
0x40000400 C FIELD 04w01 DIR (rw): Direction Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode.
0x40000400 C FIELD 05w02 CMS (rw): Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1)
0x40000400 C FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40000400 C FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx),
0x40000400 C FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x40000404 B REGISTER CR2 (rw): TIM3 control register 2
0x40000404 C FIELD 03w01 CCDS (rw): Capture/compare DMA selection
0x40000404 C FIELD 04w03 MMS (rw): Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.
0x40000404 C FIELD 07w01 TI1S (rw): TI1 selection
0x40000408 B REGISTER SMCR (rw): TIM3 slave mode control register
0x40000408 C FIELD 00w03 SMS1 (rw): SMS[2:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
0x40000408 C FIELD 03w01 OCCS (rw): OCREF clear selection This bit is used to select the OCREF clear source
0x40000408 C FIELD 04w03 TS1 (rw): TS[2:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 77: TIM3 internal trigger connection on page 478 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
0x40000408 C FIELD 07w01 MSM (rw): Master/Slave mode
0x40000408 C FIELD 08w04 ETF (rw): External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0x40000408 C FIELD 12w02 ETPS (rw): External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
0x40000408 C FIELD 14w01 ECE (rw): External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). Note: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF.
0x40000408 C FIELD 15w01 ETP (rw): External trigger polarity This bit selects whether ETR or ETR is used for trigger operations
0x40000408 C FIELD 16w01 SMS2 (rw): SMS[3]
0x40000408 C FIELD 20w02 TS2 (rw): TS[4:3]
0x4000040C B REGISTER DIER (rw): TIM3 DMA/Interrupt enable register
0x4000040C C FIELD 00w01 UIE (rw): Update interrupt enable
0x4000040C C FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x4000040C C FIELD 02w01 CC2IE (rw): Capture/Compare 2 interrupt enable
0x4000040C C FIELD 03w01 CC3IE (rw): Capture/Compare 3 interrupt enable
0x4000040C C FIELD 04w01 CC4IE (rw): Capture/Compare 4 interrupt enable
0x4000040C C FIELD 06w01 TIE (rw): Trigger interrupt enable
0x4000040C C FIELD 08w01 UDE (rw): Update DMA request enable
0x4000040C C FIELD 09w01 CC1DE (rw): Capture/Compare 1 DMA request enable
0x4000040C C FIELD 10w01 CC2DE (rw): Capture/Compare 2 DMA request enable
0x4000040C C FIELD 11w01 CC3DE (rw): Capture/Compare 3 DMA request enable
0x4000040C C FIELD 12w01 CC4DE (rw): Capture/Compare 4 DMA request enable
0x4000040C C FIELD 14w01 TDE (rw): Trigger DMA request enable
0x40000410 B REGISTER SR (rw): TIM3 status register
0x40000410 C FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register.
0x40000410 C FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
0x40000410 C FIELD 02w01 CC2IF (rw): Capture/Compare 2 interrupt flag Refer to CC1IF description
0x40000410 C FIELD 03w01 CC3IF (rw): Capture/Compare 3 interrupt flag Refer to CC1IF description
0x40000410 C FIELD 04w01 CC4IF (rw): Capture/Compare 4 interrupt flag Refer to CC1IF description
0x40000410 C FIELD 06w01 TIF (rw): Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
0x40000410 C FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0 .
0x40000410 C FIELD 10w01 CC2OF (rw): Capture/compare 2 overcapture flag refer to CC1OF description
0x40000410 C FIELD 11w01 CC3OF (rw): Capture/Compare 3 overcapture flag refer to CC1OF description
0x40000410 C FIELD 12w01 CC4OF (rw): Capture/Compare 4 overcapture flag refer to CC1OF description
0x40000414 B REGISTER EGR (wo): TIM3 event generation register
0x40000414 C FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40000414 C FIELD 01w01 CC1G (wo): Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
0x40000414 C FIELD 02w01 CC2G (wo): Capture/compare 2 generation Refer to CC1G description
0x40000414 C FIELD 03w01 CC3G (wo): Capture/compare 3 generation Refer to CC1G description
0x40000414 C FIELD 04w01 CC4G (wo): Capture/compare 4 generation Refer to CC1G description
0x40000414 C FIELD 06w01 TG (wo): Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
0x40000418 B REGISTER CCMR1_Input (rw): TIM3 capture/compare mode register 1
0x40000418 B REGISTER CCMR1_Output (rw): TIM3 capture/compare mode register 1
0x40000418 C FIELD 00w02 CC1S (rw): Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0x40000418 C FIELD 00w02 CC1S (rw): Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0x40000418 C FIELD 02w01 OC1FE (rw): Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
0x40000418 C FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).
0x40000418 C FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40000418 C FIELD 04w03 OC1M (rw): OC1M[2:0]: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
0x40000418 C FIELD 04w04 IC1F (rw): Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0x40000418 C FIELD 07w01 OC1CE (rw): Output compare 1 clear enable
0x40000418 C FIELD 08w02 CC2S (rw): Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
0x40000418 C FIELD 08w02 CC2S (rw): Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
0x40000418 C FIELD 10w01 OC2FE (rw): Output compare 2 fast enable
0x40000418 C FIELD 10w02 IC2PSC (rw): Input capture 2 prescaler
0x40000418 C FIELD 11w01 OC2PE (rw): Output compare 2 preload enable
0x40000418 C FIELD 12w03 OC2M (rw): OC2M[2:0]: Output compare 2 mode refer to OC1M description on bits 6:4
0x40000418 C FIELD 12w04 IC2F (rw): Input capture 2 filter
0x40000418 C FIELD 15w01 OC2CE (rw): Output compare 2 clear enable
0x40000418 C FIELD 16w01 OC1M_3 (rw): OC1M[3]
0x40000418 C FIELD 24w01 OC2M_3 (rw): OC2M[3]
0x4000041C B REGISTER CCMR2_Input (rw): TIM3 capture/compare mode register 2
0x4000041C B REGISTER CCMR2_Output (rw): TIM3 capture/compare mode register 2
0x4000041C C FIELD 00w02 CC3S (rw): Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
0x4000041C C FIELD 00w02 CC3S (rw): Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
0x4000041C C FIELD 02w01 OC3FE (rw): Output compare 3 fast enable
0x4000041C C FIELD 02w02 IC3PSC (rw): Input capture 3 prescaler
0x4000041C C FIELD 03w01 OC3PE (rw): Output compare 3 preload enable
0x4000041C C FIELD 04w03 OC3M (rw): OC3M[2:0]: Output compare 3 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register)
0x4000041C C FIELD 04w04 IC3F (rw): Input capture 3 filter
0x4000041C C FIELD 07w01 OC3CE (rw): Output compare 3 clear enable
0x4000041C C FIELD 08w02 CC4S (rw): Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
0x4000041C C FIELD 08w02 CC4S (rw): Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
0x4000041C C FIELD 10w01 OC4FE (rw): Output compare 4 fast enable
0x4000041C C FIELD 10w02 IC4PSC (rw): Input capture 4 prescaler
0x4000041C C FIELD 11w01 OC4PE (rw): Output compare 4 preload enable
0x4000041C C FIELD 12w03 OC4M (rw): OC4M[2:0]: Output compare 4 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register)
0x4000041C C FIELD 12w04 IC4F (rw): Input capture 4 filter
0x4000041C C FIELD 15w01 OC4CE (rw): Output compare 4 clear enable
0x4000041C C FIELD 16w01 OC3M_3 (rw): OC3M[3]
0x4000041C C FIELD 24w01 OC4M_3 (rw): OC4M[3]
0x40000420 B REGISTER CCER (rw): TIM3 capture/compare enable register
0x40000420 C FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable.
0x40000420 C FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used.
0x40000420 C FIELD 03w01 CC1NP (rw): Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description.
0x40000420 C FIELD 04w01 CC2E (rw): Capture/Compare 2 output enable. Refer to CC1E description
0x40000420 C FIELD 05w01 CC2P (rw): Capture/Compare 2 output Polarity. refer to CC1P description
0x40000420 C FIELD 07w01 CC2NP (rw): Capture/Compare 2 output Polarity. Refer to CC1NP description
0x40000420 C FIELD 08w01 CC3E (rw): Capture/Compare 3 output enable. Refer to CC1E description
0x40000420 C FIELD 09w01 CC3P (rw): Capture/Compare 3 output Polarity. Refer to CC1P description
0x40000420 C FIELD 11w01 CC3NP (rw): Capture/Compare 3 output Polarity. Refer to CC1NP description
0x40000420 C FIELD 12w01 CC4E (rw): Capture/Compare 4 output enable. refer to CC1E description
0x40000420 C FIELD 13w01 CC4P (rw): Capture/Compare 4 output Polarity. Refer to CC1P description
0x40000420 C FIELD 15w01 CC4NP (rw): Capture/Compare 4 output Polarity. Refer to CC1NP description
0x40000424 B REGISTER CNT (rw): TIM3 counter
0x40000424 B REGISTER CNT_remap (rw): TIM3 counter
0x40000424 C FIELD 00w31 CNT (rw): counter value
0x40000424 C FIELD 00w32 CNT (rw): counter value
0x40000424 C FIELD 31w01 UIFCPY (rw): UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register
0x40000428 B REGISTER PSC (rw): TIM3 prescaler
0x40000428 C FIELD 00w16 PSC (rw): Prescaler value The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ).
0x4000042C B REGISTER ARR (rw): TIM3 auto-reload register
0x4000042C C FIELD 00w32 ARR (rw): Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 18.3.1: Time-base unit on page 429 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40000434 B REGISTER CCR1 (rw): TIM3 capture/compare register 1
0x40000434 C FIELD 00w32 CCR1 (rw): Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed.
0x40000438 B REGISTER CCR2 (rw): TIM3 capture/compare register 2
0x40000438 C FIELD 00w32 CCR2 (rw): Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed.
0x4000043C B REGISTER CCR3 (rw): TIM3 capture/compare register 3
0x4000043C C FIELD 00w32 CCR3 (rw): Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed.
0x40000440 B REGISTER CCR4 (rw): TIM3 capture/compare register 4
0x40000440 C FIELD 00w32 CCR4 (rw): Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed.
0x40000448 B REGISTER DCR (rw): TIM3 DMA control register
0x40000448 C FIELD 00w05 DBA (rw): DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.
0x40000448 C FIELD 08w05 DBL (rw): DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ...
0x4000044C B REGISTER DMAR (rw): TIM3 DMA address for full transfer
0x4000044C C FIELD 00w16 DMAB (rw): DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
0x40000460 B REGISTER AF1 (rw): TIM3 alternate function option register 1
0x40000460 C FIELD 14w04 ETRSEL (rw): ETR source selection These bits select the ETR input source. Others: Reserved
0x40000468 B REGISTER TISEL (rw): TIM3 timer input selection register
0x40000468 C FIELD 00w04 TI1SEL (rw): TI1[0] to TI1[15] input selection These bits select the TI1[0] to TI1[15] input source. Others: Reserved
0x40000468 C FIELD 08w04 TI2SEL (rw): TI2[0] to TI2[15] input selection These bits select the TI2[0] to TI2[15] input source. Others: Reserved
0x40000468 C FIELD 16w04 TI3SEL (rw): TI3[0] to TI3[15] input selection These bits select the TI3[0] to TI3[15] input source. Others: Reserved
0x40002000 A PERIPHERAL TIM14
0x40002000 B REGISTER CR1 (rw): TIM14 control register 1
0x40002000 C FIELD 00w01 CEN (rw): Counter enable Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
0x40002000 C FIELD 01w01 UDIS (rw): Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values.
0x40002000 C FIELD 02w01 URS (rw): Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit
0x40002000 C FIELD 03w01 OPM (rw): One-pulse mode
0x40002000 C FIELD 07w01 ARPE (rw): Auto-reload preload enable
0x40002000 C FIELD 08w02 CKD (rw): Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx),
0x40002000 C FIELD 11w01 UIFREMAP (rw): UIF status bit remapping
0x4000200C B REGISTER DIER (rw): TIM14 Interrupt enable register
0x4000200C C FIELD 00w01 UIE (rw): Update interrupt enable
0x4000200C C FIELD 01w01 CC1IE (rw): Capture/Compare 1 interrupt enable
0x40002010 B REGISTER SR (rw): TIM14 status register
0x40002010 C FIELD 00w01 UIF (rw): Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS= 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS= 0 and UDIS= 0 in the TIMx_CR1 register.
0x40002010 C FIELD 01w01 CC1IF (rw): Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
0x40002010 C FIELD 09w01 CC1OF (rw): Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to 0 .
0x40002014 B REGISTER EGR (wo): TIM14 event generation register
0x40002014 C FIELD 00w01 UG (wo): Update generation This bit can be set by software, it is automatically cleared by hardware.
0x40002014 C FIELD 01w01 CC1G (wo): Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
0x40002018 B REGISTER CCMR1_Input (rw): TIM14 capture/compare mode register 1
0x40002018 B REGISTER CCMR1_Output (rw): TIM14 capture/compare mode register 1
0x40002018 C FIELD 00w02 CC1S (rw): Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0x40002018 C FIELD 00w02 CC1S (rw): Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).
0x40002018 C FIELD 02w01 OC1FE (rw): Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
0x40002018 C FIELD 02w02 IC1PSC (rw): Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E= 0 (TIMx_CCER register).
0x40002018 C FIELD 03w01 OC1PE (rw): Output compare 1 preload enable
0x40002018 C FIELD 04w03 OC1M (rw): OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16.
0x40002018 C FIELD 04w04 IC1F (rw): Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
0x40002018 C FIELD 16w01 OC1M_3 (rw): OC1M[3]
0x40002020 B REGISTER CCER (rw): TIM14 capture/compare enable register
0x40002020 C FIELD 00w01 CC1E (rw): Capture/Compare 1 output enable.
0x40002020 C FIELD 01w01 CC1P (rw): Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used.
0x40002020 C FIELD 03w01 CC1NP (rw): Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description).
0x40002024 B REGISTER CNT (rw): TIM14 counter
0x40002024 C FIELD 00w16 CNT (rw): Counter value
0x40002024 C FIELD 31w01 UIFCPY (rw): UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register.
0x40002028 B REGISTER PSC (rw): TIM14 prescaler
0x40002028 C FIELD 00w16 PSC (rw): Prescaler value The counter clock frequency CK_CNT is equal to f<sub>CK_PSC</sub> / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode ).
0x4000202C B REGISTER ARR (rw): TIM14 auto-reload register
0x4000202C C FIELD 00w16 ARR (rw): Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to Section 19.3.1: Time-base unit on page 517 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
0x40002034 B REGISTER CCR1 (rw): TIM14 capture/compare register 1
0x40002034 C FIELD 00w16 CCR1 (rw): Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1).
0x40002068 B REGISTER TISEL (rw): TIM14 timer input selection register
0x40002068 C FIELD 00w04 TI1SEL (rw): selects TI1[0] to TI1[15] input Others: Reserved
0x40002800 A PERIPHERAL RTC
0x40002800 B REGISTER TR (rw): RTC time register
0x40002800 C FIELD 00w04 SU (rw): Second units in BCD format
0x40002800 C FIELD 04w03 ST (rw): Second tens in BCD format
0x40002800 C FIELD 08w04 MNU (rw): Minute units in BCD format
0x40002800 C FIELD 12w03 MNT (rw): Minute tens in BCD format
0x40002800 C FIELD 16w04 HU (rw): Hour units in BCD format
0x40002800 C FIELD 20w02 HT (rw): Hour tens in BCD format
0x40002800 C FIELD 22w01 PM (rw): AM/PM notation
0x40002804 B REGISTER DR (rw): RTC date register
0x40002804 C FIELD 00w04 DU (rw): Date units in BCD format
0x40002804 C FIELD 04w02 DT (rw): Date tens in BCD format
0x40002804 C FIELD 08w04 MU (rw): Month units in BCD format
0x40002804 C FIELD 12w01 MT (rw): Month tens in BCD format
0x40002804 C FIELD 13w03 WDU (rw): Week day units ...
0x40002804 C FIELD 16w04 YU (rw): Year units in BCD format
0x40002804 C FIELD 20w04 YT (rw): Year tens in BCD format
0x40002808 B REGISTER SSR (ro): RTC sub second register
0x40002808 C FIELD 00w16 SS (ro): Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR.
0x4000280C B REGISTER ICSR (rw): RTC initialization control and status register
0x4000280C C FIELD 00w01 ALRAWF (ro): Alarm A write flag This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode.
0x4000280C C FIELD 03w01 SHPF (ro): Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
0x4000280C C FIELD 04w01 INITS (ro): Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Power-on reset state).
0x4000280C C FIELD 05w01 RSF (rw): Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.
0x4000280C C FIELD 06w01 INITF (ro): Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.
0x4000280C C FIELD 07w01 INIT (rw): Initialization mode
0x4000280C C FIELD 16w01 RECALPF (ro): Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly.
0x40002810 B REGISTER PRER (rw): RTC prescaler register
0x40002810 C FIELD 00w15 PREDIV_S (rw): Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
0x40002810 C FIELD 16w07 PREDIV_A (rw): Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
0x40002818 B REGISTER CR (rw): RTC control register
0x40002818 C FIELD 03w01 TSEDGE (rw): Timestamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
0x40002818 C FIELD 04w01 REFCKON (rw): RTC_REFIN reference clock detection enable (50 or 60 Hz) Note: PREDIV_S must be 0x00FF.
0x40002818 C FIELD 05w01 BYPSHAD (rw): Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1.
0x40002818 C FIELD 06w01 FMT (rw): Hour format
0x40002818 C FIELD 08w01 ALRAE (rw): Alarm A enable
0x40002818 C FIELD 11w01 TSE (rw): timestamp enable
0x40002818 C FIELD 12w01 ALRAIE (rw): Alarm A interrupt enable
0x40002818 C FIELD 15w01 TSIE (rw): Timestamp interrupt enable
0x40002818 C FIELD 16w01 ADD1H (wo): Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0.
0x40002818 C FIELD 17w01 SUB1H (wo): Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0.
0x40002818 C FIELD 18w01 BKP (rw): Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
0x40002818 C FIELD 19w01 COSEL (rw): Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to Section 24.3.14: Calibration clock output.
0x40002818 C FIELD 20w01 POL (rw): Output polarity This bit is used to configure the polarity of TAMPALRM output.
0x40002818 C FIELD 21w02 OSEL (rw): Output selection These bits are used to select the flag to be routed to TAMPALRM output.
0x40002818 C FIELD 23w01 COE (rw): Calibration output enable This bit enables the CALIB output
0x40002818 C FIELD 29w01 TAMPALRM_PU (rw): TAMPALRM pull-up enable
0x40002818 C FIELD 30w01 TAMPALRM_TYPE (rw): TAMPALRM output type
0x40002818 C FIELD 31w01 OUT2EN (rw): RTC_OUT2 output enable
0x40002824 B REGISTER WPR (wo): RTC write protection register
0x40002824 C FIELD 00w08 KEY (wo): Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection.
0x40002828 B REGISTER CALR (rw): RTC calibration register
0x40002828 C FIELD 00w09 CALM (rw): Calibration minus The frequency of the calendar is reduced by masking CALM out of 2<sup>20</sup> RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section 24.3.12: RTC smooth digital calibration on page 606.
0x40002828 C FIELD 13w01 CALW16 (rw): Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected. This bit must not be set to 1 if CALW8 = 1. Note: CALM[0] is stuck at 0 when CALW16 = 1. Refer to Section 24.3.12: RTC smooth digital calibration.
0x40002828 C FIELD 14w01 CALW8 (rw): Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00 when CALW8 = 1. Refer to Section 24.3.12: RTC smooth digital calibration.
0x40002828 C FIELD 15w01 CALP (rw): Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 CALP) - CALM. Refer to Section 24.3.12: RTC smooth digital calibration.
0x4000282C B REGISTER SHIFTR (wo): RTC shift control register
0x4000282C C FIELD 00w15 SUBFS (wo): Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time.
0x4000282C C FIELD 31w01 ADD1S (wo): Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.
0x40002830 B REGISTER TSTR (ro): RTC timestamp time register
0x40002830 C FIELD 00w04 SU (ro): Second units in BCD format.
0x40002830 C FIELD 04w03 ST (ro): Second tens in BCD format.
0x40002830 C FIELD 08w04 MNU (ro): Minute units in BCD format.
0x40002830 C FIELD 12w03 MNT (ro): Minute tens in BCD format.
0x40002830 C FIELD 16w04 HU (ro): Hour units in BCD format.
0x40002830 C FIELD 20w02 HT (ro): Hour tens in BCD format.
0x40002830 C FIELD 22w01 PM (ro): AM/PM notation
0x40002834 B REGISTER TSDR (ro): RTC timestamp date register
0x40002834 C FIELD 00w04 DU (ro): Date units in BCD format
0x40002834 C FIELD 04w02 DT (ro): Date tens in BCD format
0x40002834 C FIELD 08w04 MU (ro): Month units in BCD format
0x40002834 C FIELD 12w01 MT (ro): Month tens in BCD format
0x40002834 C FIELD 13w03 WDU (ro): Week day units
0x40002838 B REGISTER TSSSR (ro): RTC timestamp sub second register
0x40002838 C FIELD 00w16 SS (ro): Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred.
0x40002840 B REGISTER ALRMAR (rw): RTC alarm A register
0x40002840 C FIELD 00w04 SU (rw): Second units in BCD format.
0x40002840 C FIELD 04w03 ST (rw): Second tens in BCD format.
0x40002840 C FIELD 07w01 MSK1 (rw): Alarm A seconds mask
0x40002840 C FIELD 08w04 MNU (rw): Minute units in BCD format
0x40002840 C FIELD 12w03 MNT (rw): Minute tens in BCD format
0x40002840 C FIELD 15w01 MSK2 (rw): Alarm A minutes mask
0x40002840 C FIELD 16w04 HU (rw): Hour units in BCD format
0x40002840 C FIELD 20w02 HT (rw): Hour tens in BCD format
0x40002840 C FIELD 22w01 PM (rw): AM/PM notation
0x40002840 C FIELD 23w01 MSK3 (rw): Alarm A hours mask
0x40002840 C FIELD 24w04 DU (rw): Date units or day in BCD format
0x40002840 C FIELD 28w02 DT (rw): Date tens in BCD format
0x40002840 C FIELD 30w01 WDSEL (rw): Week day selection
0x40002840 C FIELD 31w01 MSK4 (rw): Alarm A date mask
0x40002844 B REGISTER ALRMASSR (rw): RTC alarm A sub second register
0x40002844 C FIELD 00w15 SS (rw): Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
0x40002844 C FIELD 24w04 MASKSS (rw): Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation.
0x40002850 B REGISTER SR (ro): RTC status register
0x40002850 C FIELD 00w01 ALRAF (ro): Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR).
0x40002850 C FIELD 03w01 TSF (ro): Timestamp flag This flag is set by hardware when a timestamp event occurs.
0x40002850 C FIELD 04w01 TSOVF (ro): Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
0x40002854 B REGISTER MISR (ro): RTC masked interrupt status register
0x40002854 C FIELD 00w01 ALRAMF (ro): Alarm A masked flag This flag is set by hardware when the alarm A interrupt occurs.
0x40002854 C FIELD 03w01 TSMF (ro): Timestamp masked flag This flag is set by hardware when a timestamp interrupt occurs.
0x40002854 C FIELD 04w01 TSOVMF (ro): Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
0x4000285C B REGISTER SCR (wo): RTC status clear register
0x4000285C C FIELD 00w01 CALRAF (wo): Clear alarm A flag Writing 1 in this bit clears the ALRAF bit in the RTC_SR register.
0x4000285C C FIELD 03w01 CTSF (wo): Clear timestamp flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register.
0x4000285C C FIELD 04w01 CTSOVF (wo): Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.
0x40002C00 A PERIPHERAL WWDG
0x40002C00 B REGISTER CR (rw): WWDG control register
0x40002C00 C FIELD 00w07 T (rw): 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every (4096 x 2<sup>WDGTB[2:0]</sup>) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared).
0x40002C00 C FIELD 07w01 WDGA (rw): Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
0x40002C04 B REGISTER CFR (rw): WWDG configuration register
0x40002C04 C FIELD 00w07 W (rw): 7-bit window value These bits contain the window value to be compared with the down-counter.
0x40002C04 C FIELD 09w01 EWI (rw): Early wake-up interrupt enable Set by software and cleared by hardware after a reset. When set, an interrupt occurs whenever the counter reaches the value 0x40.
0x40002C04 C FIELD 11w03 WDGTB (rw): Timer base The timebase of the prescaler can be modified as follows:
0x40002C08 B REGISTER SR (rw): WWDG status register
0x40002C08 C FIELD 00w01 EWIF (rw): Early wake-up interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not enabled.
0x40003000 A PERIPHERAL IWDG
0x40003000 B REGISTER KR (wo): IWDG key register
0x40003000 C FIELD 00w16 KEY (wo): Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section 22.3.4: Register access protection) Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option is selected)
0x40003004 B REGISTER PR (rw): IWDG prescaler register
0x40003004 C FIELD 00w03 PR (rw): Prescaler divider These bits are write access protected see Section 22.3.4: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the IWDG status register (IWDG_SR) must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG status register (IWDG_SR) is reset.
0x40003008 B REGISTER RLR (rw): IWDG reload register
0x40003008 C FIELD 00w12 RL (rw): Watchdog counter reload value These bits are write access protected see Register access protection. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG key register (IWDG_KR). The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the reload value. Note: Reading this register returns the reload value from the V<sub>DD</sub> voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on it. For this reason the value read from this register is valid only when the RVU bit in the IWDG status register (IWDG_SR) is reset.
0x4000300C B REGISTER SR (ro): IWDG status register
0x4000300C C FIELD 00w01 PVU (ro): Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the V<sub>DD</sub> voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset.
0x4000300C C FIELD 01w01 RVU (ro): Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the V<sub>DD</sub> voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset.
0x4000300C C FIELD 02w01 WVU (ro): Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the V<sub>DD</sub> voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset.
0x40003010 B REGISTER WINR (rw): IWDG window register
0x40003010 C FIELD 00w12 WIN (rw): Watchdog counter window value These bits are write access protected, see Section 22.3.4, they contain the high limit of the window value to be compared with the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG status register (IWDG_SR) must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the V<sub>DD</sub> voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG status register (IWDG_SR) is reset.
0x40003800 A PERIPHERAL SPI2
0x40003800 B REGISTER CR1 (rw): SPI control register 1
0x40003800 C FIELD 00w01 CPHA (rw): Clock phase Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode.
0x40003800 C FIELD 01w01 CPOL (rw): Clock polarity Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode except the case when CRC is applied at TI mode.
0x40003800 C FIELD 02w01 MSTR (rw): Master selection Note: This bit should not be changed when communication is ongoing. Note: This bit is not used in I<sup>2</sup>S mode.
0x40003800 C FIELD 03w03 BR (rw): Baud rate control Note: These bits should not be changed when communication is ongoing. Note: These bits are not used in I<sup>2</sup>S mode.
0x40003800 C FIELD 06w01 SPE (rw): SPI enable Note: When disabling the SPI, follow the procedure described in Procedure for disabling the SPI on page 789. Note: This bit is not used in I<sup>2</sup>S mode.
0x40003800 C FIELD 07w01 LSBFIRST (rw): Frame format Note: 1. This bit should not be changed when communication is ongoing. Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode.
0x40003800 C FIELD 08w01 SSI (rw): Internal slave select This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode.
0x40003800 C FIELD 09w01 SSM (rw): Software slave management When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit. Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode.
0x40003800 C FIELD 10w01 RXONLY (rw): Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I<sup>2</sup>S mode.
0x40003800 C FIELD 11w01 CRCL (rw): CRC length This bit is set and cleared by software to select the CRC length. Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. Note: This bit is not used in I<sup>2</sup>S mode.
0x40003800 C FIELD 12w01 CRCNEXT (rw): Transmit CRC next Note: This bit has to be written as soon as the last data is written in the SPI1_DR register. Note: This bit is not used in I<sup>2</sup>S mode.
0x40003800 C FIELD 13w01 CRCEN (rw): Hardware CRC calculation enable Note: This bit should be written only when SPI is disabled (SPE = 0 ) for correct operation. Note: This bit is not used in I<sup>2</sup>S mode.
0x40003800 C FIELD 14w01 BIDIOE (rw): Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. Note: This bit is not used in I<sup>2</sup>S mode.
0x40003800 C FIELD 15w01 BIDIMODE (rw): Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I<sup>2</sup>S mode.
0x40003804 B REGISTER CR2 (rw): SPI control register 2
0x40003804 C FIELD 00w01 RXDMAEN (rw): Rx buffer DMA enable When this bit is set, a DMA request is generated whenever the RXNE flag is set.
0x40003804 C FIELD 01w01 TXDMAEN (rw): Tx buffer DMA enable When this bit is set, a DMA request is generated whenever the TXE flag is set.
0x40003804 C FIELD 02w01 SSOE (rw): SS output enable Note: This bit is not used in I<sup>2</sup>S mode and SPI TI mode.
0x40003804 C FIELD 03w01 NSSP (rw): NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = 1 , or FRF = 1 . Note: 1. This bit must be written only when the SPI is disabled (SPE=0). Note: 2. This bit is not used in I<sup>2</sup>S mode and SPI TI mode.
0x40003804 C FIELD 04w01 FRF (rw): Frame format 1 SPI TI mode Note: This bit must be written only when the SPI is disabled (SPE=0). Note: This bit is not used in I<sup>2</sup>S mode.
0x40003804 C FIELD 05w01 ERRIE (rw): Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode and UDR, OVR, and FRE in I<sup>2</sup>S mode).
0x40003804 C FIELD 06w01 RXNEIE (rw): RX buffer not empty interrupt enable
0x40003804 C FIELD 07w01 TXEIE (rw): Tx buffer empty interrupt enable
0x40003804 C FIELD 08w04 DS (rw): Data size These bits configure the data length for SPI transfers. If software attempts to write one of the Not used values, they are forced to the value 0111 (8-bit) Note: These bits are not used in I<sup>2</sup>S mode.
0x40003804 C FIELD 12w01 FRXTH (rw): FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I<sup>2</sup>S mode.
0x40003804 C FIELD 13w01 LDMA_RX (rw): Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI1_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI1_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI1_CR1 register). Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. Note: This bit is not used in I S mode.
0x40003804 C FIELD 14w01 LDMA_TX (rw): Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI1_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI1_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI1_CR1 register). Note: Refer to Procedure for disabling the SPI on page 789 if the CRCEN bit is set. Note: This bit is not used in I S mode.
0x40003808 B REGISTER SR (rw): SPI status register
0x40003808 C FIELD 00w01 RXNE (ro): Receive buffer not empty
0x40003808 C FIELD 01w01 TXE (ro): Transmit buffer empty
0x40003808 C FIELD 02w01 CHSIDE (ro): Channel side Note: This bit is not used in SPI mode. It has no significance in PCM mode.
0x40003808 C FIELD 03w01 UDR (ro): Underrun flag This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence. Note: This bit is not used in SPI mode.
0x40003808 C FIELD 04w01 CRCERR (rw): CRC error flag Note: This flag is set by hardware and cleared by software writing 0. Note: This bit is not used in I<sup>2</sup>S mode.
0x40003808 C FIELD 05w01 MODF (ro): Mode fault This flag is set by hardware and reset by a software sequence. Refer to Section : Mode fault (MODF) on page 799 for the software sequence. Note: This bit is not used in I<sup>2</sup>S mode.
0x40003808 C FIELD 06w01 OVR (ro): Overrun flag This flag is set by hardware and reset by a software sequence. Refer to I2S error flags on page 821 for the software sequence.
0x40003808 C FIELD 07w01 BSY (ro): Busy flag This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags and Procedure for disabling the SPI on page 789.
0x40003808 C FIELD 08w01 FRE (ro): Frame format error This flag is used for SPI in TI slave mode and I<sup>2</sup>S slave mode. Refer to Section 27.5.11: SPI error flags and Section 27.7.8: I2S error flags. This flag is set by hardware and reset when SPI1_SR is read by software.
0x40003808 C FIELD 09w02 FRLVL (ro): FIFO reception level These bits are set and cleared by hardware. Note: These bits are not used in I S mode and in SPI receive-only mode while CRC calculation is enabled.
0x40003808 C FIELD 11w02 FTLVL (ro): FIFO transmission level These bits are set and cleared by hardware. Note: This bit is not used in I<sup>2</sup>S mode.
0x4000380C B REGISTER DR (rw): SPI data register
0x4000380C B REGISTER DR8 (rw): Direct 8-bit access to data register
0x4000380C C FIELD 00w08 DR: Data register
0x4000380C C FIELD 00w16 DR (rw): Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 27.5.9: Data transmission and reception procedures). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used.
0x40003810 B REGISTER CRCPR (rw): SPI CRC polynomial register
0x40003810 C FIELD 00w16 CRCPOLY (rw): CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0x0007) is the reset value of this register. Another polynomial can be configured as required.
0x40003814 B REGISTER RXCRCR (ro): SPI Rx CRC register
0x40003814 C FIELD 00w16 RXCRC (ro): Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI1_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI1_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI1_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI1_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. Note: These bits are not used in I<sup>2</sup>S mode.
0x40003818 B REGISTER TXCRCR (ro): SPI Tx CRC register
0x40003818 C FIELD 00w16 TXCRC (ro): Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI1_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI1_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI1_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI1_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. Note: These bits are not used in I<sup>2</sup>S mode.
0x4000381C B REGISTER I2SCFGR (rw): SPI1_I2S configuration register
0x4000381C C FIELD 00w01 CHLEN (rw): Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. Note: It is not used in SPI mode.
0x4000381C C FIELD 01w02 DATLEN (rw): Data length to be transferred Note: For correct operation, these bits should be configured when the I2S is disabled. Note: They are not used in SPI mode.
0x4000381C C FIELD 03w01 CKPOL (rw): Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. Note: It is not used in SPI mode. Note: The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals.
0x4000381C C FIELD 04w02 I2SSTD (rw): I2S standard selection For more details on I<sup>2</sup>S standards, refer to Section 27.7.2 on page 805 Note: For correct operation, these bits should be configured when the I2S is disabled. Note: They are not used in SPI mode.
0x4000381C C FIELD 07w01 PCMSYNC (rw): PCM frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used). Note: It is not used in SPI mode.
0x4000381C C FIELD 08w02 I2SCFG (rw): I2S configuration mode Note: These bits should be configured when the I2S is disabled. Note: They are not used in SPI mode.
0x4000381C C FIELD 10w01 I2SE (rw): I2S enable Note: This bit is not used in SPI mode.
0x4000381C C FIELD 11w01 I2SMOD (rw): I2S mode selection Note: This bit should be configured when the SPI is disabled.
0x4000381C C FIELD 12w01 ASTRTEN (rw): Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I<sup>2</sup>S Philips Standard is used, or a rising edge for other standards. Note: The appropriate level is a low level on WS signal when I<sup>2</sup>S Philips Standard is used, or a high level for other standards. Note: Please refer to Section 27.7.3: Start-up description for additional information.
0x40003820 B REGISTER I2SPR (rw): SPI1_I2S prescaler register
0x40003820 C FIELD 00w08 I2SDIV (rw): I2S linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to Section 27.7.3 on page 812. Note: These bits should be configured when the I2S is disabled. They are used only when the I2S is in master mode. Note: They are not used in SPI mode.
0x40003820 C FIELD 08w01 ODD (rw): Odd factor for the prescaler Refer to Section 27.7.3 on page 812. Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. Note: It is not used in SPI mode.
0x40003820 C FIELD 09w01 MCKOE (rw): Master clock output enable Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. Note: It is not used in SPI mode.
0x40004400 A PERIPHERAL USART2
0x40004400 B REGISTER CR1_disabled (rw): USART control register 1
0x40004400 B REGISTER CR1_enabled (rw): USART control register 1
0x40004400 C FIELD 00w01 UE (rw): USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK is always available when CLKEN = 1, regardless of the UE bit value.
0x40004400 C FIELD 00w01 UE (rw): USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. Note: The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. Note: In Smartcard mode, (SCEN = 1), the CK pin is always available when CLKEN = 1, regardless of the UE bit value.
0x40004400 C FIELD 01w01 UESM (rw): USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004400 C FIELD 01w01 UESM (rw): USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004400 C FIELD 02w01 RE (rw): Receiver enable This bit enables the receiver. It is set and cleared by software.
0x40004400 C FIELD 02w01 RE (rw): Receiver enable This bit enables the receiver. It is set and cleared by software.
0x40004400 C FIELD 03w01 TE (rw): Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1 . To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
0x40004400 C FIELD 03w01 TE (rw): Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ( 0 followed by 1 ) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to 1 . To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. Note: In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts.
0x40004400 C FIELD 04w01 IDLEIE (rw): IDLE interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 04w01 IDLEIE (rw): IDLE interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 05w01 RXFNEIE (rw): RXFIFO not empty interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 05w01 RXNEIE (rw): Receive data register not empty This bit is set and cleared by software.
0x40004400 C FIELD 06w01 TCIE (rw): Transmission complete interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 06w01 TCIE (rw): Transmission complete interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 07w01 TXEIE (rw): Transmit data register empty This bit is set and cleared by software.
0x40004400 C FIELD 07w01 TXFNFIE (rw): TXFIFO not-full interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 08w01 PEIE (rw): PE interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 08w01 PEIE (rw): PE interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 09w01 PS (rw): Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004400 C FIELD 09w01 PS (rw): Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004400 C FIELD 10w01 PCE (rw): Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0).
0x40004400 C FIELD 10w01 PCE (rw): Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1; 8th bit if M = 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UE = 0).
0x40004400 C FIELD 11w01 WAKE (rw): Receiver wake-up method This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004400 C FIELD 11w01 WAKE (rw): Receiver wake-up method This bit determines the USART wake-up method from Mute mode. It is set or cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004400 C FIELD 12w01 M0 (rw): Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0).
0x40004400 C FIELD 12w01 M0 (rw): Word length This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or cleared by software (refer to bit 28 (M1)description). This bit can only be written when the USART is disabled (UE = 0).
0x40004400 C FIELD 13w01 MME (rw): Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0x40004400 C FIELD 13w01 MME (rw): Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software.
0x40004400 C FIELD 14w01 CMIE (rw): Character match interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 14w01 CMIE (rw): Character match interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 15w01 OVER8 (rw): Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
0x40004400 C FIELD 15w01 OVER8 (rw): Oversampling mode This bit can only be written when the USART is disabled (UE = 0). Note: In LIN, IrDA and Smartcard modes, this bit must be kept cleared.
0x40004400 C FIELD 16w05 DEDT (rw): Driver enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004400 C FIELD 16w05 DEDT (rw): Driver enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004400 C FIELD 21w05 DEAT (rw): Driver enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004400 C FIELD 21w05 DEAT (rw): Driver enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004400 C FIELD 26w01 RTOIE (rw): Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 26.4: USART implementation on page 691.
0x40004400 C FIELD 26w01 RTOIE (rw): Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Section 26.4: USART implementation on page 691.
0x40004400 C FIELD 27w01 EOBIE (rw): End of Bbock interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004400 C FIELD 27w01 EOBIE (rw): End-of-block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004400 C FIELD 28w01 M1 (rw): Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00 : 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01 : 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10 : 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported.
0x40004400 C FIELD 28w01 M1 (rw): Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = 00 : 1 start bit, 8 Data bits, n Stop bit M[1:0] = 01 : 1 start bit, 9 Data bits, n Stop bit M[1:0] = 10 : 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UE = 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and auto baud rate (0x7F and 0x55 frames detection) are not supported.
0x40004400 C FIELD 29w01 FIFOEN (rw): FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
0x40004400 C FIELD 29w01 FIFOEN (rw): FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes.
0x40004400 C FIELD 30w01 TXFEIE (rw): TXFIFO empty interrupt enable This bit is set and cleared by software.
0x40004400 C FIELD 31w01 RXFFIE (rw): RXFIFO full interrupt enable This bit is set and cleared by software.
0x40004404 B REGISTER CR2 (rw): USART control register 2
0x40004404 C FIELD 00w01 SLVEN (rw): Synchronous Slave mode enable When the SLVEN bit is set, the synchronous slave mode is enabled. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 03w01 DIS_NSS (rw): NSS pin enable When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 04w01 ADDM7 (rw): 7-bit address detection/4-bit address detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UE = 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively.
0x40004404 C FIELD 05w01 LBDL (rw): LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UE = 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 06w01 LBDIE (rw): LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 08w01 LBCL (rw): Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 09w01 CPHA (rw): Clock phase This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 249 and Figure 250) This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 10w01 CPOL (rw): Clock polarity This bit enables the user to select the polarity of the clock output on the CK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UE = 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 11w01 CLKEN (rw): Clock enable This bit enables the user to enable the CK pin. This bit can only be written when the USART is disabled (UE = 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691. In Smartcard mode, in order to provide correctly the CK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 Note: UE = 1
0x40004404 C FIELD 12w02 STOP (rw): Stop bits These bits are used for programming the stop bits. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C FIELD 14w01 LINEN (rw): LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 15w01 SWAP (rw): Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C FIELD 16w01 RXINV (rw): RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C FIELD 17w01 TXINV (rw): TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C FIELD 18w01 DATAINV (rw): Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C FIELD 19w01 MSBFIRST (rw): Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UE = 0).
0x40004404 C FIELD 20w01 ABREN (rw): Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 21w02 ABRMOD (rw): Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UE = 0). Note: If DATAINV = 1 and/or MSBFIRST = 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 23w01 RTOEN (rw): Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004404 C FIELD 24w08 ADD (rw): Address of the USART node These bits give the address of the USART node in Mute mode or a character code to be recognized in low-power or Run mode: In Mute mode: they are used in multiprocessor communication to wake up from Mute mode with 4-bit/7-bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1. In 4-bit address mark detection, only ADD[3:0] bits are used. In low-power mode: they are used for wake up from low-power mode on character match. When WUS[1:0] is programmed to 0b00 (WUF active on address match), the wake-up from low-power mode is performed when the received character corresponds to the character programmed through ADD[6:0] or ADD[3:0] bitfield (depending on ADDM7 bit), and WUF interrupt is enabled by setting WUFIE bit. The MSB of the character sent by transmitter should be equal to 1. In Run mode with Mute mode inactive (for example, end-of-block detection in ModBus protocol): the whole received character (8 bits) is compared to ADD[7:0] value and CMF flag is set on match. An interrupt is generated if the CMIE bit is set. These bits can only be written when the reception is disabled (RE = 0) or when the USART is disabled (UE = 0).
0x40004408 B REGISTER CR3 (rw): USART control register 3
0x40004408 C FIELD 00w01 EIE (rw): Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FE = 1 or ORE = 1 or NE = 1 or UDR = 1 in the USART_ISR register).
0x40004408 C FIELD 01w01 IREN (rw): IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 02w01 IRLP (rw): IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UE = 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 03w01 HDSEL (rw): Half-duplex selection Selection of Single-wire Half-duplex mode This bit can only be written when the USART is disabled (UE = 0).
0x40004408 C FIELD 04w01 NACK (rw): Smartcard NACK enable This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 05w01 SCEN (rw): Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 06w01 DMAR (rw): DMA enable receiver This bit is set/reset by software
0x40004408 C FIELD 07w01 DMAT (rw): DMA enable transmitter This bit is set/reset by software
0x40004408 C FIELD 08w01 RTSE (rw): RTS enable This bit can only be written when the USART is disabled (UE = 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 09w01 CTSE (rw): CTS enable This bit can only be written when the USART is disabled (UE = 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 10w01 CTSIE (rw): CTS interrupt enable Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 11w01 ONEBIT (rw): One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UE = 0).
0x40004408 C FIELD 12w01 OVRDIS (rw): Overrun disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UE = 0). Note: This control bit enables checking the communication flow w/o reading the data
0x40004408 C FIELD 13w01 DDRE (rw): DMA Disable on reception error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error.
0x40004408 C FIELD 14w01 DEM (rw): Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 15w01 DEP (rw): Driver enable polarity selection This bit can only be written when the USART is disabled (UE = 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 17w03 SCARCNT (rw): Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UE = 0). When the USART is enabled (UE = 1), this bitfield may only be written to 0x0, in order to stop retransmission. 0x1 to 0x7: number of automatic retransmission attempts (before signaling error) Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 20w02 WUS (rw): Wake-up from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (wake-up from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 22w01 WUFIE (rw): Wake-up from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 23w01 TXFTIE (rw): TXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40004408 C FIELD 24w01 TCBGTIE (rw): Transmission complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004408 C FIELD 25w03 RXFTCFG (rw): Receive FIFO threshold configuration Remaining combinations: Reserved
0x40004408 C FIELD 28w01 RXFTIE (rw): RXFIFO threshold interrupt enable This bit is set and cleared by software.
0x40004408 C FIELD 29w03 TXFTCFG (rw): TXFIFO threshold configuration Remaining combinations: Reserved
0x4000440C B REGISTER BRR (rw): USART baud rate register
0x4000440C C FIELD 00w16 BRR (rw): USART baud rate BRR[15:4] BRR[15:4] = USARTDIV[15:4] BRR[3:0] When OVER8 = 0, BRR[3:0] = USARTDIV[3:0]. When OVER8 = 1: BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right. BRR[3] must be kept cleared.
0x40004410 B REGISTER GTPR (rw): USART guard time and prescaler register
0x40004410 C FIELD 00w08 PSC (rw): Prescaler value
0x40004410 C FIELD 08w08 GT (rw): Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UE = 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004414 B REGISTER RTOR (rw): USART receiver timeout register
0x40004414 C FIELD 00w24 RTO (rw): Receiver timeout value This bitfield gives the Receiver timeout value in terms of number of bits during which there is no activity on the RX line. In standard mode, the RTOF flag is set if, after the last received character, no new start bit is detected for more than the RTO value. In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard chapter for more details. In the standard, the CWT/BWT measurement is done starting from the start bit of the last received character. Note: This value must only be programmed once per received character.
0x40004414 C FIELD 24w08 BLEN (rw): Block length This bitfield gives the Block length in Smartcard T = 1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0: 0 information characters + LEC BLEN = 1: 0 information characters + CRC BLEN = 255: 254 information characters + CRC (total 256 characters)) In Smartcard mode, the Block length counter is reset when TXE = 0 (TXFE = 0 in case FIFO mode is enabled). This bitfield can be used also in other modes. In this case, the Block length counter is reset when RE = 0 (receiver disabled) and/or when the EOBCF bit is written to 1. Note: This value can be programmed after the start of the block reception (using the data from the LEN character in the Prologue Field). It must be programmed only once per received block.
0x40004418 B REGISTER RQR (wo): USART request register
0x40004418 C FIELD 00w01 ABRRQ (wo): Auto baud rate request Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004418 C FIELD 01w01 SBKRQ (wo): Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit.
0x40004418 C FIELD 02w01 MMRQ (wo): Mute mode request Writing 1 to this bit puts the USART in Mute mode and resets the RWU flag.
0x40004418 C FIELD 03w01 RXFRQ (wo): Receive data flush request Writing 1 to this bit empties the entire receive FIFO i.e. clears the bit RXFNE. This enables to discard the received data without reading them, and avoid an overrun condition.
0x40004418 C FIELD 04w01 TXFRQ (wo): Transmit data flush request When FIFO mode is disabled, writing 1 to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register.
0x4000441C B REGISTER ISR_disabled (ro): USART interrupt and status register
0x4000441C B REGISTER ISR_enabled (ro): USART interrupt and status register
0x4000441C C FIELD 00w01 PE (ro): Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0x4000441C C FIELD 00w01 PE (ro): Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR.
0x4000441C C FIELD 01w01 FE (ro): Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR3 register.
0x4000441C C FIELD 01w01 FE (ro): Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIE = 1 in the USART_CR3 register. Note: This error is associated with the character in the USART_RDR.
0x4000441C C FIELD 02w01 NE (ro): Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 26.5.8: Tolerance of the USART receiver to clock deviation on page 709). Note: This error is associated with the character in the USART_RDR.
0x4000441C C FIELD 02w01 NE (ro): Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. Note: When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Section 26.5.8: Tolerance of the USART receiver to clock deviation on page 709).
0x4000441C C FIELD 03w01 ORE (ro): Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
0x4000441C C FIELD 03w01 ORE (ro): Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIE = 1 or EIE = 1 in the LPUART_CR1 register, or EIE = 1 in the USART_CR3 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. Note: This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register.
0x4000441C C FIELD 04w01 IDLE (ro): Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.
0x4000441C C FIELD 04w01 IDLE (ro): Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). Note: If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0), whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.
0x4000441C C FIELD 05w01 RXFNE (ro): RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register.
0x4000441C C FIELD 05w01 RXNE (ro): Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIE = 1 in the USART_CR1 register.
0x4000441C C FIELD 06w01 TC (ro): Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately.
0x4000441C C FIELD 06w01 TC (ro): Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIE = 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set.
0x4000441C C FIELD 07w01 TXE (ro): Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit = 1 in the USART_CR1 register.
0x4000441C C FIELD 07w01 TXFNF (ro): TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). Note: This bit is used during single buffer transmission.
0x4000441C C FIELD 08w01 LBDF (ro): LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 08w01 LBDF (ro): LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 09w01 CTSIF (ro): CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000441C C FIELD 09w01 CTSIF (ro): CTS interrupt flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIE = 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000441C C FIELD 10w01 CTS (ro): CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000441C C FIELD 10w01 CTS (ro): CTS flag This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value.
0x4000441C C FIELD 11w01 RTOF (ro): Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
0x4000441C C FIELD 11w01 RTOF (ro): Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIE = 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. Note: The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value.
0x4000441C C FIELD 12w01 EOBF (ro): End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 12w01 EOBF (ro): End of block flag This bit is set by hardware when a complete block has been received (for example T = 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 13w01 UDR (ro): SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 13w01 UDR (ro): SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 14w01 ABRE (ro): Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000441C C FIELD 14w01 ABRE (ro): Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000441C C FIELD 15w01 ABRF (ro): Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000441C C FIELD 15w01 ABRF (ro): Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABRE = 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value.
0x4000441C C FIELD 16w01 BUSY (ro): Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
0x4000441C C FIELD 16w01 BUSY (ro): Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not).
0x4000441C C FIELD 17w01 CMF (ro): Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register.
0x4000441C C FIELD 17w01 CMF (ro): Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE = 1in the USART_CR1 register.
0x4000441C C FIELD 18w01 SBKF (ro): Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
0x4000441C C FIELD 18w01 SBKF (ro): Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission.
0x4000441C C FIELD 19w01 RWU (ro): Receiver wake-up from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 19w01 RWU (ro): Receiver wake-up from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wake-up/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wake-up on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 20w01 WUF (ro): Wake-up from low-power mode flag This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 20w01 WUF (ro): Wake-up from low-power mode flag This bit is set by hardware, when a wake-up event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIE = 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 21w01 TEACK (ro): Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period.
0x4000441C C FIELD 21w01 TEACK (ro): Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TE = 0, followed by TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period.
0x4000441C C FIELD 22w01 REACK (ro): Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 22w01 REACK (ro): Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x4000441C C FIELD 23w01 TXFE (ro): TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit = 1 (bit 30) in the USART_CR1 register.
0x4000441C C FIELD 24w01 RXFF (ro): RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit = 1 in the USART_CR1 register.
0x4000441C C FIELD 25w01 TCBGT (ro): Transmission complete before guard time flag
0x4000441C C FIELD 25w01 TCBGT (ro): Transmission complete before guard time flag
0x4000441C C FIELD 26w01 RXFT (ro): RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to 101 , RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data.
0x4000441C C FIELD 27w01 TXFT (ro): TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit = 1 (bit 31) in the USART_CR3 register.
0x40004420 B REGISTER ICR (wo): USART interrupt flag clear register
0x40004420 C FIELD 00w01 PECF (wo): Parity error clear flag Writing 1 to this bit clears the PE flag in the USART_ISR register.
0x40004420 C FIELD 01w01 FECF (wo): Framing error clear flag Writing 1 to this bit clears the FE flag in the USART_ISR register.
0x40004420 C FIELD 02w01 NECF (wo): Noise detected clear flag Writing 1 to this bit clears the NE flag in the USART_ISR register.
0x40004420 C FIELD 03w01 ORECF (wo): Overrun error clear flag Writing 1 to this bit clears the ORE flag in the USART_ISR register.
0x40004420 C FIELD 04w01 IDLECF (wo): Idle line detected clear flag Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
0x40004420 C FIELD 05w01 TXFECF (wo): TXFIFO empty clear flag Writing 1 to this bit clears the TXFE flag in the USART_ISR register.
0x40004420 C FIELD 06w01 TCCF (wo): Transmission complete clear flag Writing 1 to this bit clears the TC flag in the USART_ISR register.
0x40004420 C FIELD 07w01 TCBGTCF (wo): Transmission complete before Guard time clear flag Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
0x40004420 C FIELD 08w01 LBDCF (wo): LIN break detection clear flag Writing 1 to this bit clears the LBDF flag in the USART_ISR register. Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004420 C FIELD 09w01 CTSCF (wo): CTS clear flag Writing 1 to this bit clears the CTSIF flag in the USART_ISR register. Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004420 C FIELD 11w01 RTOCF (wo): Receiver timeout clear flag Writing 1 to this bit clears the RTOF flag in the USART_ISR register. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004420 C FIELD 12w01 EOBCF (wo): End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004420 C FIELD 13w01 UDRCF (wo): SPI slave underrun clear flag Writing 1 to this bit clears the UDRF flag in the USART_ISR register. Note: If the USART does not support SPI slave mode, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691
0x40004420 C FIELD 17w01 CMCF (wo): Character match clear flag Writing 1 to this bit clears the CMF flag in the USART_ISR register.
0x40004420 C FIELD 20w01 WUCF (wo): Wake-up from low-power mode clear flag Writing 1 to this bit clears the WUF flag in the USART_ISR register. Note: If the USART does not support the wake-up from Stop feature, this bit is reserved and must be kept at reset value. Refer to Section 26.4: USART implementation on page 691.
0x40004424 B REGISTER RDR (ro): USART receive data register
0x40004424 C FIELD 00w09 RDR (ro): Receive data value Contains the received data character. The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 243). When receiving with the parity enabled, the value read in the MSB bit is the received parity bit.
0x40004428 B REGISTER TDR (rw): USART transmit data register
0x40004428 C FIELD 00w09 TDR (rw): Transmit data value Contains the data character to be transmitted. The USART_TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 243). When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNF = 1.
0x4000442C B REGISTER PRESC (rw): USART prescaler register
0x4000442C C FIELD 00w04 PRESCALER (rw): Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256.
0x40005400 A PERIPHERAL I2C1
0x40005400 B REGISTER CR1 (rw): I2C control register 1
0x40005400 C FIELD 00w01 PE (rw): Peripheral enable Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least three APB clock cycles.
0x40005400 C FIELD 01w01 TXIE (rw): TX interrupt enable
0x40005400 C FIELD 02w01 RXIE (rw): RX interrupt enable
0x40005400 C FIELD 03w01 ADDRIE (rw): Address match interrupt enable (slave only)
0x40005400 C FIELD 04w01 NACKIE (rw): Not acknowledge received interrupt enable
0x40005400 C FIELD 05w01 STOPIE (rw): Stop detection interrupt enable
0x40005400 C FIELD 06w01 TCIE (rw): Transfer complete interrupt enable Note: Any of these events generates an interrupt: Note: Transfer complete (TC) Note: Transfer complete reload (TCR)
0x40005400 C FIELD 07w01 ERRIE (rw): Error interrupts enable Note: Any of these errors generates an interrupt: Note: Arbitration loss (ARLO) Note: Bus error detection (BERR) Note: Overrun/underrun (OVR) Note: Timeout detection (TIMEOUT) Note: PEC error detection (PECERR) Note: Alert pin event detection (ALERT)
0x40005400 C FIELD 08w04 DNF (rw): Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t<sub>I2CCLK</sub> ... Note: If the analog filter is enabled, the digital filter is added to it. This filter can be programmed only when the I2C is disabled (PE = 0).
0x40005400 C FIELD 12w01 ANFOFF (rw): Analog noise filter OFF Note: This bit can be programmed only when the I2C is disabled (PE = 0).
0x40005400 C FIELD 14w01 TXDMAEN (rw): DMA transmission requests enable
0x40005400 C FIELD 15w01 RXDMAEN (rw): DMA reception requests enable
0x40005400 C FIELD 16w01 SBC (rw): Slave byte control This bit is used to enable hardware byte control in slave mode.
0x40005400 C FIELD 17w01 NOSTRETCH (rw): Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can be programmed only when the I2C is disabled (PE = 0).
0x40005400 C FIELD 18w01 WUPEN (rw): Wake-up from Stop mode enable Note: If the wake-up from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. Note: WUPEN can be set only when DNF = 0000.
0x40005400 C FIELD 19w01 GCEN (rw): General call enable
0x40005400 C FIELD 20w01 SMBHEN (rw): SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005400 C FIELD 21w01 SMBDEN (rw): SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005400 C FIELD 22w01 ALERTEN (rw): SMBus alert enable Note: When ALERTEN = 0, the SMBA pin can be used as a standard GPIO. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005400 C FIELD 23w01 PECEN (rw): PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005404 B REGISTER CR2 (rw): I2C control register 2
0x40005404 C FIELD 00w10 SADD (rw): Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] must be written with the 7-bit slave address to be sent. Bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] must be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
0x40005404 C FIELD 10w01 RD_WRN (rw): Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C FIELD 11w01 ADD10 (rw): 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C FIELD 12w01 HEAD10R (rw): 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005404 C FIELD 13w01 START (rw): Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD = 0, after the end of the NBYTES transfer. Otherwise, setting this bit generates a START condition once the bus is free. Note: Writing 0 to this bit has no effect. Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. Note: This bit has no effect when RELOAD is set.
0x40005404 C FIELD 14w01 STOP (rw): Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In master mode: Note: Writing 0 to this bit has no effect.
0x40005404 C FIELD 15w01 NACK (rw): NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. Note: Writing 0 to this bit has no effect. Note: This bit is used only in slave mode: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated, whatever the NACK bit value. Note: When hardware PEC checking is enabled (PECBYTE = 1), the PEC acknowledge value does not depend on the NACK value.
0x40005404 C FIELD 16w08 NBYTES (rw): Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don t care in slave mode with SBC = 0. Note: Changing these bits when the START bit is set is not allowed.
0x40005404 C FIELD 24w01 RELOAD (rw): NBYTES reload mode This bit is set and cleared by software.
0x40005404 C FIELD 25w01 AUTOEND (rw): Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
0x40005404 C FIELD 26w01 PECBYTE (rw): Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. Note: Writing 0 to this bit has no effect. Note: This bit has no effect when RELOAD is set, and in slave mode when SBC = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005408 B REGISTER OAR1 (rw): I2C own address 1 register
0x40005408 C FIELD 00w10 OA1 (rw): Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. Bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN = 0.
0x40005408 C FIELD 10w01 OA1MODE (rw): Own address 1 10-bit mode Note: This bit can be written only when OA1EN = 0.
0x40005408 C FIELD 15w01 OA1EN (rw): Own address 1 enable
0x4000540C B REGISTER OAR2 (rw): I2C own address 2 register
0x4000540C C FIELD 01w07 OA2 (rw): Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN = 0.
0x4000540C C FIELD 08w03 OA2MSK (rw): Own address 2 masks
0x4000540C C FIELD 15w01 OA2EN (rw): Own address 2 enable
0x40005410 B REGISTER TIMINGR (rw): I2C timing register
0x40005410 C FIELD 00w08 SCLL (rw): SCL low period (master mode) This field is used to generate the SCL low period in master mode. t<sub>SCLL </sub>= (SCLL + 1) x t<sub>PRESC</sub> Note: SCLL is also used to generate t<sub>BUF </sub>and t<sub>SU:STA </sub>timings.
0x40005410 C FIELD 08w08 SCLH (rw): SCL high period (master mode) This field is used to generate the SCL high period in master mode. t<sub>SCLH </sub>= (SCLH + 1) x t<sub>PRESC</sub> Note: SCLH is also used to generate t<sub>SU:STO </sub>and t<sub>HD:STA </sub>timing.
0x40005410 C FIELD 16w04 SDADEL (rw): Data hold time This field is used to generate the delay t<sub>SDADEL </sub>between SCL falling edge and SDA edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SDADEL</sub>. t<sub>SDADEL</sub>= SDADEL x t<sub>PRESC</sub> Note: SDADEL is used to generate t<sub>HD:DAT </sub>timing.
0x40005410 C FIELD 20w04 SCLDEL (rw): Data setup time This field is used to generate a delay t<sub>SCLDEL</sub> = (SCLDEL + 1) x t<sub>PRESC</sub> between SDA edge and SCL rising edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SCLDEL</sub>. Note: t<sub>SCLDEL</sub> is used to generate t<sub>SU:DAT </sub>timing.
0x40005410 C FIELD 28w04 PRESC (rw): Timing prescaler This field is used to prescale I2CCLK to generate the clock period t<sub>PRESC </sub>used for data setup and hold counters (refer to I2C timings), and for SCL high and low level counters (refer to I2C master initialization). t<sub>PRESC </sub>= (PRESC + 1) x t<sub>I2CCLK</sub>
0x40005414 B REGISTER TIMEOUTR (rw): I2C timeout register
0x40005414 C FIELD 00w12 TIMEOUTA (rw): Bus timeout A This field is used to configure: The SCL low timeout condition t<sub>TIMEOUT</sub> when TIDLE = 0 t<sub>TIMEOUT</sub>= (TIMEOUTA + 1) x 2048 x t<sub>I2CCLK</sub> The bus idle condition (both SCL and SDA high) when TIDLE = 1 t<sub>IDLE</sub>= (TIMEOUTA + 1) x 4 x t<sub>I2CCLK</sub> Note: These bits can be written only when TIMOUTEN = 0.
0x40005414 C FIELD 12w01 TIDLE (rw): Idle clock timeout detection Note: This bit can be written only when TIMOUTEN = 0.
0x40005414 C FIELD 15w01 TIMOUTEN (rw): Clock timeout enable
0x40005414 C FIELD 16w12 TIMEOUTB (rw): Bus timeout B This field is used to configure the cumulative clock extension timeout: Master mode: the master cumulative clock low extend time (t<sub>LOW:MEXT</sub>) is detected Slave mode: the slave cumulative clock low extend time (t<sub>LOW:SEXT</sub>) is detected t<sub>LOW:EXT </sub>= (TIMEOUTB + TIDLE = 01) x 2048 x t<sub>I2CCLK</sub> Note: These bits can be written only when TEXTEN = 0.
0x40005414 C FIELD 31w01 TEXTEN (rw): Extended clock timeout enable
0x40005418 B REGISTER ISR (rw): I2C interrupt and status register
0x40005418 C FIELD 00w01 TXE (rw): Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE = 0.
0x40005418 C FIELD 01w01 TXIS (rw): Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software only when NOSTRETCH = 1, to generate a TXIS event (interrupt if TXIE = 1 or DMA request if TXDMAEN = 1). Note: This bit is cleared by hardware when PE = 0.
0x40005418 C FIELD 02w01 RXNE (ro): Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE = 0.
0x40005418 C FIELD 03w01 ADDR (ro): Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005418 C FIELD 04w01 NACKF (ro): Not acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005418 C FIELD 05w01 STOPF (ro): Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: as a master, provided that the STOP condition is generated by the peripheral. as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005418 C FIELD 06w01 TC (ro): Transfer complete (master mode) This flag is set by hardware when RELOAD = 0, AUTOEND = 0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE = 0.
0x40005418 C FIELD 07w01 TCR (ro): Transfer complete reload This flag is set by hardware when RELOAD = 1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE = 0. Note: This flag is only for master mode, or for slave mode when the SBC bit is set.
0x40005418 C FIELD 08w01 BERR (ro): Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting the BERRCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005418 C FIELD 09w01 ARLO (ro): Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005418 C FIELD 10w01 OVR (ro): Overrun/underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005418 C FIELD 11w01 PECERR (ro): PEC error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005418 C FIELD 12w01 TIMEOUT (ro): Timeout or t<sub>LOW</sub> detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005418 C FIELD 13w01 ALERT (ro): SMBus alert This flag is set by hardware when SMBHEN = 1 (SMBus host configuration), ALERTEN = 1 and an SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005418 C FIELD 15w01 BUSY (ro): Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected, and cleared by hardware when a STOP condition is detected, or when PE = 0.
0x40005418 C FIELD 16w01 DIR (ro): Transfer direction (slave mode) This flag is updated when an address match event occurs (ADDR = 1).
0x40005418 C FIELD 17w07 ADDCODE (ro): Address match code (slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the two MSBs of the address.
0x4000541C B REGISTER ICR (wo): I2C interrupt clear register
0x4000541C C FIELD 03w01 ADDRCF (wo): Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register.
0x4000541C C FIELD 04w01 NACKCF (wo): Not acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register.
0x4000541C C FIELD 05w01 STOPCF (wo): STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.
0x4000541C C FIELD 08w01 BERRCF (wo): Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
0x4000541C C FIELD 09w01 ARLOCF (wo): Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.
0x4000541C C FIELD 10w01 OVRCF (wo): Overrun/underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
0x4000541C C FIELD 11w01 PECCF (wo): PEC error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x4000541C C FIELD 12w01 TIMOUTCF (wo): Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x4000541C C FIELD 13w01 ALERTCF (wo): Alert flag clear Note: Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005420 B REGISTER PECR (ro): I2C PEC register
0x40005420 C FIELD 00w08 PEC (ro): Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE = 0.
0x40005424 B REGISTER RXDR (ro): I2C receive data register
0x40005424 C FIELD 00w08 RXDATA (ro): 8-bit receive data Data byte received from the I<sup>2</sup>C bus
0x40005428 B REGISTER TXDR (rw): I2C transmit data register
0x40005428 C FIELD 00w08 TXDATA (rw): 8-bit transmit data Data byte to be transmitted to the I<sup>2</sup>C bus Note: These bits can be written only when TXE = 1.
0x40005800 A PERIPHERAL I2C2
0x40005800 B REGISTER CR1 (rw): I2C control register 1
0x40005800 C FIELD 00w01 PE (rw): Peripheral enable Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least three APB clock cycles.
0x40005800 C FIELD 01w01 TXIE (rw): TX interrupt enable
0x40005800 C FIELD 02w01 RXIE (rw): RX interrupt enable
0x40005800 C FIELD 03w01 ADDRIE (rw): Address match interrupt enable (slave only)
0x40005800 C FIELD 04w01 NACKIE (rw): Not acknowledge received interrupt enable
0x40005800 C FIELD 05w01 STOPIE (rw): Stop detection interrupt enable
0x40005800 C FIELD 06w01 TCIE (rw): Transfer complete interrupt enable Note: Any of these events generates an interrupt: Note: Transfer complete (TC) Note: Transfer complete reload (TCR)
0x40005800 C FIELD 07w01 ERRIE (rw): Error interrupts enable Note: Any of these errors generates an interrupt: Note: Arbitration loss (ARLO) Note: Bus error detection (BERR) Note: Overrun/underrun (OVR) Note: Timeout detection (TIMEOUT) Note: PEC error detection (PECERR) Note: Alert pin event detection (ALERT)
0x40005800 C FIELD 08w04 DNF (rw): Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * t<sub>I2CCLK</sub> ... Note: If the analog filter is enabled, the digital filter is added to it. This filter can be programmed only when the I2C is disabled (PE = 0).
0x40005800 C FIELD 12w01 ANFOFF (rw): Analog noise filter OFF Note: This bit can be programmed only when the I2C is disabled (PE = 0).
0x40005800 C FIELD 14w01 TXDMAEN (rw): DMA transmission requests enable
0x40005800 C FIELD 15w01 RXDMAEN (rw): DMA reception requests enable
0x40005800 C FIELD 16w01 SBC (rw): Slave byte control This bit is used to enable hardware byte control in slave mode.
0x40005800 C FIELD 17w01 NOSTRETCH (rw): Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can be programmed only when the I2C is disabled (PE = 0).
0x40005800 C FIELD 18w01 WUPEN (rw): Wake-up from Stop mode enable Note: If the wake-up from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3. Note: WUPEN can be set only when DNF = 0000.
0x40005800 C FIELD 19w01 GCEN (rw): General call enable
0x40005800 C FIELD 20w01 SMBHEN (rw): SMBus host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005800 C FIELD 21w01 SMBDEN (rw): SMBus device default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005800 C FIELD 22w01 ALERTEN (rw): SMBus alert enable Note: When ALERTEN = 0, the SMBA pin can be used as a standard GPIO. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005800 C FIELD 23w01 PECEN (rw): PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005804 B REGISTER CR2 (rw): I2C control register 2
0x40005804 C FIELD 00w10 SADD (rw): Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] must be written with the 7-bit slave address to be sent. Bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] must be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed.
0x40005804 C FIELD 10w01 RD_WRN (rw): Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005804 C FIELD 11w01 ADD10 (rw): 10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005804 C FIELD 12w01 HEAD10R (rw): 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed.
0x40005804 C FIELD 13w01 START (rw): Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by an address matched in slave mode, by a timeout error detection, or when PE = 0. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated start condition when RELOAD = 0, after the end of the NBYTES transfer. Otherwise, setting this bit generates a START condition once the bus is free. Note: Writing 0 to this bit has no effect. Note: The START bit can be set even if the bus is BUSY or I2C is in slave mode. Note: This bit has no effect when RELOAD is set.
0x40005804 C FIELD 14w01 STOP (rw): Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In master mode: Note: Writing 0 to this bit has no effect.
0x40005804 C FIELD 15w01 NACK (rw): NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0. Note: Writing 0 to this bit has no effect. Note: This bit is used only in slave mode: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. Note: When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated, whatever the NACK bit value. Note: When hardware PEC checking is enabled (PECBYTE = 1), the PEC acknowledge value does not depend on the NACK value.
0x40005804 C FIELD 16w08 NBYTES (rw): Number of bytes The number of bytes to be transmitted/received is programmed there. This field is don t care in slave mode with SBC = 0. Note: Changing these bits when the START bit is set is not allowed.
0x40005804 C FIELD 24w01 RELOAD (rw): NBYTES reload mode This bit is set and cleared by software.
0x40005804 C FIELD 25w01 AUTOEND (rw): Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set.
0x40005804 C FIELD 26w01 PECBYTE (rw): Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0. Note: Writing 0 to this bit has no effect. Note: This bit has no effect when RELOAD is set, and in slave mode when SBC = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005808 B REGISTER OAR1 (rw): I2C own address 1 register
0x40005808 C FIELD 00w10 OA1 (rw): Interface own slave address 7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. Bits OA1[9], OA1[8] and OA1[0] are don't care. 10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address. Note: These bits can be written only when OA1EN = 0.
0x40005808 C FIELD 10w01 OA1MODE (rw): Own address 1 10-bit mode Note: This bit can be written only when OA1EN = 0.
0x40005808 C FIELD 15w01 OA1EN (rw): Own address 1 enable
0x4000580C B REGISTER OAR2 (rw): I2C own address 2 register
0x4000580C C FIELD 01w07 OA2 (rw): Interface address 7-bit addressing mode: 7-bit address Note: These bits can be written only when OA2EN = 0.
0x4000580C C FIELD 08w03 OA2MSK (rw): Own address 2 masks
0x4000580C C FIELD 15w01 OA2EN (rw): Own address 2 enable
0x40005810 B REGISTER TIMINGR (rw): I2C timing register
0x40005810 C FIELD 00w08 SCLL (rw): SCL low period (master mode) This field is used to generate the SCL low period in master mode. t<sub>SCLL </sub>= (SCLL + 1) x t<sub>PRESC</sub> Note: SCLL is also used to generate t<sub>BUF </sub>and t<sub>SU:STA </sub>timings.
0x40005810 C FIELD 08w08 SCLH (rw): SCL high period (master mode) This field is used to generate the SCL high period in master mode. t<sub>SCLH </sub>= (SCLH + 1) x t<sub>PRESC</sub> Note: SCLH is also used to generate t<sub>SU:STO </sub>and t<sub>HD:STA </sub>timing.
0x40005810 C FIELD 16w04 SDADEL (rw): Data hold time This field is used to generate the delay t<sub>SDADEL </sub>between SCL falling edge and SDA edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SDADEL</sub>. t<sub>SDADEL</sub>= SDADEL x t<sub>PRESC</sub> Note: SDADEL is used to generate t<sub>HD:DAT </sub>timing.
0x40005810 C FIELD 20w04 SCLDEL (rw): Data setup time This field is used to generate a delay t<sub>SCLDEL</sub> = (SCLDEL + 1) x t<sub>PRESC</sub> between SDA edge and SCL rising edge. In master and in slave modes with NOSTRETCH = 0, the SCL line is stretched low during t<sub>SCLDEL</sub>. Note: t<sub>SCLDEL</sub> is used to generate t<sub>SU:DAT </sub>timing.
0x40005810 C FIELD 28w04 PRESC (rw): Timing prescaler This field is used to prescale I2CCLK to generate the clock period t<sub>PRESC </sub>used for data setup and hold counters (refer to I2C timings), and for SCL high and low level counters (refer to I2C master initialization). t<sub>PRESC </sub>= (PRESC + 1) x t<sub>I2CCLK</sub>
0x40005814 B REGISTER TIMEOUTR (rw): I2C timeout register
0x40005814 C FIELD 00w12 TIMEOUTA (rw): Bus timeout A This field is used to configure: The SCL low timeout condition t<sub>TIMEOUT</sub> when TIDLE = 0 t<sub>TIMEOUT</sub>= (TIMEOUTA + 1) x 2048 x t<sub>I2CCLK</sub> The bus idle condition (both SCL and SDA high) when TIDLE = 1 t<sub>IDLE</sub>= (TIMEOUTA + 1) x 4 x t<sub>I2CCLK</sub> Note: These bits can be written only when TIMOUTEN = 0.
0x40005814 C FIELD 12w01 TIDLE (rw): Idle clock timeout detection Note: This bit can be written only when TIMOUTEN = 0.
0x40005814 C FIELD 15w01 TIMOUTEN (rw): Clock timeout enable
0x40005814 C FIELD 16w12 TIMEOUTB (rw): Bus timeout B This field is used to configure the cumulative clock extension timeout: Master mode: the master cumulative clock low extend time (t<sub>LOW:MEXT</sub>) is detected Slave mode: the slave cumulative clock low extend time (t<sub>LOW:SEXT</sub>) is detected t<sub>LOW:EXT </sub>= (TIMEOUTB + TIDLE = 01) x 2048 x t<sub>I2CCLK</sub> Note: These bits can be written only when TEXTEN = 0.
0x40005814 C FIELD 31w01 TEXTEN (rw): Extended clock timeout enable
0x40005818 B REGISTER ISR (rw): I2C interrupt and status register
0x40005818 C FIELD 00w01 TXE (rw): Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE = 0.
0x40005818 C FIELD 01w01 TXIS (rw): Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software only when NOSTRETCH = 1, to generate a TXIS event (interrupt if TXIE = 1 or DMA request if TXDMAEN = 1). Note: This bit is cleared by hardware when PE = 0.
0x40005818 C FIELD 02w01 RXNE (ro): Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE = 0.
0x40005818 C FIELD 03w01 ADDR (ro): Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005818 C FIELD 04w01 NACKF (ro): Not acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005818 C FIELD 05w01 STOPF (ro): Stop detection flag This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer: as a master, provided that the STOP condition is generated by the peripheral. as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005818 C FIELD 06w01 TC (ro): Transfer complete (master mode) This flag is set by hardware when RELOAD = 0, AUTOEND = 0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE = 0.
0x40005818 C FIELD 07w01 TCR (ro): Transfer complete reload This flag is set by hardware when RELOAD = 1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE = 0. Note: This flag is only for master mode, or for slave mode when the SBC bit is set.
0x40005818 C FIELD 08w01 BERR (ro): Bus error This flag is set by hardware when a misplaced Start or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting the BERRCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005818 C FIELD 09w01 ARLO (ro): Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005818 C FIELD 10w01 OVR (ro): Overrun/underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE = 0.
0x40005818 C FIELD 11w01 PECERR (ro): PEC error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005818 C FIELD 12w01 TIMEOUT (ro): Timeout or t<sub>LOW</sub> detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005818 C FIELD 13w01 ALERT (ro): SMBus alert This flag is set by hardware when SMBHEN = 1 (SMBus host configuration), ALERTEN = 1 and an SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE = 0. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005818 C FIELD 15w01 BUSY (ro): Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected, and cleared by hardware when a STOP condition is detected, or when PE = 0.
0x40005818 C FIELD 16w01 DIR (ro): Transfer direction (slave mode) This flag is updated when an address match event occurs (ADDR = 1).
0x40005818 C FIELD 17w07 ADDCODE (ro): Address match code (slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the two MSBs of the address.
0x4000581C B REGISTER ICR (wo): I2C interrupt clear register
0x4000581C C FIELD 03w01 ADDRCF (wo): Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register.
0x4000581C C FIELD 04w01 NACKCF (wo): Not acknowledge flag clear Writing 1 to this bit clears the NACKF flag in I2C_ISR register.
0x4000581C C FIELD 05w01 STOPCF (wo): STOP detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.
0x4000581C C FIELD 08w01 BERRCF (wo): Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
0x4000581C C FIELD 09w01 ARLOCF (wo): Arbitration lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.
0x4000581C C FIELD 10w01 OVRCF (wo): Overrun/underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
0x4000581C C FIELD 11w01 PECCF (wo): PEC error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x4000581C C FIELD 12w01 TIMOUTCF (wo): Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x4000581C C FIELD 13w01 ALERTCF (wo): Alert flag clear Note: Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Refer to Section 25.3.
0x40005820 B REGISTER PECR (ro): I2C PEC register
0x40005820 C FIELD 00w08 PEC (ro): Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE = 0.
0x40005824 B REGISTER RXDR (ro): I2C receive data register
0x40005824 C FIELD 00w08 RXDATA (ro): 8-bit receive data Data byte received from the I<sup>2</sup>C bus
0x40005828 B REGISTER TXDR (rw): I2C transmit data register
0x40005828 C FIELD 00w08 TXDATA (rw): 8-bit transmit data Data byte to be transmitted to the I<sup>2</sup>C bus Note: These bits can be written only when TXE = 1.
0x40005C00 A PERIPHERAL USB
0x40005C00 B REGISTER CHEP0R (rw): USB endpoint/channel 0 register
0x40005C00 C FIELD 00w04 EA (rw): endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction.
0x40005C00 C FIELD 04w02 STATTX (wo): Status bits, for transmission transfers
0x40005C00 C FIELD 06w01 DTOGTX (wo): Data toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1.
0x40005C00 C FIELD 07w01 VTTX (rw): Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written. Host mode Same as VTRX behavior but for USB OUT and SETUP transactions.
0x40005C00 C FIELD 08w01 EPKIND (rw): endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required.
0x40005C00 C FIELD 09w02 UTYPE (rw): USB type of transaction These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode
0x40005C00 C FIELD 11w01 SETUP (ro): Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated.
0x40005C00 C FIELD 12w02 STATRX (wo): Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate.
0x40005C00 C FIELD 14w01 DTOGRX (wo): Data Toggle, for reception transfers If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1.
0x40005C00 C FIELD 15w01 VTRX (rw): USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. - A transaction ended with error sets this bit. Errors can be seen via the bits ERR_RX (host mode only). This bit is read/write but only 0 can be written, writing 1 has no effect.
0x40005C00 C FIELD 16w07 DEVADDR (rw): Host mode Device address assigned to the endpoint during the enumeration process.
0x40005C00 C FIELD 23w01 NAK (rw): Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device.
0x40005C00 C FIELD 24w01 LS_EP (rw): Low speed endpoint
0x40005C00 C FIELD 25w01 ERR_TX (rw): Received error for an OUT/SETUP transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C00 C FIELD 26w01 ERR_RX (rw): Received error for an IN transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C00 C FIELD 27w02 THREE_ERR_TX (rw): Three errors for an OUT or SETUP transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C00 C FIELD 29w02 THREE_ERR_RX (rw): Three errors for an IN transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C04 B REGISTER CHEP1R (rw): USB endpoint/channel 1 register
0x40005C04 C FIELD 00w04 EA (rw): endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction.
0x40005C04 C FIELD 04w02 STATTX (wo): Status bits, for transmission transfers
0x40005C04 C FIELD 06w01 DTOGTX (wo): Data toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1.
0x40005C04 C FIELD 07w01 VTTX (rw): Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written. Host mode Same as VTRX behavior but for USB OUT and SETUP transactions.
0x40005C04 C FIELD 08w01 EPKIND (rw): endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required.
0x40005C04 C FIELD 09w02 UTYPE (rw): USB type of transaction These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode
0x40005C04 C FIELD 11w01 SETUP (ro): Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated.
0x40005C04 C FIELD 12w02 STATRX (wo): Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate.
0x40005C04 C FIELD 14w01 DTOGRX (wo): Data Toggle, for reception transfers If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1.
0x40005C04 C FIELD 15w01 VTRX (rw): USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. - A transaction ended with error sets this bit. Errors can be seen via the bits ERR_RX (host mode only). This bit is read/write but only 0 can be written, writing 1 has no effect.
0x40005C04 C FIELD 16w07 DEVADDR (rw): Host mode Device address assigned to the endpoint during the enumeration process.
0x40005C04 C FIELD 23w01 NAK (rw): Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device.
0x40005C04 C FIELD 24w01 LS_EP (rw): Low speed endpoint
0x40005C04 C FIELD 25w01 ERR_TX (rw): Received error for an OUT/SETUP transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C04 C FIELD 26w01 ERR_RX (rw): Received error for an IN transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C04 C FIELD 27w02 THREE_ERR_TX (rw): Three errors for an OUT or SETUP transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C04 C FIELD 29w02 THREE_ERR_RX (rw): Three errors for an IN transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C08 B REGISTER CHEP2R (rw): USB endpoint/channel 2 register
0x40005C08 C FIELD 00w04 EA (rw): endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction.
0x40005C08 C FIELD 04w02 STATTX (wo): Status bits, for transmission transfers
0x40005C08 C FIELD 06w01 DTOGTX (wo): Data toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1.
0x40005C08 C FIELD 07w01 VTTX (rw): Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written. Host mode Same as VTRX behavior but for USB OUT and SETUP transactions.
0x40005C08 C FIELD 08w01 EPKIND (rw): endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required.
0x40005C08 C FIELD 09w02 UTYPE (rw): USB type of transaction These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode
0x40005C08 C FIELD 11w01 SETUP (ro): Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated.
0x40005C08 C FIELD 12w02 STATRX (wo): Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate.
0x40005C08 C FIELD 14w01 DTOGRX (wo): Data Toggle, for reception transfers If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1.
0x40005C08 C FIELD 15w01 VTRX (rw): USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. - A transaction ended with error sets this bit. Errors can be seen via the bits ERR_RX (host mode only). This bit is read/write but only 0 can be written, writing 1 has no effect.
0x40005C08 C FIELD 16w07 DEVADDR (rw): Host mode Device address assigned to the endpoint during the enumeration process.
0x40005C08 C FIELD 23w01 NAK (rw): Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device.
0x40005C08 C FIELD 24w01 LS_EP (rw): Low speed endpoint
0x40005C08 C FIELD 25w01 ERR_TX (rw): Received error for an OUT/SETUP transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C08 C FIELD 26w01 ERR_RX (rw): Received error for an IN transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C08 C FIELD 27w02 THREE_ERR_TX (rw): Three errors for an OUT or SETUP transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C08 C FIELD 29w02 THREE_ERR_RX (rw): Three errors for an IN transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C0C B REGISTER CHEP3R (rw): USB endpoint/channel 3 register
0x40005C0C C FIELD 00w04 EA (rw): endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction.
0x40005C0C C FIELD 04w02 STATTX (wo): Status bits, for transmission transfers
0x40005C0C C FIELD 06w01 DTOGTX (wo): Data toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1.
0x40005C0C C FIELD 07w01 VTTX (rw): Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written. Host mode Same as VTRX behavior but for USB OUT and SETUP transactions.
0x40005C0C C FIELD 08w01 EPKIND (rw): endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required.
0x40005C0C C FIELD 09w02 UTYPE (rw): USB type of transaction These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode
0x40005C0C C FIELD 11w01 SETUP (ro): Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated.
0x40005C0C C FIELD 12w02 STATRX (wo): Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate.
0x40005C0C C FIELD 14w01 DTOGRX (wo): Data Toggle, for reception transfers If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1.
0x40005C0C C FIELD 15w01 VTRX (rw): USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. - A transaction ended with error sets this bit. Errors can be seen via the bits ERR_RX (host mode only). This bit is read/write but only 0 can be written, writing 1 has no effect.
0x40005C0C C FIELD 16w07 DEVADDR (rw): Host mode Device address assigned to the endpoint during the enumeration process.
0x40005C0C C FIELD 23w01 NAK (rw): Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device.
0x40005C0C C FIELD 24w01 LS_EP (rw): Low speed endpoint
0x40005C0C C FIELD 25w01 ERR_TX (rw): Received error for an OUT/SETUP transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C0C C FIELD 26w01 ERR_RX (rw): Received error for an IN transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C0C C FIELD 27w02 THREE_ERR_TX (rw): Three errors for an OUT or SETUP transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C0C C FIELD 29w02 THREE_ERR_RX (rw): Three errors for an IN transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C10 B REGISTER CHEP4R (rw): USB endpoint/channel 4 register
0x40005C10 C FIELD 00w04 EA (rw): endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction.
0x40005C10 C FIELD 04w02 STATTX (wo): Status bits, for transmission transfers
0x40005C10 C FIELD 06w01 DTOGTX (wo): Data toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1.
0x40005C10 C FIELD 07w01 VTTX (rw): Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written. Host mode Same as VTRX behavior but for USB OUT and SETUP transactions.
0x40005C10 C FIELD 08w01 EPKIND (rw): endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required.
0x40005C10 C FIELD 09w02 UTYPE (rw): USB type of transaction These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode
0x40005C10 C FIELD 11w01 SETUP (ro): Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated.
0x40005C10 C FIELD 12w02 STATRX (wo): Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate.
0x40005C10 C FIELD 14w01 DTOGRX (wo): Data Toggle, for reception transfers If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1.
0x40005C10 C FIELD 15w01 VTRX (rw): USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. - A transaction ended with error sets this bit. Errors can be seen via the bits ERR_RX (host mode only). This bit is read/write but only 0 can be written, writing 1 has no effect.
0x40005C10 C FIELD 16w07 DEVADDR (rw): Host mode Device address assigned to the endpoint during the enumeration process.
0x40005C10 C FIELD 23w01 NAK (rw): Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device.
0x40005C10 C FIELD 24w01 LS_EP (rw): Low speed endpoint
0x40005C10 C FIELD 25w01 ERR_TX (rw): Received error for an OUT/SETUP transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C10 C FIELD 26w01 ERR_RX (rw): Received error for an IN transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C10 C FIELD 27w02 THREE_ERR_TX (rw): Three errors for an OUT or SETUP transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C10 C FIELD 29w02 THREE_ERR_RX (rw): Three errors for an IN transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C14 B REGISTER CHEP5R (rw): USB endpoint/channel 5 register
0x40005C14 C FIELD 00w04 EA (rw): endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction.
0x40005C14 C FIELD 04w02 STATTX (wo): Status bits, for transmission transfers
0x40005C14 C FIELD 06w01 DTOGTX (wo): Data toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1.
0x40005C14 C FIELD 07w01 VTTX (rw): Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written. Host mode Same as VTRX behavior but for USB OUT and SETUP transactions.
0x40005C14 C FIELD 08w01 EPKIND (rw): endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required.
0x40005C14 C FIELD 09w02 UTYPE (rw): USB type of transaction These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode
0x40005C14 C FIELD 11w01 SETUP (ro): Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated.
0x40005C14 C FIELD 12w02 STATRX (wo): Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate.
0x40005C14 C FIELD 14w01 DTOGRX (wo): Data Toggle, for reception transfers If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1.
0x40005C14 C FIELD 15w01 VTRX (rw): USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. - A transaction ended with error sets this bit. Errors can be seen via the bits ERR_RX (host mode only). This bit is read/write but only 0 can be written, writing 1 has no effect.
0x40005C14 C FIELD 16w07 DEVADDR (rw): Host mode Device address assigned to the endpoint during the enumeration process.
0x40005C14 C FIELD 23w01 NAK (rw): Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device.
0x40005C14 C FIELD 24w01 LS_EP (rw): Low speed endpoint
0x40005C14 C FIELD 25w01 ERR_TX (rw): Received error for an OUT/SETUP transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C14 C FIELD 26w01 ERR_RX (rw): Received error for an IN transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C14 C FIELD 27w02 THREE_ERR_TX (rw): Three errors for an OUT or SETUP transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C14 C FIELD 29w02 THREE_ERR_RX (rw): Three errors for an IN transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an IN transaction. THREE_ERR_RX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error:
0x40005C18 B REGISTER CHEP6R (rw): USB endpoint/channel 6 register
0x40005C18 C FIELD 00w04 EA (rw): endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction.
0x40005C18 C FIELD 04w02 STATTX (wo): Status bits, for transmission transfers
0x40005C18 C FIELD 06w01 DTOGTX (wo): Data toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint (in device mode) or when a SETUP transaction is acknowledged by the device (in host mode). If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGTX remains unchanged, while writing 1 makes the bit value to toggle. This bit is read/write but it can only be toggled by writing 1.
0x40005C18 C FIELD 07w01 VTTX (rw): Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written. Host mode Same as VTRX behavior but for USB OUT and SETUP transactions.
0x40005C18 C FIELD 08w01 EPKIND (rw): endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the UTYPE bits. Table 142 summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Section 28.5.3: Double-buffered endpoints and usage in Device mode. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered STALL instead of ACK . This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required.
0x40005C18 C FIELD 09w02 UTYPE (rw): USB type of transaction These bits configure the behavior of this endpoint/channel as described in Table 141: Endpoint/channel type encoding. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral does not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet is accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of isochronous channels/endpoints is explained in Section 28.5.5: Isochronous transfers in Device mode
0x40005C18 C FIELD 11w01 SETUP (ro): Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated.
0x40005C18 C FIELD 12w02 STATRX (wo): Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Table 140: Reception status encoding on page 881. These bits can be toggled by software to initialize their value. When the application software writes 0, the value remains unchanged, while writing 1 makes the bit value to toggle. Hardware sets the STATRX bits to NAK when a correct transfer has occurred (VTRX = 1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledges a new transaction. Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint is defined as isochronous, its status can be only VALID or DISABLED , so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STATRX bits to STALL or NAK for an isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing 1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STATRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the host execution list. If the aborted transaction was already under execution it is regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID A host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the host frame scheduler to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel is re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application must not retry transmission but reset the USB and re-enumerate.
0x40005C18 C FIELD 14w01 DTOGRX (wo): Data Toggle, for reception transfers If the endpoint/channel is not isochronous, this bit contains the expected value of the data toggle bit (0 = DATA0, 1 = DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device mode), while it sets this bit to 1 when SETUP transaction is acknowledged by device (in host mode). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to Section 28.5.3: Double-buffered endpoints and usage in Device mode). If the endpoint/channel is isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Section 28.5.5: Isochronous transfers in Device mode). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes 0, the value of DTOGRX remains unchanged, while writing 1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1.
0x40005C18 C FIELD 15w01 VTRX (rw): USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only 0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the CTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STATRX field of this register. One NAKed transaction keeps pending and is automatically retried by the host at the next frame, or the host can immediately retry by resetting STATRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STATRX field of this register. Host application must consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STATRX field of this register. Host application must read received data from USBRAM and re-arm the channel by writing VALID to the STATRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STATRX field of this register. Host application must read received data from USBRAM and toggle the DTOGTX bit of this register. - A transaction ended with error sets this bit. Errors can be seen via the bits ERR_RX (host mode only). This bit is read/write but only 0 can be written, writing 1 has no effect.
0x40005C18 C FIELD 16w07 DEVADDR (rw): Host mode Device address assigned to the endpoint during the enumeration process.
0x40005C18 C FIELD 23w01 NAK (rw): Host mode This bit is set by the hardware when a device responds with a NAK. Software can use this bit to monitor the number of NAKs received from a device.
0x40005C18 C FIELD 24w01 LS_EP (rw): Low speed endpoint
0x40005C18 C FIELD 25w01 ERR_TX (rw): Received error for an OUT/SETUP transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C18 C FIELD 26w01 ERR_RX (rw): Received error for an IN transaction Host mode This bit is set by the hardware when an error (for example no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set, a generic interrupt condition is generated together with the channel related flag, which is always activated.
0x40005C18 C FIELD 27w02 THREE_ERR_TX (rw): Three errors for an OUT or SETUP transaction Host mode This bit is set by the hardware when 3 consecutive transaction errors occurred on the USB bus for an OUT transaction. THREE_ERR_TX is not generated for isochronous transactions. The software can only clear this bit. Coding of the received error: