Merge pull request #1117 from slaclab/Idelaye3Wrapper-revent

Release Candidate v2.45.2
slaclab · Sep 27, 2023 · d92f7c4 · d92f7c4
2 parents c7c4294 + 19890f2
commit d92f7c4
Showing 1 changed file with 1 addition and 5 deletions.
diff --git a/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd b/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd
@@ -37,8 +37,7 @@ entity Idelaye3Wrapper is
       IS_RST_INVERTED  : bit     := '0';  -- Optional inversion for RST
       REFCLK_FREQUENCY : real    := 300.0;  -- IDELAYCTRL clock input frequency in MHz (200.0-2667.0)
       SIM_DEVICE       : string  := "ULTRASCALE";  -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS)
-      UPDATE_MODE      : string  := "ASYNC";
-      IODELAY_GROUP_G  : string  := "DLYGRP_C");  -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
+      UPDATE_MODE      : string  := "ASYNC");  -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
    port (
       BUSY        : out sl;             -- 1-bit output: Patch module is busy
       CASC_OUT    : out sl;  -- 1-bit output: Cascade delay output to ODELAY input cascade
@@ -63,9 +62,6 @@ architecture rtl of Idelaye3Wrapper is
    signal patchCntValue   : slv(8 downto 0);
    signal patchLoad       : sl;
 
-   attribute IODELAY_GROUP            : string;
-   attribute IODELAY_GROUP of U_IDELAYE3 : label is IODELAY_GROUP_G;
-
 begin
 
    CNTVALUEOUT <= currentCntValue;