diff --git a/ethernet/EthMacCore/rtl/EthMacRx.vhd b/ethernet/EthMacCore/rtl/EthMacRx.vhd index 884629187f..4b215cfde7 100644 --- a/ethernet/EthMacCore/rtl/EthMacRx.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRx.vhd @@ -31,6 +31,7 @@ entity EthMacRx is PHY_TYPE_G : string := "XGMII"; JUMBO_G : boolean := true; -- Misc. Configurations + ROCEV2_EN_G : boolean := false; FILT_EN_G : boolean := false; BYP_EN_G : boolean := false; BYP_ETH_TYPE_G : slv(15 downto 0) := x"0000"; @@ -131,8 +132,9 @@ begin --------------------- U_Csum : entity surf.EthMacRxCsum generic map ( - TPD_G => TPD_G, - JUMBO_G => JUMBO_G) + TPD_G => TPD_G, + JUMBO_G => JUMBO_G, + ROCEV2_EN_G => ROCEV2_EN_G) port map ( -- Clock and Reset ethClk => ethClk, @@ -148,17 +150,23 @@ begin -------------------------------- -- RoCEv2 Protocol iCRC Checking -------------------------------- - U_RoCEv2 : entity surf.EthMacRxRoCEv2 - generic map ( - TPD_G => TPD_G) - port map ( - -- Clock and Reset - ethClk => ethClk, - ethRst => ethRst, - -- Checksum Interface - obCsumMaster => obCsumMaster, - -- Bypass Interface - ibBypassMaster => ibBypassMaster); + GEN_RoCEv2 : if (ROCEV2_EN_G = true) generate + U_RoCEv2 : entity surf.EthMacRxRoCEv2 + generic map ( + TPD_G => TPD_G) + port map ( + -- Clock and Reset + ethClk => ethClk, + ethRst => ethRst, + -- Checksum Interface + obCsumMaster => obCsumMaster, + -- Bypass Interface + ibBypassMaster => ibBypassMaster); + end generate; + + BYPASS_RoCEv2 : if (ROCEV2_EN_G = false) generate + ibBypassMaster <= obCsumMaster; + end generate; ------------------- -- RX Bypass Module diff --git a/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd b/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd index d64c46ed3e..ffd3186cd2 100644 --- a/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd +++ b/ethernet/EthMacCore/rtl/EthMacRxCsum.vhd @@ -25,8 +25,9 @@ use surf.EthMacPkg.all; entity EthMacRxCsum is generic ( - TPD_G : time := 1 ns; - JUMBO_G : boolean := true); + TPD_G : time := 1 ns; + JUMBO_G : boolean := true; + ROCEV2_EN_G : boolean := false); port ( -- Clock and Reset ethClk : in sl; @@ -283,7 +284,7 @@ begin v.protLen(0)(15 downto 8) := sAxisMaster.tData(55 downto 48); v.protLen(0)(7 downto 0) := sAxisMaster.tData(63 downto 56); end if; - if sAxisMaster.tData(47 downto 32) = x"B712" then + if ROCEV2_EN_G and (sAxisMaster.tData(47 downto 32) = x"B712") then v.roce(0) := '1'; else v.roce(0) := '0'; @@ -356,6 +357,11 @@ begin axiStreamSetUserBit(INT_EMAC_AXIS_CONFIG_C, v.mAxisMasters(EMAC_CSUM_PIPELINE_C+1), EMAC_FRAG_BIT_C, r.fragDet(EMAC_CSUM_PIPELINE_C), 0); end if; + -- Outputs + mAxisMaster <= r.mAxisMasters(EMAC_CSUM_PIPELINE_C+1); + mAxisMaster.tDest(0) <= r.roce(EMAC_CSUM_PIPELINE_C); + dbg <= dummy; + -- Reset if (ethRst = '1') then v := REG_INIT_C; @@ -364,11 +370,6 @@ begin -- Register the variable for next clock cycle rin <= v; - -- Outputs - mAxisMaster <= r.mAxisMasters(EMAC_CSUM_PIPELINE_C+1); - mAxisMaster.tDest(0) <= r.roce(EMAC_CSUM_PIPELINE_C); - dbg <= dummy; - end process comb; seq : process (ethClk) is diff --git a/ethernet/EthMacCore/rtl/EthMacTop.vhd b/ethernet/EthMacCore/rtl/EthMacTop.vhd index 3a87fc95c6..cf2dc986b3 100644 --- a/ethernet/EthMacCore/rtl/EthMacTop.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTop.vhd @@ -39,6 +39,7 @@ entity EthMacTop is SYNTH_MODE_G : string := "inferred"; MEMORY_TYPE_G : string := "block"; -- Misc. Configurations + ROCEV2_EN_G : boolean := false; FILT_EN_G : boolean := false; PRIM_COMMON_CLK_G : boolean := false; PRIM_CONFIG_G : AxiStreamConfigType := EMAC_AXIS_CONFIG_C; @@ -159,6 +160,7 @@ begin DROP_ERR_PKT_G => DROP_ERR_PKT_G, JUMBO_G => JUMBO_G, -- Misc. Configurations + ROCEV2_EN_G => ROCEV2_EN_G, BYP_EN_G => BYP_EN_G, -- RAM sythesis Mode SYNTH_MODE_G => SYNTH_MODE_G) @@ -224,6 +226,7 @@ begin PHY_TYPE_G => PHY_TYPE_G, JUMBO_G => JUMBO_G, -- Misc. Configurations + ROCEV2_EN_G => ROCEV2_EN_G, FILT_EN_G => FILT_EN_G, BYP_EN_G => BYP_EN_G, BYP_ETH_TYPE_G => BYP_ETH_TYPE_G, diff --git a/ethernet/EthMacCore/rtl/EthMacTx.vhd b/ethernet/EthMacCore/rtl/EthMacTx.vhd index 791443a875..0e04ebbcdb 100644 --- a/ethernet/EthMacCore/rtl/EthMacTx.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTx.vhd @@ -33,6 +33,7 @@ entity EthMacTx is DROP_ERR_PKT_G : boolean := true; JUMBO_G : boolean := true; -- Misc. Configurations + ROCEV2_EN_G : boolean := false; BYP_EN_G : boolean := false; -- RAM Synthesis mode SYNTH_MODE_G : string := "inferred"); @@ -114,7 +115,9 @@ begin generic map ( TPD_G => TPD_G, DROP_ERR_PKT_G => DROP_ERR_PKT_G, - JUMBO_G => JUMBO_G) + JUMBO_G => JUMBO_G, + ROCEV2_EN_G => ROCEV2_EN_G, + SYNTH_MODE_G => SYNTH_MODE_G) port map ( -- Clock and Reset ethClk => ethClk, @@ -132,19 +135,26 @@ begin --------------------------------- -- RoCEv2 Protocol iCRC insertion --------------------------------- - U_RoCEv2 : entity surf.EthMacTxRoCEv2 - generic map ( - TPD_G => TPD_G) - port map ( - -- Clock and Reset - ethClk => ethClk, - ethRst => ethRst, - -- Checksum Interface - obCsumMaster => obCsumMaster, - obCsumSlave => obCsumSlave, - -- Pause Interface - ibPauseMaster => ibPauseMaster, - ibPauseSlave => ibPauseSlave); + GEN_RoCEv2 : if (ROCEV2_EN_G = true) generate + U_RoCEv2 : entity surf.EthMacTxRoCEv2 + generic map ( + TPD_G => TPD_G) + port map ( + -- Clock and Reset + ethClk => ethClk, + ethRst => ethRst, + -- Checksum Interface + obCsumMaster => obCsumMaster, + obCsumSlave => obCsumSlave, + -- Pause Interface + ibPauseMaster => ibPauseMaster, + ibPauseSlave => ibPauseSlave); + end generate; + + BYPASS_RoCEv2 : if (ROCEV2_EN_G = false) generate + ibPauseMaster <= obCsumMaster; + obCsumSlave <= ibPauseSlave; + end generate; ------------------ -- TX Pause Module diff --git a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd index 1cbdd734ac..6a2695f59e 100644 --- a/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd +++ b/ethernet/EthMacCore/rtl/EthMacTxCsum.vhd @@ -28,6 +28,7 @@ entity EthMacTxCsum is TPD_G : time := 1 ns; DROP_ERR_PKT_G : boolean := true; JUMBO_G : boolean := true; + ROCEV2_EN_G : boolean := false; SYNTH_MODE_G : string := "inferred"); -- Synthesis mode for internal RAMs port ( -- Clock and Reset @@ -335,7 +336,7 @@ begin v.tData := rxMaster.tData(127 downto 80) & x"00000000" & rxMaster.tData(47 downto 0); end if; -- Track the number of bytes and check if its a RoCE transmission (UDP dst port = 4791) - if rxMaster.tData(47 downto 32) = x"B712" then + if ROCEV2_EN_G and (rxMaster.tData(47 downto 32) = x"B712") then v.roce(0) := '1'; v.ipv4Len(0) := r.ipv4Len(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2 + ROCEV2_CRC32_BYTE_WIDTH_C; v.protLen(0) := r.protLen(0) + getTKeep(rxMaster.tKeep, INT_EMAC_AXIS_CONFIG_C) - 2 + ROCEV2_CRC32_BYTE_WIDTH_C; @@ -425,7 +426,7 @@ begin v.mSlave.tReady := '1'; -- Move data v.txMaster := mMaster; - if roce = '1' then + if ROCEV2_EN_G and (roce = '1') then v.txMaster.tDest(0) := '1'; else v.txMaster.tDest(0) := '0'; @@ -468,7 +469,7 @@ begin -- Overwrite the data field v.txMaster.tData(55 downto 48) := protLen(15 downto 8); v.txMaster.tData(63 downto 56) := protLen(7 downto 0); - if roce = '1' then + if ROCEV2_EN_G and (roce = '1') then v.txMaster.tData(71 downto 64) := (others => '0'); v.txMaster.tData(79 downto 72) := (others => '0'); else @@ -514,9 +515,11 @@ begin end if; end if; - -- Combinatorial outputs before the reset - rxSlave <= v.rxSlave; - mSlave <= v.mSlave; + -- Outputs + sMaster <= r.sMaster; + txMaster <= r.txMaster; + rxSlave <= v.rxSlave; + mSlave <= v.mSlave; -- Reset if (ethRst = '1') then @@ -526,10 +529,6 @@ begin -- Register the variable for next clock cycle rin <= v; - -- Registered Outputs - sMaster <= r.sMaster; - txMaster <= r.txMaster; - end process comb; seq : process (ethClk) is diff --git a/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd b/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd index 1236b18b45..db2f416d09 100644 --- a/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd +++ b/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd @@ -28,6 +28,7 @@ entity GigEthGth7 is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -174,6 +175,7 @@ begin JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "GMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd b/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd index b46cb01d4f..49cf3b563d 100644 --- a/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd +++ b/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd @@ -33,6 +33,7 @@ entity GigEthGth7Wrapper is NUM_LANE_G : natural range 1 to 4 := 1; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk CLKIN_PERIOD_G : real := 8.0; @@ -169,6 +170,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd b/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd index cf1e116757..3b24cbfe28 100644 --- a/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd +++ b/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScale.vhd @@ -33,6 +33,7 @@ entity GigEthGthUltraScale is MEMORY_TYPE_G : string := "ultra"; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -188,6 +189,7 @@ begin JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "GMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd b/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd index 9adecff93b..f19eae129f 100644 --- a/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd +++ b/ethernet/GigEthCore/gthUltraScale+/rtl/GigEthGthUltraScaleWrapper.vhd @@ -39,6 +39,7 @@ entity GigEthGthUltraScaleWrapper is MEMORY_TYPE_G : string := "ultra"; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- Clocking Configurations EXT_PLL_G : boolean := false; USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -208,6 +209,7 @@ begin MEMORY_TYPE_G => MEMORY_TYPE_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd index 1d1e2f86cd..7adc39f3a5 100644 --- a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd +++ b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd @@ -28,6 +28,7 @@ entity GigEthGthUltraScale is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -186,6 +187,7 @@ begin JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "GMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd index 9b5b31138c..d0b06fd803 100644 --- a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd +++ b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd @@ -33,6 +33,7 @@ entity GigEthGthUltraScaleWrapper is NUM_LANE_G : natural range 1 to 4 := 1; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- Clocking Configurations EXT_PLL_G : boolean := false; USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -196,6 +197,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd index ad5168567e..e22561884f 100644 --- a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd +++ b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd @@ -28,6 +28,7 @@ entity GigEthGtp7 is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -228,6 +229,7 @@ begin JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "GMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd index bfab8912fd..d0011fd33e 100644 --- a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd +++ b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd @@ -33,6 +33,7 @@ entity GigEthGtp7Wrapper is NUM_LANE_G : natural range 1 to 4 := 1; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -224,6 +225,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd index 59378c1ec8..f0990543b5 100644 --- a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd +++ b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd @@ -29,6 +29,7 @@ entity GigEthGtx7 is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; SYNTH_MODE_G : string := "inferred"; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -239,6 +240,7 @@ begin JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "GMII", SYNTH_MODE_G => SYNTH_MODE_G, PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd index e593e34331..54986a4e3b 100644 --- a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd +++ b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd @@ -33,6 +33,7 @@ entity GigEthGtx7Wrapper is NUM_LANE_G : natural range 1 to 4 := 1; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk CLKIN_PERIOD_G : real := 8.0; @@ -169,6 +170,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd b/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd index d80419a71a..0690f836ca 100644 --- a/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd +++ b/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScale.vhd @@ -33,6 +33,7 @@ entity GigEthGtyUltraScale is MEMORY_TYPE_G : string := "ultra"; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -188,6 +189,7 @@ begin JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "GMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd b/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd index dc9a72da9e..dacd36c573 100644 --- a/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd +++ b/ethernet/GigEthCore/gtyUltraScale+/rtl/GigEthGtyUltraScaleWrapper.vhd @@ -39,6 +39,7 @@ entity GigEthGtyUltraScaleWrapper is MEMORY_TYPE_G : string := "ultra"; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk CLKIN_PERIOD_G : real := 8.0; @@ -189,6 +190,7 @@ begin MEMORY_TYPE_G => MEMORY_TYPE_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd b/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd index b09e32ac1c..4e408a2dab 100644 --- a/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd +++ b/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd @@ -27,6 +27,7 @@ entity GigEthLvdsUltraScale is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXIL_REG_G : boolean := false; -- AXI Streaming Configurations @@ -160,6 +161,7 @@ begin JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "GMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd index 3b3b2ebb1e..6d9a093879 100644 --- a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd +++ b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd @@ -28,6 +28,7 @@ entity TenGigEthGth7 is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -211,6 +212,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd index 6e00f4454d..4b4169d1b9 100644 --- a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd +++ b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd @@ -30,6 +30,7 @@ entity TenGigEthGth7Wrapper is NUM_LANE_G : natural range 1 to 4 := 1; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk REFCLK_DIV2_G : boolean := false; -- FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz @@ -129,6 +130,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd index 4a5e2b891d..36f363973b 100644 --- a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd @@ -27,6 +27,7 @@ entity TenGigEthGthUltraScale is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -237,6 +238,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", MEMORY_TYPE_G => "ultra", diff --git a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd index 33945f6105..935d3e73c1 100644 --- a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd @@ -30,6 +30,7 @@ entity TenGigEthGthUltraScaleWrapper is NUM_LANE_G : natural range 1 to 4 := 1; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- QUAD PLL Configurations EXT_REF_G : boolean := false; QPLL_REFCLK_SEL_G : slv(2 downto 0) := "001"; @@ -146,6 +147,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd index 3eab811909..fc00a440a4 100644 --- a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd @@ -28,6 +28,7 @@ entity TenGigEthGthUltraScale is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -257,6 +258,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd index 3c1f7f72f5..435a58b67d 100644 --- a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd @@ -30,6 +30,7 @@ entity TenGigEthGthUltraScaleWrapper is NUM_LANE_G : natural range 1 to 4 := 1; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- QUAD PLL Configurations EXT_REF_G : boolean := false; QPLL_REFCLK_SEL_G : slv(2 downto 0) := "001"; @@ -149,6 +150,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd index d21ee53c66..16ed640eca 100644 --- a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd +++ b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd @@ -28,6 +28,7 @@ entity TenGigEthGtx7 is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -237,6 +238,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd index afe0f8903b..d3613c332e 100644 --- a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd +++ b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd @@ -30,6 +30,7 @@ entity TenGigEthGtx7Wrapper is NUM_LANE_G : natural range 1 to 4 := 1; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk REFCLK_DIV2_G : boolean := false; -- FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz @@ -137,6 +138,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd index dc8ebe3697..6e21678b2e 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd +++ b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd @@ -27,6 +27,7 @@ entity TenGigEthGtyUltraScale is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -237,6 +238,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", MEMORY_TYPE_G => "ultra", diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd index 948d3e528d..09a3a33468 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd @@ -31,6 +31,7 @@ entity TenGigEthGtyUltraScaleWrapper is NUM_LANE_G : natural range 1 to 4 := 1; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- QUAD PLL Configurations QPLL_REFCLK_SEL_G : slv(2 downto 0) := "001"; -- AXI-Lite Configurations @@ -143,6 +144,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd b/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd index 13e17834c0..6ad3f04689 100644 --- a/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd +++ b/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd @@ -28,6 +28,7 @@ entity XauiGth7 is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -95,6 +96,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd b/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd index 53fd5fc385..f04d64c72a 100644 --- a/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd +++ b/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd @@ -31,6 +31,7 @@ entity XauiGth7Wrapper is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk REFCLK_DIV2_G : boolean := false; -- FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz @@ -98,6 +99,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd index a5ea828b06..93ba5b5386 100644 --- a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd +++ b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd @@ -30,6 +30,7 @@ entity XauiGthUltraScale is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- XAUI Configurations REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz -- AXI-Lite Configurations @@ -205,6 +206,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", MEMORY_TYPE_G => "ultra", diff --git a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd index 8e984b8284..4968a9d014 100644 --- a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd @@ -31,6 +31,7 @@ entity XauiGthUltraScaleWrapper is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; EN_WDT_G : boolean := false; EXT_REF_G : boolean := false; STABLE_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz @@ -142,6 +143,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd index 7e1e90cdec..0492da303f 100644 --- a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd +++ b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd @@ -31,6 +31,7 @@ entity XauiGthUltraScale is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -198,6 +199,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd index a560bdf56c..5d04c70a57 100644 --- a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd @@ -31,6 +31,7 @@ entity XauiGthUltraScaleWrapper is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; EN_WDT_G : boolean := false; EXT_REF_G : boolean := false; STABLE_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz @@ -142,6 +143,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd b/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd index 0ff5e63c0e..405035dd81 100644 --- a/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd +++ b/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd @@ -28,6 +28,7 @@ entity XauiGtx7 is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -95,6 +96,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) port map ( diff --git a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd index f7ffdd41cf..cbca797ad3 100644 --- a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd +++ b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd @@ -31,6 +31,7 @@ entity XauiGtx7Wrapper is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk REFCLK_DIV2_G : boolean := false; -- FALSE: gtClkP/N = 156.25 MHz, TRUE: gtClkP/N = 312.5 MHz @@ -98,6 +99,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations diff --git a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd index aa62e3f26e..80f89319b1 100644 --- a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd +++ b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd @@ -30,6 +30,7 @@ entity XauiGtyUltraScale is TPD_G : time := 1 ns; JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- XAUI Configurations REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz -- AXI-Lite Configurations @@ -205,6 +206,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", MEMORY_TYPE_G => "ultra", diff --git a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd index 4100ce704d..7d46424337 100644 --- a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd @@ -33,6 +33,7 @@ entity XauiGtyUltraScaleWrapper is STABLE_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; + ROCEV2_EN_G : boolean := false; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; -- AXI Streaming Configurations @@ -137,6 +138,7 @@ begin TPD_G => TPD_G, JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, + ROCEV2_EN_G => ROCEV2_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, -- AXI Streaming Configurations