Merge pull request #1129 from slaclab/pre-release

Release Candidate v2.45.4

Makefile

@@ -34,7 +34,7 @@ GHDLFLAGS = --workdir=$(OUT_DIR) --ieee=synopsys -fexplicit -frelaxed-rules  --w
 include $(RUCKUS_DIR)/system_shared.mk
 
 # Override system_shared.mk build string
-export BUILD_SVR_TYPE = $(shell python -m platform)
+export BUILD_SVR_TYPE = $(shell python3 -m platform)
 export GHDL_VERSION   = $(shell ghdl -v 2>&1 | head -n 1)
 export BUILD_STRING   = $(PROJECT): $(GHDL_VERSION), $(BUILD_SYS_NAME) ($(BUILD_SVR_TYPE)), Built $(BUILD_DATE) by $(BUILD_USER)
 

protocols/pgp/pgp2b/core/rtl/Pgp2bAxi.vhd

@@ -55,6 +55,11 @@ entity Pgp2bAxi is
       statusWord : out slv(63 downto 0);
       statusSend : out sl;
 
+      -- Debug Interface (axilClk domain)
+      txDiffCtrl      : out slv(4 downto 0);
+      txPreCursor     : out slv(4 downto 0);
+      txPostCursor    : out slv(4 downto 0);
+
       -- AXI-Lite Register Interface (axilClk domain)
       axilClk         : in  sl;
       axilRst         : in  sl;
@@ -90,6 +95,9 @@ architecture structure of Pgp2bAxi is
    signal syncFlowCntlDis : sl;
 
    type RegType is record
+      txDiffCtrl     : slv(4 downto 0);
+      txPreCursor    : slv(4 downto 0);
+      txPostCursor   : slv(4 downto 0);
       flush          : sl;
       resetTx        : sl;
       resetRx        : sl;
@@ -105,6 +113,9 @@ architecture structure of Pgp2bAxi is
    end record RegType;
 
    constant REG_INIT_C : RegType := (
+      txDiffCtrl     => "11111",
+      txPreCursor    => "00111",
+      txPostCursor   => "01111",
       flush          => '0',
       resetTx        => '0',
       resetRx        => '0',
@@ -566,6 +577,12 @@ begin
                v.autoStatus := axilWriteMaster.wdata(0);
             when X"18" =>
                v.flowCntlDis := ite(WRITE_EN_G, axilWriteMaster.wdata(0), '0');
+            when X"1C" =>
+               if WRITE_EN_G then
+                  v.txDiffCtrl   := axilWriteMaster.wdata(4 downto 0);
+                  v.txPreCursor  := axilWriteMaster.wdata(9 downto 5);
+                  v.txPostCursor := axilWriteMaster.wdata(14 downto 10);
+               end if;
             when others => null;
          end case;
 
@@ -595,6 +612,10 @@ begin
                v.axilReadSlave.rdata(0) := r.autoStatus;
             when X"18" =>
                v.axilReadSlave.rdata(0) := r.flowCntlDis;
+            when X"1C" =>
+               v.axilReadSlave.rdata(4 downto 0)   := r.txDiffCtrl;
+               v.axilReadSlave.rdata(9 downto 5)   := r.txPreCursor;
+               v.axilReadSlave.rdata(14 downto 10) := r.txPostCursor;
             when X"20" =>
                v.axilReadSlave.rdata(0)            := rxStatusSync.phyRxReady;
                v.axilReadSlave.rdata(1)            := txStatusSync.phyTxReady;
@@ -671,6 +692,9 @@ begin
       -- Outputs
       axilReadSlave  <= r.axilReadSlave;
       axilWriteSlave <= r.axilWriteSlave;
+      txDiffCtrl     <= r.txDiffCtrl;
+      txPreCursor    <= r.txPreCursor;
+      txPostCursor   <= r.txPostCursor;
 
    end process;
 

python/surf/protocols/pgp/_Pgp2bAxi.py

@@ -73,6 +73,30 @@ def __init__(self,
                 base        = pr.Bool,
             ))
 
+            self.add(pr.RemoteVariable(
+                name        = "TxDiffCtrl",
+                offset      = 0x1C,
+                bitSize     = 5,
+                bitOffset   = 0,
+                mode        = "RW",
+            ))
+
+            self.add(pr.RemoteVariable(
+                name        = "TxPreCursor",
+                offset      = 0x1C,
+                bitSize     = 5,
+                bitOffset   = 5,
+                mode        = "RW",
+            ))
+
+            self.add(pr.RemoteVariable(
+                name        = "TxPostCursor",
+                offset      = 0x1C,
+                bitSize     = 5,
+                bitOffset   = 10,
+                mode        = "RW",
+            ))
+
         self.add(pr.RemoteVariable(
             name        = "RxPhyReady",
             offset      = 0x20,

python/surf/xilinx/_Xadc.py

@@ -22,12 +22,17 @@ def __init__(self,
                  description = "AXI-Lite XADC for Xilinx 7 Series (Refer to PG091 & PG019)",
                  auxChannels = 0,
                  zynq        = False,
+                 simpleViewList = ["Temperature", "VccInt", "VccAux", "VccBram"],
+                 pollInterval = 5,
                  **kwargs):
         super().__init__(description=description, **kwargs)
 
         if isinstance(auxChannels, int):
             auxChannels = list(range(auxChannels))
 
+        self.simpleViewList = simpleViewList
+        self.simpleViewList.append('enable')
+
         def addPair(name, offset, bitSize, units, bitOffset, description, function, pollInterval=0):
             self.add(pr.RemoteVariable(
                 name         = ("Raw"+name),
@@ -56,7 +61,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll
             bitOffset    = 4,
             units        = "degC",
             function     = self.convTemp,
-            pollInterval = 5,
+            pollInterval = pollInterval,
             description  = """
                 The result of the on-chip temperature sensor measurement is
                 stored in this location. The data is MSB justified in the
@@ -116,7 +121,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll
             bitOffset   = 4,
             units       = "V",
             function    = self.convCoreVoltage,
-            pollInterval = 5,
+            pollInterval = pollInterval,
             description = """
                 The result of the on-chip VccInt supply monitor measurement
                 is stored at this location. The data is MSB justified in the
@@ -164,7 +169,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll
             bitOffset   = 4,
             units       = "V",
             function    = self.convCoreVoltage,
-            pollInterval = 5,
+            pollInterval = pollInterval,
             description = """
                 The result of the on-chip VccAux supply monitor measurement
                 is stored at this location. The data is MSB justified in the
@@ -214,7 +219,7 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll
             bitOffset   = 4,
             units       = "V",
             function    = self.convCoreVoltage,
-            pollInterval = 5,
+            pollInterval = pollInterval,
             description = """
                 The result of the on-chip VccBram supply monitor measurement
                 is stored at this location. The data is MSB justified in the
@@ -331,6 +336,8 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll
                 variable=self.AuxRaw[ch],
                 linkedGet=self.convAuxVoltage))
 
+            self.simpleViewList.append(f'Aux[{ch}]')
+
         if (zynq):
             addPair(
                 name        = 'VccpInt',
@@ -610,5 +617,5 @@ def simpleView(self):
         # Hide all the variable
         self.hideVariables(hidden=True)
         # Then unhide the most interesting ones
-        vars = ["enable", "Temperature", "VccInt", "VccAux", "VccBram"]
+        vars = self.simpleViewList
         self.hideVariables(hidden=False, variables=vars)

ruckus.tcl

@@ -3,7 +3,7 @@ source $::env(RUCKUS_PROC_TCL)
 
 # Check for submodule tagging
 if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } {
-   if { [SubmoduleCheck {ruckus} {4.8.4} ] < 0 } {exit -1}
+   if { [SubmoduleCheck {ruckus} {4.9.0} ] < 0 } {exit -1}
 } else {
    puts "\n\n*********************************************************"
    puts "OVERRIDE_SUBMODULE_LOCKS != 0"

xilinx/general/microblaze/ruckus.tcl

@@ -19,7 +19,8 @@ if { [info exists ::env(VITIS_SRC_PATH)] != 1 }  {
       loadSource -lib surf -path "$::DIR_PATH/generate/MicroblazeBasicCoreWrapper.vhd"
 
       # Load the .bd file
-      if { $::env(VIVADO_VERSION) == 2023.1 ||
+      if { $::env(VIVADO_VERSION) == 2023.2 ||
+           $::env(VIVADO_VERSION) == 2023.1 ||
            $::env(VIVADO_VERSION) == 2022.2 } {
          puts "\nVivado v$::env(VIVADO_VERSION) not supported for general/microblaze\n"
          exit -1