diff --git a/LICENSE.txt b/LICENSE.txt index 44e3f12dca..9aa129c6fb 100644 --- a/LICENSE.txt +++ b/LICENSE.txt @@ -1,5 +1,5 @@ -Copyright (c) 2023, The Board of Trustees of the Leland Stanford Junior +Copyright (c) 2024, The Board of Trustees of the Leland Stanford Junior University, through SLAC National Accelerator Laboratory (subject to receipt of any required approvals from the U.S. Dept. of Energy). All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/axi/simlink/src/RogueSideBand.c b/axi/simlink/src/RogueSideBand.c index 43e6b54e34..319a37be00 100755 --- a/axi/simlink/src/RogueSideBand.c +++ b/axi/simlink/src/RogueSideBand.c @@ -41,13 +41,13 @@ void RogueSideBandRestart(RogueSideBandData *data, portDataT *portData) { vhpi_printf("RogueSideBand: Listening on ports %i & %i\n",data->port, data->port+1); - sprintf(buffer,"tcp://*:%i",data->port+1); + sprintf(buffer,"tcp://127.0.0.1:%i",data->port+1); if ( zmq_bind(data->zmqPull,buffer) ) { vhpi_assert("RogueSideBand: Failed to bind sideband port",vhpiFatal); return; } - sprintf(buffer,"tcp://*:%i",data->port); + sprintf(buffer,"tcp://127.0.0.1:%i",data->port); if ( zmq_bind(data->zmqPush,buffer) ) { vhpi_assert("RogueSideBand: Failed to bind push port",vhpiFatal); return; diff --git a/axi/simlink/src/RogueTcpMemory.c b/axi/simlink/src/RogueTcpMemory.c index a08fc0e3da..a080fdac25 100755 --- a/axi/simlink/src/RogueTcpMemory.c +++ b/axi/simlink/src/RogueTcpMemory.c @@ -41,13 +41,13 @@ void RogueTcpMemoryRestart(RogueTcpMemoryData *data, portDataT *portData) { vhpi_printf("RogueTcpMemory: Listening on ports %i & %i\n",data->port,data->port+1); - sprintf(buffer,"tcp://*:%i",data->port); + sprintf(buffer,"tcp://127.0.0.1:%i",data->port); if ( zmq_bind(data->zmqPull,buffer) ) { vhpi_assert("RogueTcpMemory: Failed to bind pull port",vhpiFatal); return; } - sprintf(buffer,"tcp://*:%i",data->port+1); + sprintf(buffer,"tcp://127.0.0.1:%i",data->port+1); if ( zmq_bind(data->zmqPush,buffer) ) { vhpi_assert("RogueTcpMemory: Failed to bind push port",vhpiFatal); return; diff --git a/axi/simlink/src/RogueTcpStream.c b/axi/simlink/src/RogueTcpStream.c index e7f77a0faf..9bd16f78a5 100755 --- a/axi/simlink/src/RogueTcpStream.c +++ b/axi/simlink/src/RogueTcpStream.c @@ -42,13 +42,13 @@ void RogueTcpStreamRestart(RogueTcpStreamData *data, portDataT *portData) { vhpi_printf("RogueTcpStream: Listening on ports %i & %i\n",data->port,data->port+1); - sprintf(buffer,"tcp://*:%i",data->port); + sprintf(buffer,"tcp://127.0.0.1:%i",data->port); if ( zmq_bind(data->zmqPull,buffer) ) { vhpi_assert("RogueTcpStream: Failed to bind pull port",vhpiFatal); return; } - sprintf(buffer,"tcp://*:%i",data->port+1); + sprintf(buffer,"tcp://127.0.0.1:%i",data->port+1); if ( zmq_bind(data->zmqPush,buffer) ) { vhpi_assert("RogueTcpStream: Failed to bind push port",vhpiFatal); return; diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd index d0d9f3feec..d8b08f5f12 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd @@ -32,30 +32,30 @@ use surf.Ad9249Pkg.all; entity Ad9249Deserializer is generic ( - TPD_G : time := 1 ns; - SIM_DEVICE_G : string := "ULTRASCALE"; - IODELAY_GROUP_G : string := "DEFAULT_GROUP"; - IDELAY_CASCADE_G : boolean := false; - IDELAYCTRL_FREQ_G : real := 300.0; - DEFAULT_DELAY_G : slv(8 downto 0) := (others => '0'); - ADC_INVERT_CH_G : sl := '0'; - BIT_REV_G : sl := '0'); + TPD_G : time := 1 ns; + SIM_DEVICE_G : string := "ULTRASCALE"; + IODELAY_GROUP_G : string := "DEFAULT_GROUP"; + IDELAY_CASCADE_G : boolean := false; + IDELAYCTRL_FREQ_G : real := 300.0; + DEFAULT_DELAY_G : slv(8 downto 0) := (others => '0'); + ADC_INVERT_CH_G : sl := '0'; + BIT_REV_G : sl := '0'); port ( -- Serial Data from ADC - dClk : in sl; -- Data clock - dRst : in sl; -- Data reset + dClk : in sl; -- Data clock + dRst : in sl; -- Data reset dClkDiv4 : in sl; dRstDiv4 : in sl; - sDataP : in sl; -- Frame clock + sDataP : in sl; -- Frame clock sDataN : in sl; -- Signal to control data gearboxes loadDelay : in sl; delay : in slv(8 downto 0) := "000000000"; delayValueOut : out slv(8 downto 0); - bitSlip : in sl; -- dClkDiv4 domain - adcData : out slv(13 downto 0); -- dClkDiv4 domain - adcValid : out sl -- dClkDiv4 domain - ); + bitSlip : in sl; -- dClkDiv4 domain + adcData : out slv(13 downto 0); -- dClkDiv4 domain + adcValid : out sl -- dClkDiv4 domain + ); end Ad9249Deserializer; -- Define architecture @@ -70,21 +70,21 @@ architecture rtl of Ad9249Deserializer is -- Local signals - signal sDataPadP : sl; - signal sDataPadN : sl; - signal sData_i : sl; - signal sData_d : sl; + signal sDataPadP : sl; + signal sDataPadN : sl; + signal sData_i : sl; + signal sData_d : sl; -- idelay signals signal masterCntValue1 : slv(8 downto 0); signal masterCntValue2 : slv(8 downto 0); - signal cascOut : sl; - signal cascRet : sl; + signal cascOut : sl; + signal cascRet : sl; -- iserdes signal - signal masterData : slv(7 downto 0); - signal iAdcData : slv(13 downto 0); + signal masterData : slv(7 downto 0); + signal iAdcData : slv(13 downto 0); - attribute keep of sData_i : signal is "true"; + attribute keep of sData_i : signal is "true"; begin @@ -97,13 +97,13 @@ begin U_IBUFDS_sData : IBUFDS_DIFF_OUT generic map ( DQS_BIAS => "FALSE" -- (FALSE, TRUE) - ) + ) port map ( O => sDataPadP, -- 1-bit output: Buffer output OB => sDataPadN, I => sDataP, -- 1-bit input: Diff_p buffer input (connect directly to top-level port) IB => sDataN -- 1-bit input: Diff_n buffer input (connect directly to top-level port) - ); + ); -- Optionally invert the pad input sData_i <= sDataPadP when ADC_INVERT_CH_G = '0' else sDataPadN; ---------------------------------------------------------------------------- @@ -111,7 +111,7 @@ begin ---------------------------------------------------------------------------- U_IDELAYE3_0 : entity surf.Idelaye3Wrapper generic map ( - CASCADE => CASCADE_C, -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) + CASCADE => CASCADE_C, -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) DELAY_FORMAT => "COUNT", -- Units of the DELAY_VALUE (COUNT, TIME) DELAY_SRC => "IDATAIN", -- Delay input (DATAIN, IDATAIN) DELAY_TYPE => "VAR_LOAD", -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD) @@ -125,59 +125,60 @@ begin -- SYNC) ) port map ( - CASC_IN => '0', -- 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT - CASC_OUT => cascOut, -- 1-bit output: Cascade delay output to ODELAY input cascade + CASC_IN => '0', -- 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT + CASC_OUT => cascOut, -- 1-bit output: Cascade delay output to ODELAY input cascade CASC_RETURN => cascRet, -- 1-bit input: Cascade delay returning from slave ODELAY DATAOUT - CNTVALUEOUT => masterCntValue1, -- 9-bit output: Counter value output + CNTVALUEOUT => masterCntValue1, -- 9-bit output: Counter value output DATAOUT => sData_d, -- 1-bit output: Delayed data output - CE => '0', -- 1-bit input: Active high enable increment/decrement input + CE => '0', -- 1-bit input: Active high enable increment/decrement input CLK => dClkDiv4, -- 1-bit input: Clock input - CNTVALUEIN => delay, -- 9-bit input: Counter value input + CNTVALUEIN => delay, -- 9-bit input: Counter value input DATAIN => '1', -- 1-bit input: Data input from the logic - EN_VTC => '0', -- 1-bit input: Keep delay constant over VT + EN_VTC => '0', -- 1-bit input: Keep delay constant over VT IDATAIN => sData_i, -- 1-bit input: Data input from the IOBUF INC => '0', -- 1-bit input: Increment / Decrement tap delay input - LOAD => loadDelay, -- 1-bit input: Load DELAY_VALUE input - RST => dRstDiv4 -- 1-bit input: Asynchronous Reset to the DELAY_VALUE + LOAD => loadDelay, -- 1-bit input: Load DELAY_VALUE input + RST => dRstDiv4 -- 1-bit input: Asynchronous Reset to the DELAY_VALUE ); - G_IdelayCascade: if IDELAY_CASCADE_G = true generate - signal masterCntValue : slv(9 downto 0); + G_IdelayCascade : if IDELAY_CASCADE_G = true generate + signal masterCntValue : slv(9 downto 0); begin U_ODELAYE3_0 : entity surf.Odelaye3Wrapper generic map ( - CASCADE => "SLAVE_END", -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) - DELAY_FORMAT => "COUNT", -- Units of the DELAY_VALUE (COUNT, TIME) - DELAY_TYPE => "VAR_LOAD", -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD) - DELAY_VALUE => conv_integer(DEFAULT_DELAY_G), -- Input delay value setting - IS_CLK_INVERTED => '0', -- Optional inversion for CLK - IS_RST_INVERTED => '0', -- Optional inversion for RST - REFCLK_FREQUENCY => IDELAYCTRL_FREQ_G, -- IDELAYCTRL clock input frequency in MHz (200.0-2400.0) - UPDATE_MODE => "ASYNC") -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) + CASCADE => "SLAVE_END", -- Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) + DELAY_FORMAT => "COUNT", -- Units of the DELAY_VALUE (COUNT, TIME) + DELAY_TYPE => "VAR_LOAD", -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD) + DELAY_VALUE => conv_integer(DEFAULT_DELAY_G), -- Input delay value setting + IS_CLK_INVERTED => '0', -- Optional inversion for CLK + IS_RST_INVERTED => '0', -- Optional inversion for RST + REFCLK_FREQUENCY => IDELAYCTRL_FREQ_G, -- IDELAYCTRL clock input frequency in MHz (200.0-2400.0) + SIM_DEVICE => SIM_DEVICE_G, + UPDATE_MODE => "ASYNC") -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) port map ( - CASC_IN => cascOut, -- 1-bit input: Cascade delay input from slave IDELAY CASCADE_OUT - CASC_OUT => open, -- 1-bit output: Cascade delay output to IDELAY input cascade - CASC_RETURN => '0', -- 1-bit input: Cascade delay returning from slave IDELAY DATAOUT - ODATAIN => '0', -- 1-bit input: Data input - DATAOUT => cascRet, -- 1-bit output: Delayed data from ODATAIN input port - CLK => dClkDiv4, -- 1-bit input: Clock input - EN_VTC => '0', -- 1-bit input: Keep delay constant over VT - INC => '0', -- 1-bit input: Increment / Decrement tap delay input - CE => '0', -- 1-bit input: Active high enable increment/decrement input + CASC_IN => cascOut, -- 1-bit input: Cascade delay input from slave IDELAY CASCADE_OUT + CASC_OUT => open, -- 1-bit output: Cascade delay output to IDELAY input cascade + CASC_RETURN => '0', -- 1-bit input: Cascade delay returning from slave IDELAY DATAOUT + ODATAIN => '0', -- 1-bit input: Data input + DATAOUT => cascRet, -- 1-bit output: Delayed data from ODATAIN input port + CLK => dClkDiv4, -- 1-bit input: Clock input + EN_VTC => '0', -- 1-bit input: Keep delay constant over VT + INC => '0', -- 1-bit input: Increment / Decrement tap delay input + CE => '0', -- 1-bit input: Active high enable increment/decrement input LOAD => loadDelay, -- 1-bit input: Load DELAY_VALUE input - RST => dRstDiv4, -- 1-bit input: Asynchronous Reset to the DELAY_VALUE - CNTVALUEIN => delay, -- 9-bit input: Counter value input - CNTVALUEOUT => masterCntValue2); -- 9-bit output: Counter value output + RST => dRstDiv4, -- 1-bit input: Asynchronous Reset to the DELAY_VALUE + CNTVALUEIN => delay, -- 9-bit input: Counter value input + CNTVALUEOUT => masterCntValue2); -- 9-bit output: Counter value output masterCntValue <= resize(masterCntValue1, 10, '0') + masterCntValue2; - delayValueOut <= masterCntValue(9 downto 1); + delayValueOut <= masterCntValue(9 downto 1); end generate; - G_IdelayNoCascade: if IDELAY_CASCADE_G = false generate - delayValueOut <= masterCntValue1; - masterCntValue2 <= (others=>'0'); - cascRet <= '0'; + G_IdelayNoCascade : if IDELAY_CASCADE_G = false generate + delayValueOut <= masterCntValue1; + masterCntValue2 <= (others => '0'); + cascRet <= '0'; end generate; ---------------------------------------------------------------------------- @@ -192,42 +193,38 @@ begin IS_CLK_INVERTED => '0', -- Optional inversion for CLK IS_RST_INVERTED => '0', -- Optional inversion for RST SIM_DEVICE => SIM_DEVICE_G -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, - ) + ) port map ( FIFO_EMPTY => open, -- 1-bit output: FIFO empty flag INTERNAL_DIVCLK => open, -- 1-bit output: Internally divided down clock used when FIFO is - Q => masterData, -- bit registered output - CLK => dClk, -- 1-bit input: High-speed clock - CLKDIV => dClkDiv4, -- 1-bit input: Divided Clock - CLK_B => dClk, -- 1-bit input: Inversion of High-speed clock CLK - D => sData_d, -- 1-bit input: Serial Data Input - FIFO_RD_CLK => '1', -- 1-bit input: FIFO read clock - FIFO_RD_EN => '1', -- 1-bit input: Enables reading the FIFO when asserted - RST => dRstDiv4 -- 1-bit input: Asynchronous Reset - ); - - + Q => masterData, -- bit registered output + CLK => dClk, -- 1-bit input: High-speed clock + CLKDIV => dClkDiv4, -- 1-bit input: Divided Clock + CLK_B => dClk, -- 1-bit input: Inversion of High-speed clock CLK + D => sData_d, -- 1-bit input: Serial Data Input + FIFO_RD_CLK => '1', -- 1-bit input: FIFO read clock + FIFO_RD_EN => '1', -- 1-bit input: Enables reading the FIFO when asserted + RST => dRstDiv4 -- 1-bit input: Asynchronous Reset + ); U_Gearbox : entity surf.Gearbox generic map ( - TPD_G => TPD_G, - SLAVE_WIDTH_G => 8, - MASTER_WIDTH_G => 14 - ) + TPD_G => TPD_G, + SLAVE_WIDTH_G => 8, + MASTER_WIDTH_G => 14, + MASTER_BIT_REVERSE_G => toBoolean(BIT_REV_G) + ) port map ( clk => dClkDiv4, rst => dRstDiv4, - slip => bitSlip, -- bitslip by the Microblaze alignment code + slip => bitSlip, -- bitslip by the Microblaze alignment code -- Slave Interface slaveValid => '1', slaveData => masterData, -- Master Interface masterValid => adcValid, - masterData => iAdcData, - masterReady => '1' - ); - - adcData <= iAdcData when BIT_REV_G = '0' else bitReverse(iAdcData(6 downto 0)) & bitReverse(iAdcData(13 downto 7)); + masterData => adcData, + masterReady => '1'); end rtl; diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd index 0b4c58c91c..e610af0cab 100644 --- a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd @@ -45,36 +45,36 @@ entity Ad9249ReadoutGroup is SIM_SPEEDUP_G : boolean := false); port ( -- Master system clock, 125Mhz - axilClk : in sl; - axilRst : in sl; + axilClk : in sl; + axilRst : in sl; -- Axi Interface - axilWriteMaster : in AxiLiteWriteMasterType; - axilWriteSlave : out AxiLiteWriteSlaveType; - axilReadMaster : in AxiLiteReadMasterType; - axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType; -- Reset for adc deserializer (axilClk domain) - adcClkRst : in sl; + adcClkRst : in sl; -- clocks must be provided with USE_MMCME_G = false -- this option is necessary if there is many ADCs -- one external MMCM should be instantiated to be used with all Ad9249ReadoutGroups - adcBitClkIn : in sl; -- 350.0 MHz - adcBitClkDiv4In : in sl; -- 87.5 MHz - adcBitRstIn : in sl; - adcBitRstDiv4In : in sl; + adcBitClkIn : in sl; -- 350.0 MHz + adcBitClkDiv4In : in sl; -- 87.5 MHz + adcBitRstIn : in sl; + adcBitRstDiv4In : in sl; -- Serial Data from ADC - adcSerial : in Ad9249SerialGroupType; + adcSerial : in Ad9249SerialGroupType; -- Deserialized ADC Data - adcStreamClk : in sl; - adcStreams : out AxiStreamMasterArray(NUM_CHANNELS_G-1 downto 0) := - (others => axiStreamMasterInit((false, 2, 8, 0, TKEEP_NORMAL_C, 0, TUSER_NORMAL_C))); + adcStreamClk : in sl; + adcStreams : out AxiStreamMasterArray(NUM_CHANNELS_G-1 downto 0) := + (others => axiStreamMasterInit((false, 2, 8, 0, TKEEP_NORMAL_C, 0, TUSER_NORMAL_C))); -- optional ready to allow evenout samples readout in adcStreamClk - adcReady : in slv(NUM_CHANNELS_G-1 downto 0) := (others => '1') - ); + adcReady : in slv(NUM_CHANNELS_G-1 downto 0) := (others => '1') + ); end Ad9249ReadoutGroup; -- Define architecture @@ -111,7 +111,7 @@ architecture rtl of Ad9249ReadoutGroup is readoutDebug1 => (others => (others => '0')), lockedCountRst => '0', invert => '0' - ); + ); signal lockedSync : sl; signal lockedFallCount : slv(15 downto 0); @@ -123,24 +123,24 @@ architecture rtl of Ad9249ReadoutGroup is -- ADC Readout Clocked Registers ------------------------------------------------------------------------------------------------- type AdcRegType is record - slip : sl; - count : slv(5 downto 0); + slip : sl; + count : slv(5 downto 0); --loadDelay : sl; --delayValue : slv(8 downto 0); - locked : sl; - fifoWrData : Slv16Array(NUM_CHANNELS_G-1 downto 0); - fifoWrDataEn : slv(NUM_CHANNELS_G-1 downto 0); + locked : sl; + fifoWrData : Slv16Array(NUM_CHANNELS_G-1 downto 0); + fifoWrDataEn : slv(NUM_CHANNELS_G-1 downto 0); end record; constant ADC_REG_INIT_C : AdcRegType := ( - slip => '0', - count => (others => '0'), + slip => '0', + count => (others => '0'), --loadDelay => '0', --delayValue => (others => '0'), - locked => '0', - fifoWrData => (others => (others => '0')), - fifoWrDataEn => (others => '0') - ); + locked => '0', + fifoWrData => (others => (others => '0')), + fifoWrDataEn => (others => '0') + ); signal adcR : AdcRegType := ADC_REG_INIT_C; signal adcRin : AdcRegType; @@ -157,9 +157,9 @@ architecture rtl of Ad9249ReadoutGroup is signal adcBitRst : sl; signal adcClkRstSync : sl; - signal adcFrame : slv(13 downto 0); - signal adcFrameSync : slv(13 downto 0); - signal adcData : Slv14Array(NUM_CHANNELS_G-1 downto 0); + signal adcFrame : slv(13 downto 0); + signal adcFrameSync : slv(13 downto 0); + signal adcData : Slv14Array(NUM_CHANNELS_G-1 downto 0); signal curDelayFrame : slv(8 downto 0); signal curDelayData : slv9Array(NUM_CHANNELS_G-1 downto 0); @@ -173,7 +173,7 @@ architecture rtl of Ad9249ReadoutGroup is signal frameDelay : slv(8 downto 0); signal frameDelaySet : sl; - signal invertSync : sl; + signal invertSync : sl; begin ------------------------------------------------------------------------------------------------- @@ -198,7 +198,7 @@ begin rdClk => axilClk, rdRst => axilRst, cntRst => axilR.lockedCountRst - ); + ); Synchronizer_1 : entity surf.Synchronizer generic map ( @@ -240,9 +240,9 @@ begin begin v := axilR; - v.dataDelaySet := (others => '0'); - v.frameDelaySet := '0'; - v.lockedCountRst := '0'; + v.dataDelaySet := (others => '0'); + v.frameDelaySet := '0'; + v.lockedCountRst := '0'; -- Store last two samples read from ADC for i in 0 to NUM_CHANNELS_G-1 loop @@ -318,14 +318,14 @@ begin G_MMCM : if USE_MMCME_G = true generate AdcClk_I_Ibufds : IBUFDS - generic map ( - DQS_BIAS => "FALSE" - ) - port map ( - I => adcSerial.dClkP, - IB => adcSerial.dClkN, - O => adcDclk - ); + generic map ( + DQS_BIAS => "FALSE" + ) + port map ( + I => adcSerial.dClkP, + IB => adcSerial.dClkN, + O => adcDclk + ); ------------------------------------------ -- Generate clocks from ADC incoming clock @@ -335,22 +335,22 @@ begin -- clkOut(1) : 87.50 MHz adcBitClkDiv4 clock U_iserdesClockGen : entity surf.ClockManagerUltraScale generic map( - TPD_G => 1 ns, - TYPE_G => "MMCM", -- or "PLL" - INPUT_BUFG_G => true, - FB_BUFG_G => true, - RST_IN_POLARITY_G => '1', -- '0' for active low - NUM_CLOCKS_G => 2, + TPD_G => 1 ns, + TYPE_G => "MMCM", -- or "PLL" + INPUT_BUFG_G => true, + FB_BUFG_G => true, + RST_IN_POLARITY_G => '1', -- '0' for active low + NUM_CLOCKS_G => 2, -- MMCM attributes - BANDWIDTH_G => "OPTIMIZED", - CLKIN_PERIOD_G => 2.85, -- Input period in ns ); - DIVCLK_DIVIDE_G => 10, - CLKFBOUT_MULT_F_G => 20.0, - CLKFBOUT_MULT_G => 5, - CLKOUT0_DIVIDE_F_G => 1.0, - CLKOUT0_DIVIDE_G => 2, - CLKOUT1_DIVIDE_G => 8 - ) + BANDWIDTH_G => "OPTIMIZED", + CLKIN_PERIOD_G => 2.85, -- Input period in ns ); + DIVCLK_DIVIDE_G => 10, + CLKFBOUT_MULT_F_G => 20.0, + CLKFBOUT_MULT_G => 5, + CLKOUT0_DIVIDE_F_G => 1.0, + CLKOUT0_DIVIDE_G => 2, + CLKOUT1_DIVIDE_G => 8 + ) port map( clkIn => adcDclk, rstIn => '0', @@ -359,16 +359,16 @@ begin rstOut(0) => adcBitRst, rstOut(1) => adcBitRstDiv4, locked => open - ); + ); end generate G_MMCM; G_NO_MMCM : if USE_MMCME_G = false generate - adcBitClk <= adcBitClkIn; - adcBitClkDiv4 <= adcBitClkDiv4In; - adcBitRst <= adcBitRstIn; - adcBitRstDiv4 <= adcBitRstDiv4In; + adcBitClk <= adcBitClkIn; + adcBitClkDiv4 <= adcBitClkDiv4In; + adcBitRst <= adcBitRstIn; + adcBitRstDiv4 <= adcBitRstDiv4In; end generate G_NO_MMCM; @@ -386,7 +386,7 @@ begin ADC_INVERT_CH_G => '1', BIT_REV_G => '0') port map ( - dClk => adcBitClk, -- Data clock + dClk => adcBitClk, -- Data clock dRst => adcBitRst, dClkDiv4 => adcBitClkDiv4, dRstDiv4 => adcBitRstDiv4, @@ -398,7 +398,7 @@ begin bitSlip => adcR.slip, adcData => adcFrame, adcValid => adcFrameValid - ); + ); U_FrmDlyFifo : entity surf.SynchronizerFifo generic map ( @@ -436,7 +436,7 @@ begin ADC_INVERT_CH_G => ADC_INVERT_CH_G(i), BIT_REV_G => '1') port map ( - dClk => adcBitClk, -- Data clock + dClk => adcBitClk, -- Data clock dRst => adcBitRst, dClkDiv4 => adcBitClkDiv4, dRstDiv4 => adcBitRstDiv4, @@ -481,7 +481,7 @@ begin ---------------------------------------------------------------------------------------------- -- Slip bits until correct alignment seen ---------------------------------------------------------------------------------------------- - v.slip := '0'; + v.slip := '0'; if (adcR.count = 0) then if adcFrameValid = '1' then if (adcFrame = FRAME_PATTERN_C) then @@ -537,14 +537,14 @@ begin end process adcSeq; RstSync_1 : entity surf.RstSync - generic map ( - TPD_G => TPD_G - ) - port map ( - clk => adcBitClkDiv4, - asyncRst => adcClkRst, - syncRst => adcClkRstSync - ); + generic map ( + TPD_G => TPD_G + ) + port map ( + clk => adcBitClkDiv4, + asyncRst => adcClkRst, + syncRst => adcClkRstSync + ); -- synchronize data cross-clocks G_FIFO_SYNC : for i in NUM_CHANNELS_G-1 downto 0 generate @@ -552,9 +552,9 @@ begin U_DataFifo : entity surf.SynchronizerFifo generic map ( - TPD_G => TPD_G, - DATA_WIDTH_G => 16, - ADDR_WIDTH_G => 4) + TPD_G => TPD_G, + DATA_WIDTH_G => 16, + ADDR_WIDTH_G => 4) port map ( rst => adcBitRstDiv4, wr_clk => adcBitClkDiv4, @@ -564,7 +564,7 @@ begin rd_en => fifoDataRdEn(i), valid => fifoDataValid(i), dout => adcStreams(i).tdata(15 downto 0) - ); + ); fifoDataRdEn(i) <= adcReady(i) and fifoDataValid(i); adcStreams(i).tDest <= toSlv(i, 8); @@ -572,9 +572,9 @@ begin U_DataFifoDebug : entity surf.SynchronizerFifo generic map ( - TPD_G => TPD_G, - DATA_WIDTH_G => 16, - ADDR_WIDTH_G => 4) + TPD_G => TPD_G, + DATA_WIDTH_G => 16, + ADDR_WIDTH_G => 4) port map ( rst => adcBitRstDiv4, wr_clk => adcBitClkDiv4, @@ -584,7 +584,7 @@ begin rd_en => debugDataValid(i), valid => debugDataValid(i), dout => debugData(i) - ); + ); end generate; diff --git a/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd new file mode 100644 index 0000000000..4a86948b48 --- /dev/null +++ b/devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd @@ -0,0 +1,582 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: +-- ADC Readout Controller +-- Receives ADC Data from an AD9592 chip. +-- Designed specifically for Xilinx 7 series FPGAs +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library UNISIM; +use UNISIM.vcomponents.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.Ad9249Pkg.all; + +entity Ad9249ReadoutGroup2 is + generic ( + TPD_G : time := 1 ns; + SIM_DEVICE_G : string := "ULTRASCALE"; + NUM_CHANNELS_G : natural := 8; + SIMULATION_G : boolean := false; + DEFAULT_DELAY_G : slv(8 downto 0) := "000000000"; + ADC_INVERT_CH_G : slv(7 downto 0) := "00000000"); + port ( + -- AXI-Lite clock + axilClk : in sl; + axilRst : in sl; + + -- Axi Interface + axilWriteMaster : in AxiLiteWriteMasterType; + axilWriteSlave : out AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C; + axilReadMaster : in AxiLiteReadMasterType; + axilReadSlave : out AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C; + + -- Asynchronous reset for adc deserializer + adcClkRst : in sl; + + -- DDR Serial Data from ADC + adcSerial : in Ad9249SerialGroupType; + + -- Deserialized ADC Data + adcStreamClk : in sl; + adcStreams : out AxiStreamMasterArray(NUM_CHANNELS_G-1 downto 0) := (others => axiStreamMasterInit(AD9249_AXIS_CFG_G))); + +end Ad9249ReadoutGroup2; + +-- Define architecture +architecture rtl of Ad9249ReadoutGroup2 is + + + ------------------------------------------------------------------------------------------------- + -- AXIL Registers + ------------------------------------------------------------------------------------------------- + type AxilRegType is record + axilWriteSlave : AxiLiteWriteSlaveType; + axilReadSlave : AxiLiteReadSlaveType; + delay : slv(8 downto 0); + delaySet : sl; + freezeDebug : sl; + readoutDebug0 : slv16Array(7 downto 0); + readoutDebug1 : slv16Array(7 downto 0); + lockedCountRst : sl; + invert : sl; + realign : sl; + minEyeWidth : slv(7 downto 0); + end record; + + constant AXIL_REG_INIT_C : AxilRegType := ( + axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, + axilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, + delay => DEFAULT_DELAY_G, + delaySet => '0', + freezeDebug => '0', + readoutDebug0 => (others => (others => '0')), + readoutDebug1 => (others => (others => '0')), + lockedCountRst => '0', + invert => '0', + realign => '1', + minEyeWidth => X"50"); + + signal lockedSync : sl; + signal lockedFallCount : slv(15 downto 0); + + signal axilR : AxilRegType := AXIL_REG_INIT_C; + signal axilRin : AxilRegType; + + ------------------------------------------------------------------------------------------------- + -- ADC Readout Clocked Registers + ------------------------------------------------------------------------------------------------- + type AdcRegType is record + errorDet : sl; + end record; + + constant ADC_REG_INIT_C : AdcRegType := ( + errorDet => '1'); + + + signal adcR : AdcRegType := ADC_REG_INIT_C; + signal adcRin : AdcRegType; + + + -- Local Signals + signal adcBitClk : sl; + signal adcBitRst : sl; + signal adcBitClkDiv4 : sl; + signal adcBitRstDiv4 : sl; + + signal adcFrame : slv(13 downto 0); + signal adcFrameValid : sl; + signal adcFrameSync : slv(13 downto 0); + signal adcFrameSyncValid : sl; + signal adcData : slv14Array(NUM_CHANNELS_G-1 downto 0); + signal adcDataValid : slv(NUM_CHANNELS_G-1 downto 0); + + signal fifoWrData : slv16Array(NUM_CHANNELS_G-1 downto 0); + signal fifoDataValid : sl; + signal fifoDataOut : slv(NUM_CHANNELS_G*16-1 downto 0); + signal fifoDataIn : slv(NUM_CHANNELS_G*16-1 downto 0); + signal fifoDataTmp : slv16Array(NUM_CHANNELS_G-1 downto 0); + + signal debugDataValid : sl; + signal debugDataOut : slv(NUM_CHANNELS_G*16-1 downto 0); + signal debugDataTmp : slv16Array(7 downto 0); + + signal invertSync : sl; + signal bitSlip : sl; + signal dlyLoad : sl; + signal dlyCfg : slv(8 downto 0); + signal enUsrDlyCfg : sl; + signal usrDlyCfg : slv(8 downto 0) := (others => '0'); + signal minEyeWidthSync : slv(7 downto 0); + signal lockingCntCfg : slv(23 downto 0) := ite(SIMULATION_G, X"000008", X"00FFFF"); + signal locked : sl; + signal realignSync : sl; + signal curDelay : slv(8 downto 0); + signal errorDetCount : slv(15 downto 0); + signal errorDet : sl; + + +begin + ------------------------------------------------------------------------------------------------- + -- Synchronize adcR.locked across to axil clock domain and count falling edges on it + ------------------------------------------------------------------------------------------------- + Synchronizer_locked : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G, + STAGES_G => 2) + port map ( + clk => axilClk, + rst => axilRst, + dataIn => locked, + dataOut => lockedSync); + + SynchronizerOneShotCnt_locked_fall : entity surf.SynchronizerOneShotCnt + generic map ( + TPD_G => TPD_G, + IN_POLARITY_G => '0', + OUT_POLARITY_G => '0', + CNT_RST_EDGE_G => true, + CNT_WIDTH_G => 16) + port map ( + dataIn => locked, + rollOverEn => '0', + cntRst => axilR.lockedCountRst, + dataOut => open, + cntOut => lockedFallCount, + wrClk => adcBitClkDiv4, + wrRst => '0', + rdClk => axilClk, + rdRst => axilRst); + + SynchronizerOneShotCnt_2 : entity surf.SynchronizerOneShotCnt + generic map ( + TPD_G => TPD_G, + IN_POLARITY_G => '1', + OUT_POLARITY_G => '1', + CNT_RST_EDGE_G => false, + CNT_WIDTH_G => 16) + port map ( + dataIn => errorDet, + rollOverEn => '0', + cntRst => axilR.lockedCountRst, + dataOut => open, + cntOut => errorDetCount, + wrClk => adcBitClkDiv4, + wrRst => '0', + rdClk => axilClk, + rdRst => axilRst); + + + SynchronizerVector_FRAME : entity surf.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => 14, + ADDR_WIDTH_G => 4) + port map ( + rst => axilRst, + wr_clk => adcBitClkDiv4, + wr_en => adcFrameValid, + din => adcFrame, + rd_clk => axilClk, + rd_en => adcFrameSyncValid, + valid => adcFrameSyncValid, + dout => adcFrameSync); + + U_SynchronizerVector_CUR_DELAY : entity surf.SynchronizerVector + generic map ( + TPD_G => TPD_G, + STAGES_G => 2, + WIDTH_G => 9) + port map ( + clk => axilClk, -- [in] + rst => axilRst, -- [in] + dataIn => dlyCfg, -- [in] + dataOut => curDelay); -- [out] + + + -- AXIL to ADC clock + Synchronizer_INVERT : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G, + STAGES_G => 2) + port map ( + clk => adcBitClkDiv4, + dataIn => axilR.invert, + dataOut => invertSync); + + Synchronizer_REALIGN : entity surf.RstSync + generic map ( + TPD_G => TPD_G, + RELEASE_DELAY_G => 3) + port map ( + clk => adcBitClkDiv4, + asyncRst => axilR.realign, + syncRst => realignSync); + + Synchronizer_USR_DELAY_SET : entity surf.Synchronizer + generic map ( + TPD_G => TPD_G, + STAGES_G => 3) + port map ( + clk => adcBitClkDiv4, + rst => adcBitRstDiv4, + dataIn => axilR.delaySet, + dataOut => enUsrDlyCfg); + + U_SynchronizerVector_USR_DELAY : entity surf.SynchronizerVector + generic map ( + TPD_G => TPD_G, + STAGES_G => 2, + WIDTH_G => 9) + port map ( + clk => adcBitClkDiv4, -- [in] + rst => adcBitRstDiv4, -- [in] + dataIn => axilR.delay, -- [in] + dataOut => usrDlyCfg); -- [out] + + U_SynchronizerVector_EYE_WIDTH : entity surf.SynchronizerVector + generic map ( + TPD_G => TPD_G, + STAGES_G => 2, + WIDTH_G => 8) + port map ( + clk => adcBitClkDiv4, -- [in] + rst => adcBitRstDiv4, -- [in] + dataIn => axilR.minEyeWidth, -- [in] + dataOut => minEyeWidthSync); -- [out] + + + +------------------------------------------------------------------------------------------------- +-- AXIL Interface +------------------------------------------------------------------------------------------------- + axilComb : process (adcFrameSync, axilR, axilReadMaster, axilRst, axilWriteMaster, curDelay, + debugDataTmp, debugDataValid, errorDetCount, lockedFallCount, lockedSync) is + variable v : AxilRegType; + variable axilEp : AxiLiteEndpointType; + begin + v := axilR; + + v.delaySet := '0'; + + -- Store last two samples read from ADC + if (debugDataValid = '1' and axilR.freezeDebug = '0') then + v.readoutDebug0 := debugDataTmp; + v.readoutDebug1 := axilR.readoutDebug0; + end if; + + axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); + + -- Write delay values to IDELAY primatives + -- Overriding gearbox aligner + -- All writes go to same r.delay register, + axiSlaveRegister(axilEp, X"00", 0, v.delay); + axiWrDetect(axilEp, X"00", v.delaySet); + axiSlaveRegisterR(axilEp, X"00", 0, curDelay); + + v.realign := '0'; + axiSlaveRegister(axilEp, X"20", 0, v.realign); + axiSlaveRegisterR(axilEp, X"30", 0, errorDetCount); + + -- Debug output to see how many times the shift has needed a relock + axiSlaveRegisterR(axilEp, X"50", 0, lockedFallCount); + axiSlaveRegisterR(axilEp, X"50", 16, lockedSync); + + axiSlaveRegisterR(axilEp, X"58", 0, adcFrameSync); + + axiSlaveRegister(axilEp, X"5C", 0, v.lockedCountRst); + + axiSlaveRegister(axilEp, X"60", 0, v.invert); + + -- Debug registers. Output the last 2 words received + for ch in 0 to 7 loop + axiSlaveRegisterR(axilEp, X"80"+toSlv((ch*4), 8), 0, axilR.readoutDebug0(ch)); + axiSlaveRegisterR(axilEp, X"80"+toSlv((ch*4), 8), 16, axilR.readoutDebug1(ch)); + end loop; + + axiSlaveRegister(axilEp, X"A0", 0, v.freezeDebug); + + axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); + + if (axilRst = '1') then + v := AXIL_REG_INIT_C; + end if; + + axilRin <= v; + axilWriteSlave <= axilR.axilWriteSlave; + axilReadSlave <= axilR.axilReadSlave; + + end process; + + axilSeq : process (axilClk) is + begin + if (rising_edge(axilClk)) then + axilR <= axilRin after TPD_G; + end if; + end process axilSeq; + + +------------------------------------------------------------------------------------------------- +-- Create Clocks +------------------------------------------------------------------------------------------------- + + AdcClk_I_Ibufds : IBUFGDS + port map ( + I => adcSerial.dClkP, + IB => adcSerial.dClkN, + O => adcBitClk); + + + ADC_BITCLK_RST_SYNC : entity surf.RstSync + generic map ( + TPD_G => TPD_G, + RELEASE_DELAY_G => 5) + port map ( + clk => adcBitClk, + asyncRst => adcClkRst, + syncRst => adcBitRst); + + + U_AdcBitClkRD4 : BUFGCE_DIV + generic map ( + BUFGCE_DIVIDE => 4, -- 1-8 + -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins + IS_CE_INVERTED => '0', -- Optional inversion for CE + IS_CLR_INVERTED => '0', -- Optional inversion for CLR + IS_I_INVERTED => '0') -- Optional inversion for I + port map ( + I => adcBitClk, + O => adcBitClkDiv4, + CE => '1', + CLR => '0'); + + + ADC_BITCLK_DIV4_RST_SYNC : entity surf.RstSync + generic map ( + TPD_G => TPD_G, + RELEASE_DELAY_G => 5) + port map ( + clk => adcBitClkDiv4, + asyncRst => adcClkRst, + syncRst => adcBitRstDiv4); + + +------------------------------------------------------------------------------------------------- +-- Deserializers +------------------------------------------------------------------------------------------------- + + U_FRAME_DESERIALIZER : entity surf.Ad9249Deserializer + generic map ( + TPD_G => TPD_G, + SIM_DEVICE_G => SIM_DEVICE_G, + DEFAULT_DELAY_G => DEFAULT_DELAY_G, + IDELAYCTRL_FREQ_G => 350.0, -- Check this + ADC_INVERT_CH_G => '0', + BIT_REV_G => '1') + port map ( + dClk => adcBitClk, + dRst => adcBitRst, + dClkDiv4 => adcBitClkDiv4, + dRstDiv4 => realignSync, + sDataP => adcSerial.fClkP, + sDataN => adcSerial.fClkN, + loadDelay => dlyLoad, + delay => dlyCfg, + bitSlip => bitSlip, + delayValueOut => open, + adcData => adcFrame, + adcValid => adcFrameValid); + + +-------------------------------- +-- Data Input, 8 channels +-------------------------------- + GenData : for ch in NUM_CHANNELS_G-1 downto 0 generate + U_DATA_DESERIALIZER : entity surf.Ad9249Deserializer + generic map ( + TPD_G => TPD_G, + SIM_DEVICE_G => SIM_DEVICE_G, + DEFAULT_DELAY_G => DEFAULT_DELAY_G, + IDELAYCTRL_FREQ_G => 350.0, -- Check this + ADC_INVERT_CH_G => ADC_INVERT_CH_G(ch), + BIT_REV_G => '1') -- Should maybe be '1' + port map ( + dClk => adcBitClk, + dRst => adcBitRst, + dClkDiv4 => adcBitClkDiv4, + dRstDiv4 => realignSync, + sDataP => adcSerial.chP(ch), + sDataN => adcSerial.chN(ch), + loadDelay => dlyLoad, + delay => dlyCfg, + bitSlip => bitSlip, + delayValueOut => open, + adcData => adcData(ch), + adcValid => adcDataValid(ch)); + end generate; + + + ---------------------------------------------------------------------------------------------- + -- Aligner + ---------------------------------------------------------------------------------------------- + U_SelectIoRxGearboxAligner_1 : entity surf.SelectIoRxGearboxAligner + generic map ( + TPD_G => TPD_G, + SIMULATION_G => SIMULATION_G, + CODE_TYPE_G => "LINE_CODE", + DLY_STEP_SIZE_G => ite(SIMULATION_G, 16, 1)) + port map ( + clk => adcBitClkDiv4, -- [in] + rst => adcBitRstDiv4, -- [in] + lineCodeValid => '1', -- [in] + lineCodeErr => adcR.errorDet, -- [in] + lineCodeDispErr => realignSync, -- [in] + linkOutOfSync => '0', -- [in] + rxHeaderValid => '0', -- [in] + rxHeader => (others => '0'), -- [in] + bitSlip => bitSlip, -- [out] + dlyLoad => dlyLoad, -- [out] + dlyCfg => dlyCfg, -- [out] + enUsrDlyCfg => enUsrDlyCfg, -- [in] + usrDlyCfg => usrDlyCfg, -- [in] + bypFirstBerDet => '1', -- [in] + minEyeWidth => minEyeWidthSync, -- [in] + lockingCntCfg => lockingCntCfg, -- [in] + errorDet => errorDet, -- [out] + locked => locked); -- [out] + + + ------------------------------------------------------------------------------------------------- + -- ADC Bit Clocked Logic + ------------------------------------------------------------------------------------------------- + adcComb : process (adcFrame, adcFrameValid, adcR) is + variable v : AdcRegType; + begin + v := adcR; + + if (adcFrameValid = '1') then + v.errorDet := toSl(adcFrame /= "11111110000000"); + end if; + + adcRin <= v; + + end process adcComb; + + adcSeq : process (adcBitClkDiv4, adcBitRstDiv4) is + begin + if (adcBitRstDiv4 = '1') then + adcR <= ADC_REG_INIT_C after TPD_G; + elsif (rising_edge(adcBitClkDiv4)) then + adcR <= adcRin after TPD_G; + end if; + end process adcSeq; + + + GLUE_COMB : process (adcData, invertSync, locked) is + begin + for ch in NUM_CHANNELS_G-1 downto 0 loop + if (locked = '1') then + -- Locked, output adc data + if invertSync = '1' then + -- Invert all bits but keep 2 LSBs clear + fifoWrData(ch) <= "00" & ("11111111111111" - adcData(ch)); + else + fifoWrData(ch) <= "00" & adcData(ch); + end if; + else + -- Not locked + fifoWrData(ch) <= (others => '1'); --"10" & "00000000000000"; + end if; + end loop; + end process GLUE_COMB; + + +-- Flatten fifoWrData onto fifoDataIn for FIFO +-- Regroup fifoDataOut by channel into fifoDataTmp +-- Format fifoDataTmp into AxiStream channels + glue : for i in NUM_CHANNELS_G-1 downto 0 generate + fifoDataIn(i*16+15 downto i*16) <= fifoWrData(i); + fifoDataTmp(i) <= fifoDataOut(i*16+15 downto i*16); + debugDataTmp(i) <= debugDataOut(i*16+15 downto i*16); + adcStreams(i).tdata(15 downto 0) <= fifoDataTmp(i); + adcStreams(i).tDest <= toSlv(i, 8); + adcStreams(i).tValid <= fifoDataValid; + end generate; + + -- Single fifo to synchronize adc data to the Stream clock + U_DataFifo : entity surf.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => NUM_CHANNELS_G*16, + ADDR_WIDTH_G => 4, + INIT_G => "0") + port map ( + rst => adcBitRstDiv4, + wr_clk => adcBitClkDiv4, + wr_en => adcFrameValid, --Always write data + din => fifoDataIn, + rd_clk => adcStreamClk, + rd_en => fifoDataValid, + valid => fifoDataValid, + dout => fifoDataOut); + + U_DataFifoDebug : entity surf.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + MEMORY_TYPE_G => "distributed", + DATA_WIDTH_G => NUM_CHANNELS_G*16, + ADDR_WIDTH_G => 4, + INIT_G => "0") + port map ( + rst => adcBitRstDiv4, + wr_clk => adcBitClkDiv4, + wr_en => adcFrameValid, --Always write data + din => fifoDataIn, + rd_clk => axilClk, + rd_en => debugDataValid, + valid => debugDataValid, + dout => debugDataOut); + + +end rtl; + diff --git a/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd b/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd index 694c68637f..02db1c9676 100644 --- a/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd +++ b/devices/AnalogDevices/ad9249/tb/Ad9249Group.vhd @@ -32,8 +32,8 @@ entity Ad9249Group is CLK_PERIOD_G : time := 24 ns; DIVCLK_DIVIDE_G : integer := 1; CLKFBOUT_MULT_G : integer := 49; - CLK_DCO_DIVIDE_G : integer := 49; - CLK_FCO_DIVIDE_G : integer := 7); + CLK_DCO_DIVIDE_G : integer := 7; + CLK_FCO_DIVIDE_G : integer := 49); port ( clk : in sl; @@ -230,31 +230,32 @@ begin -- Use a clock manager to create the serial clock -- There's probably a better way but this works. ------------------------------------------------------------------------------------------------- - U_CtrlClockManager7 : entity surf.ClockManager7 - generic map ( - TPD_G => TPD_G, - TYPE_G => "MMCM", - INPUT_BUFG_G => false, - FB_BUFG_G => true, - NUM_CLOCKS_G => 4, - BANDWIDTH_G => "HIGH", - CLKIN_PERIOD_G => CLK_PERIOD_C, - DIVCLK_DIVIDE_G => DIVCLK_DIVIDE_G, - CLKFBOUT_MULT_G => CLKFBOUT_MULT_G, - CLKOUT0_DIVIDE_G => CLK_FCO_DIVIDE_G, - CLKOUT1_DIVIDE_G => CLK_DCO_DIVIDE_G, - CLKOUT2_DIVIDE_G => CLK_DCO_DIVIDE_G, - CLKOUT2_PHASE_G => 90.0, - CLKOUT3_DIVIDE_G => CLK_FCO_DIVIDE_G, - CLKOUT3_PHASE_G => 257.143) - port map ( - clkIn => clk, - rstIn => pllRst, - clkOut(0) => fClk, - clkOut(1) => dClk, - clkOut(2) => dco, - clkOut(3) => fco, - locked => locked); + U_CtrlClockManager7 : entity surf.ClockManager7 + generic map ( + TPD_G => TPD_G, + TYPE_G => "PLL", + INPUT_BUFG_G => false, + FB_BUFG_G => true, + NUM_CLOCKS_G => 4, + BANDWIDTH_G => "HIGH", + CLKIN_PERIOD_G => CLK_PERIOD_C, + DIVCLK_DIVIDE_G => DIVCLK_DIVIDE_G, + CLKFBOUT_MULT_G => CLKFBOUT_MULT_G, + CLKOUT0_DIVIDE_G => CLK_FCO_DIVIDE_G, + CLKOUT1_DIVIDE_G => CLK_DCO_DIVIDE_G, + CLKOUT2_DIVIDE_G => CLK_DCO_DIVIDE_G, + CLKOUT2_PHASE_G => 90.0, + CLKOUT3_DIVIDE_G => CLK_FCO_DIVIDE_G, + CLKOUT3_PHASE_G => 257.143) + port map ( + clkIn => clk, + rstIn => pllRst, + clkOut(0) => fClk, + clkOut(1) => dClk, + clkOut(2) => dco, + clkOut(3) => fco, + locked => locked); + RstSync_1 : entity surf.RstSync diff --git a/devices/AnalogDevices/ruckus.tcl b/devices/AnalogDevices/ruckus.tcl index 0d3997bbe6..0e92b6ce04 100644 --- a/devices/AnalogDevices/ruckus.tcl +++ b/devices/AnalogDevices/ruckus.tcl @@ -10,4 +10,8 @@ if { $::env(VIVADO_VERSION) > 0.0} { loadRuckusTcl "$::DIR_PATH/ad9467" loadRuckusTcl "$::DIR_PATH/ad9249" loadRuckusTcl "$::DIR_PATH/ad9681" -} \ No newline at end of file + + # AD9249 sim model requires ClockManager7 + loadSource -lib surf -path "$::DIR_PATH/../../xilinx/7Series/general/rtl/ClockManager7.vhd" + loadSource -lib surf -path "$::DIR_PATH/../../xilinx/7Series/general/rtl/ClockManager7Pkg.vhd" +} diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd index fe12fd7e1a..b926d8164d 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcAxi.vhd @@ -6,96 +6,6 @@ -- Description: -- AXI-Lite block to manage the PGP (fc) interface. -- --- Address map (offset from base): --- 0x00 = Read/Write --- Bits 0 = Count Reset --- 0x04 = Read/Write --- Bits 0 = Reset Rx --- 0x08 = Read/Write --- Bits 0 = Flush --- 0x0C = Read/Write --- Bits 1:0 = Loop Back --- 0x10 = Read/Write --- Bits 7:0 = Sideband data to transmit --- Bits 8 = Sideband data enable --- 0x14 = Read/Write --- Bits 0 = Auto Status Send Enable (PPI) --- 0x18 = Read/Write --- Bits 0 = Disable Flow Control --- 0x20 = Read Only --- Bits 0 = Rx Phy Ready --- Bits 1 = Tx Phy Ready --- Bits 2 = Local Link Ready --- Bits 3 = Remote Link Ready --- Bits 4 = Transmit Ready --- Bits 9:8 = Receive Link Polarity --- Bits 15:12 = Remote Pause Status --- Bits 19:16 = Local Pause Status --- Bits 23:20 = Remote Overflow Status --- Bits 27:24 = Local Overflow Status --- 0x24 = Read Only --- Bits 7:0 = Remote Link Data --- 0x28 = Read Only --- Bits ?:0 = Cell Error Count --- 0x2C = Read Only --- Bits ?:0 = Link Down Count --- 0x30 = Read Only --- Bits ?:0 = Link Error Count --- 0x34 = Read Only --- Bits ?:0 = Remote Overflow VC 0 Count --- 0x38 = Read Only --- Bits ?:0 = Remote Overflow VC 1 Count --- 0x3C = Read Only --- Bits ?:0 = Remote Overflow VC 2 Count --- 0x40 = Read Only --- Bits ?:0 = Remote Overflow VC 3 Count --- 0x44 = Read Only --- Bits ?:0 = Receive Frame Error Count --- 0x48 = Read Only --- Bits ?:0 = Receive Frame Count --- 0x4C = Read Only --- Bits ?:0 = Local Overflow VC 0 Count --- 0x50 = Read Only --- Bits ?:0 = Local Overflow VC 1 Count --- 0x54 = Read Only --- Bits ?:0 = Local Overflow VC 2 Count --- 0x58 = Read Only --- Bits ?:0 = Local Overflow VC 3 Count --- 0x5C = Read Only --- Bits ?:0 = Transmit Frame Error Count --- 0x60 = Read Only --- Bits ?:0 = Transmit Frame Count --- 0x64 = Read Only --- Bits 31:0 = Receive Clock Frequency --- 0x68 = Read Only --- Bits 31:0 = Transmit Clock Frequency --- 0x70 = Read Only --- Bits ?:0 = Fast Control Sent Count --- 0x74 = Read Only --- Bits ?:0 = Fast Control Received Count --- 0x78 = Read Only --- Bits ?:0 = Fast Control Received Error Count --- 0xA0 = Read/Write --- Bits 0 = Reset link alignment block --- Bits 1 = Place link alignment block in manual mode --- 0xA4 = Write Only --- Bits ? = Issue an RXSLIDE, automatically cleared --- 0xA8 = Read Only --- Bits 0 = Alignment status --- Bits 1 = Asserted when RXSLIDE is done --- Bits 2 = Alignment Latency (0 or 1) --- Bits 3 = Alignment Latency Valid --- 0xAC = Write Only --- Bits ? = Issue a request to get the phase latency --- --- Status vector: --- Bits 31:24 = Rx Link Down Count --- Bits 23:16 = Rx Frame Error Count --- Bits 15:8 = Rx Cell Error Count --- Bits 7:6 = Zeros --- Bits 5 = Remote Link Ready --- Bits 4 = Local Link Ready --- Bits 3:0 = Remote Overflow Status ------------------------------------------------------------------------------- -- This file is part of 'SLAC Firmware Standard Library'. -- It is subject to the license terms in the LICENSE.txt file found in the @@ -124,36 +34,24 @@ entity Pgp2fcAxi is COMMON_RX_CLK_G : boolean := false; -- Set to true if axiClk and pgpRxClk are the same clock WRITE_EN_G : boolean := false; -- Set to false when on remote end of a link AXI_CLK_FREQ_G : real := 125.0E+6; + FC_WORDS_G : natural range 1 to 8 := 1; STATUS_CNT_WIDTH_G : natural range 1 to 32 := 32; ERROR_CNT_WIDTH_G : natural range 1 to 32 := 4); port ( -- TX PGP Interface (pgpTxClk domain) - pgpTxClk : in sl; - pgpTxClkRst : in sl; - pgpTxIn : out Pgp2fcTxCtrlInType; - pgpTxOut : in Pgp2fcTxStatusOutType; - locTxIn : in Pgp2fcTxCtrlInType := PGP2FC_TX_CTRL_IN_INIT_C; + pgpTxClk : in sl; + pgpTxClkRst : in sl; + pgpTxIn : out Pgp2fcTxInType; + pgpTxOut : in Pgp2fcTxOutType; + locTxIn : in Pgp2fcTxInType := PGP2FC_TX_IN_INIT_C; -- RX PGP Interface (pgpRxClk domain) pgpRxClk : in sl; pgpRxClkRst : in sl; - pgpRxIn : out Pgp2fcRxCtrlInType; - pgpRxOut : in Pgp2fcRxStatusOutType; - locRxIn : in Pgp2fcRxCtrlInType := PGP2FC_RX_CTRL_IN_INIT_C; - - -- RX PGP Link Alignment Control (axilClk domain) - linkAlignRst : out sl; - linkAligned : in sl := '0'; - linkAlignOverride : out sl; - linkAlignSlide : out sl; - linkAlignSlideDone : in sl := '0'; - linkAlignPhaseReq : out sl; - linkAlignPhase : in sl := '0'; - linkAlignPhaseValid : in sl := '0'; - - -- Protocol error for error tracking (pgpRxClk domain) - protocolError : in sl := '0'; + pgpRxIn : out Pgp2fcRxInType; + pgpRxOut : in Pgp2fcRxOutType; + locRxIn : in Pgp2fcRxInType := PGP2FC_RX_IN_INIT_C; -- Status Bus (axilClk domain) statusWord : out slv(63 downto 0); @@ -176,15 +74,15 @@ architecture structure of Pgp2fcAxi is -- Local signals signal rxStatusSend : sl; - signal rxErrorOut : slv(17 downto 0); - signal rxErrorCntOut : SlVectorArray(17 downto 0, ERROR_CNT_WIDTH_G-1 downto 0); + signal rxErrorOut : slv(16 downto 0); + signal rxErrorCntOut : SlVectorArray(16 downto 0, ERROR_CNT_WIDTH_G-1 downto 0); signal rxStatusCntOut : SlVectorArray(0 downto 0, STATUS_CNT_WIDTH_G-1 downto 0); signal txErrorOut : slv(11 downto 0); signal txErrorCntOut : SlVectorArray(11 downto 0, ERROR_CNT_WIDTH_G-1 downto 0); signal txStatusCntOut : SlVectorArray(0 downto 0, STATUS_CNT_WIDTH_G-1 downto 0); - signal rxErrorIrqEn : slv(17 downto 0); + signal rxErrorIrqEn : slv(16 downto 0); signal locTxDataEn : sl; signal locTxData : slv(7 downto 0); signal txFlush : sl; @@ -243,7 +141,6 @@ architecture structure of Pgp2fcAxi is cellErrorCount : slv(ERROR_CNT_WIDTH_G-1 downto 0); linkDownCount : slv(ERROR_CNT_WIDTH_G-1 downto 0); linkErrorCount : slv(ERROR_CNT_WIDTH_G-1 downto 0); - remOverflow : slv(3 downto 0); remOverflow0Cnt : slv(ERROR_CNT_WIDTH_G-1 downto 0); remOverflow1Cnt : slv(ERROR_CNT_WIDTH_G-1 downto 0); @@ -253,13 +150,7 @@ architecture structure of Pgp2fcAxi is frameCount : slv(STATUS_CNT_WIDTH_G-1 downto 0); remPause : slv(3 downto 0); rxClkFreq : slv(31 downto 0); - - aligned : sl; - alignSlideDone : sl; - alignPhase : sl; - alignPhaseValid : sl; - protocolErrorCount : slv(ERROR_CNT_WIDTH_G-1 downto 0); - + rxFcWordLast : slv(FC_WORDS_G*16-1 downto 0); rxFcRecvCount : slv(ERROR_CNT_WIDTH_G-1 downto 0); rxFcErrCount : slv(ERROR_CNT_WIDTH_G-1 downto 0); end record RxStatusType; @@ -278,7 +169,7 @@ architecture structure of Pgp2fcAxi is frameErrCount : slv(ERROR_CNT_WIDTH_G-1 downto 0); frameCount : slv(STATUS_CNT_WIDTH_G-1 downto 0); txClkFreq : slv(31 downto 0); - + txFcWordLast : slv(FC_WORDS_G*16-1 downto 0); txFcSentCount : slv(ERROR_CNT_WIDTH_G-1 downto 0); end record TxStatusType; @@ -287,10 +178,32 @@ architecture structure of Pgp2fcAxi is begin + + --------------------------------------- -- Receive Status --------------------------------------- + -- OpCode Capture + U_RxFcWordSync : entity surf.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + MEMORY_TYPE_G => "distributed", + SYNC_STAGES_G => 3, + DATA_WIDTH_G => FC_WORDS_G*16, + ADDR_WIDTH_G => 2, + INIT_G => "0") + port map ( + rst => r.countReset, + wr_clk => pgpRxClk, + wr_en => pgpRxOut.fcValid, + din => pgpRxOut.fcWord(FC_WORDS_G*16-1 downto 0), + rd_clk => axilClk, + rd_en => '1', + valid => open, + dout => rxStatusSync.rxFcWordLast); + + -- Sync remote data U_RxDataSyncEn : if COMMON_RX_CLK_G = false generate U_RxDataSync : entity surf.SynchronizerFifo @@ -325,10 +238,10 @@ begin SYNC_STAGES_G => 3, IN_POLARITY_G => "1", OUT_POLARITY_G => '1', - SYNTH_CNT_G => "111111100001111100", + SYNTH_CNT_G => "11111100001111100", CNT_RST_EDGE_G => false, CNT_WIDTH_G => ERROR_CNT_WIDTH_G, - WIDTH_G => 18) + WIDTH_G => 17) port map ( statusIn(0) => pgpRxOut.phyRxReady, statusIn(1) => pgpRxOut.linkReady, @@ -339,9 +252,8 @@ begin statusIn(12) => pgpRxOut.linkDown, statusIn(13) => pgpRxOut.linkError, statusIn(14) => pgpRxOut.frameRxErr, - statusIn(15) => pgpRxOut.fcRecv, - statusIn(16) => pgpRxOut.fcRecvErr, - statusIn(17) => protocolError, + statusIn(15) => pgpRxOut.fcValid, + statusIn(16) => pgpRxOut.fcError, statusOut => rxErrorOut, cntRstIn => r.countReset, rollOverEnIn => (others => '0'), @@ -365,7 +277,6 @@ begin rxErrorIrqEn(13) <= r.autoStatus; rxErrorIrqEn(14) <= r.autoStatus; rxErrorIrqEn(16) <= r.autoStatus; - rxErrorIrqEn(17) <= r.autoStatus; end process; -- map status @@ -387,12 +298,6 @@ begin rxStatusSync.frameErrCount <= muxSlVectorArray(rxErrorCntOut, 14); rxStatusSync.rxFcRecvCount <= muxSlVectorArray(rxErrorCntOut, 15); rxStatusSync.rxFcErrCount <= muxSlVectorArray(rxErrorCntOut, 16); - rxStatusSync.protocolErrorCount <= muxSlVectorArray(rxErrorCntOut, 17); - - rxStatusSync.aligned <= linkAligned; - rxStatusSync.alignSlideDone <= linkAlignSlideDone; - rxStatusSync.alignPhase <= linkAlignPhase; - rxStatusSync.alignPhaseValid <= linkAlignPhaseValid; -- Status counters U_RxStatus : entity surf.SyncStatusVector @@ -444,6 +349,25 @@ begin --------------------------------------- -- Transmit Status --------------------------------------- + -- FC Word Capture + U_TxFcWordSync : entity surf.SynchronizerFifo + generic map ( + TPD_G => TPD_G, + MEMORY_TYPE_G => "distributed", + SYNC_STAGES_G => 3, + DATA_WIDTH_G => FC_WORDS_G*16, + ADDR_WIDTH_G => 2, + INIT_G => "0") + port map ( + rst => r.countReset, + wr_clk => pgpTxClk, + wr_en => locTxIn.fcValid, + din => locTxIn.fcWord(FC_WORDS_G*16-1 downto 0), + rd_clk => axilClk, + rd_en => '1', + valid => open, + dout => txStatusSync.txFcWordLast); + -- Errror counters and non counted values U_TxError : entity surf.SyncStatusVector @@ -607,10 +531,10 @@ begin pgpRxIn.resetRx <= locRxIn.resetRx or rxReset; pgpRxIn.loopback <= locRxIn.loopback or r.loopBack; - linkAlignRst <= r.alignRst; - linkAlignOverride <= r.alignOverride; - linkAlignSlide <= r.alignSlide; - linkAlignPhaseReq <= r.alignPhaseReq; +-- linkAlignRst <= r.alignRst; +-- linkAlignOverride <= r.alignOverride; +-- linkAlignSlide <= r.alignSlide; +-- linkAlignPhaseReq <= r.alignPhaseReq; @@ -628,147 +552,65 @@ begin -- Async process (axilRst, axilReadMaster, axilWriteMaster, r, rxStatusSync, txStatusSync) is - variable v : RegType; - variable axiStatus : AxiLiteStatusType; + variable v : RegType; + variable axilEp : AxiLiteEndpointType; begin v := r; -- Automatic clear - v.alignSlide := '0'; + v.alignSlide := '0'; v.alignPhaseReq := '0'; - axiSlaveWaitTxn(axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave, axiStatus); - - -- Write - if (axiStatus.writeEnable = '1') then - - -- Decode address and perform write - case (axilWriteMaster.awaddr(7 downto 0)) is - when X"00" => - v.countReset := axilWriteMaster.wdata(0); - when X"04" => - v.resetRx := ite(WRITE_EN_G, axilWriteMaster.wdata(0), '0'); - v.resetTx := ite(WRITE_EN_G, axilWriteMaster.wdata(1), '0'); - v.resetGt := ite(WRITE_EN_G, axilWriteMaster.wdata(2), '0'); - when X"08" => - v.flush := ite(WRITE_EN_G, axilWriteMaster.wdata(0), '0'); - when X"0C" => - v.loopBack := ite(WRITE_EN_G, axilWriteMaster.wdata(2 downto 0), "000"); - when X"10" => - v.locDataEn := axilWriteMaster.wdata(8); - v.locData := axilWriteMaster.wdata(7 downto 0); - when X"14" => - v.autoStatus := axilWriteMaster.wdata(0); - when X"18" => - v.flowCntlDis := ite(WRITE_EN_G, axilWriteMaster.wdata(0), '0'); - when X"A0" => - v.alignRst := ite(WRITE_EN_G, axilWriteMaster.wdata(0), '0'); - v.alignOverride := ite(WRITE_EN_G, axilWriteMaster.wdata(1), '0'); - when X"A4" => - v.alignSlide := ite(WRITE_EN_G, '1', '0'); - when X"AC" => - v.alignPhaseReq := ite(WRITE_EN_G, '1', '0'); - when others => null; - end case; - - -- Send Axi response - axiSlaveWriteResponse(v.axilWriteSlave); - end if; + axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave); - -- Read - if (axiStatus.readEnable = '1') then - - -- Decode address and assign read data - case axilReadMaster.araddr(7 downto 0) is - when X"00" => - v.axilReadSlave.rdata(0) := r.countReset; - when X"04" => - v.axilReadSlave.rdata(0) := r.resetRx; - v.axilReadSlave.rdata(1) := r.resetTx; - v.axilReadSlave.rdata(2) := r.resetGt; - when X"08" => - v.axilReadSlave.rdata(0) := r.flush; - when X"0C" => - v.axilReadSlave.rdata(2 downto 0) := r.loopBack; - when X"10" => - v.axilReadSlave.rdata(8) := r.locDataEn; - v.axilReadSlave.rdata(7 downto 0) := r.locData; - when X"14" => - v.axilReadSlave.rdata(0) := r.autoStatus; - when X"18" => - v.axilReadSlave.rdata(0) := r.flowCntlDis; - when X"20" => - v.axilReadSlave.rdata(0) := rxStatusSync.phyRxReady; - v.axilReadSlave.rdata(1) := txStatusSync.phyTxReady; - v.axilReadSlave.rdata(2) := rxStatusSync.locLinkReady; - v.axilReadSlave.rdata(3) := rxStatusSync.remLinkReady; - v.axilReadSlave.rdata(4) := txStatusSync.txLinkReady; - v.axilReadSlave.rdata(9 downto 8) := "00"; - v.axilReadSlave.rdata(15 downto 12) := rxStatusSync.remPause; - v.axilReadSlave.rdata(19 downto 16) := txStatusSync.locPause; - v.axilReadSlave.rdata(23 downto 20) := rxStatusSync.remOverflow; - v.axilReadSlave.rdata(27 downto 24) := txStatusSync.locOverflow; - when X"24" => - v.axilReadSlave.rdata(7 downto 0) := rxStatusSync.remLinkData; - when X"28" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.cellErrorCount; - when X"2C" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.linkDownCount; - when X"30" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.linkErrorCount; - when X"34" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.remOverflow0Cnt; - when X"38" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.remOverflow1Cnt; - when X"3C" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.remOverflow2Cnt; - when X"40" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.remOverflow3Cnt; - when X"44" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.frameErrCount; - when X"48" => - v.axilReadSlave.rdata(STATUS_CNT_WIDTH_G-1 downto 0) := rxStatusSync.frameCount; - when X"4C" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := txStatusSync.locOverflow0Cnt; - when X"50" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := txStatusSync.locOverflow1Cnt; - when X"54" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := txStatusSync.locOverflow2Cnt; - when X"58" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := txStatusSync.locOverflow3Cnt; - when X"5C" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := txStatusSync.frameErrCount; - when X"60" => - v.axilReadSlave.rdata(STATUS_CNT_WIDTH_G-1 downto 0) := txStatusSync.frameCount; - when X"64" => - v.axilReadSlave.rdata := rxStatusSync.rxClkFreq; - when X"68" => - v.axilReadSlave.rdata := txStatusSync.txClkFreq; - when X"70" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := txStatusSync.txFcSentCount; - when X"74" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.rxFcRecvCount; - when X"78" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.rxFcErrCount; - when X"7C" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.remLinkReadyCnt; - when X"A0" => - v.axilReadSlave.rdata(0) := r.alignRst; - v.axilReadSlave.rdata(1) := r.alignOverride; - when X"A8" => - v.axilReadSlave.rdata(0) := rxStatusSync.aligned; - v.axilReadSlave.rdata(1) := rxStatusSync.alignSlideDone; - v.axilReadSlave.rdata(2) := rxStatusSync.alignPhase; - v.axilReadSlave.rdata(3) := rxStatusSync.alignPhaseValid; - when X"B0" => - v.axilReadSlave.rdata(ERROR_CNT_WIDTH_G-1 downto 0) := rxStatusSync.protocolErrorCount; - - when others => null; - end case; - - -- Send Axi Response - axiSlaveReadResponse(v.axilReadSlave); + axiSlaveRegister(axilEp, X"00", 0, v.countReset); + if (WRITE_EN_G) then + axiSlaveRegister(axilEp, X"04", 0, v.resetRx); + axiSlaveRegister(axilEp, X"04", 1, v.resetTx); + axiSlaveRegister(axilEp, X"04", 2, v.resetGt); + axiSlaveRegister(axilEp, X"08", 0, v.flush); + axiSlaveRegister(axilEp, X"0C", 0, v.loopback); + axiSlaveRegister(axilEp, X"18", 0, v.flowCntlDis); end if; + axiSlaveRegister(axilEp, X"10", 0, v.locData); + axiSlaveRegister(axilEp, X"10", 8, v.locDataEn); + axiSlaveRegister(axilEp, X"14", 0, v.autoStatus); + + axiSlaveRegisterR(axilEp, X"20", 0, rxStatusSync.phyRxReady); + axiSlaveRegisterR(axilEp, X"20", 1, txStatusSync.phyTxReady); + axiSlaveRegisterR(axilEp, X"20", 2, rxStatusSync.locLinkReady); + axiSlaveRegisterR(axilEp, X"20", 3, rxStatusSync.remLinkReady); + axiSlaveRegisterR(axilEp, X"20", 4, txStatusSync.txLinkReady); + axiSlaveRegisterR(axilEp, X"20", 12, rxStatusSync.remPause); + axiSlaveRegisterR(axilEp, X"20", 16, txStatusSync.locPause); + axiSlaveRegisterR(axilEp, X"20", 20, rxStatusSync.remOverflow); + axiSlaveRegisterR(axilEp, X"20", 24, txStatusSync.locOverflow); + axiSlaveRegisterR(axilEp, X"24", 0, rxStatusSync.remLinkData); + axiSlaveRegisterR(axilEp, X"28", 0, rxStatusSync.cellErrorCount); + axiSlaveRegisterR(axilEp, X"2C", 0, rxStatusSync.linkDownCount); + axiSlaveRegisterR(axilEp, X"30", 0, rxStatusSync.linkErrorCount); + axiSlaveRegisterR(axilEp, X"34", 0, rxStatusSync.remOverflow0Cnt); + axiSlaveRegisterR(axilEp, X"38", 0, rxStatusSync.remOverflow1Cnt); + axiSlaveRegisterR(axilEp, X"3C", 0, rxStatusSync.remOverflow2Cnt); + axiSlaveRegisterR(axilEp, X"40", 0, rxStatusSync.remOverflow3Cnt); + axiSlaveRegisterR(axilEp, X"44", 0, rxStatusSync.frameErrCount); + axiSlaveRegisterR(axilEp, X"48", 0, rxStatusSync.frameCount); + axiSlaveRegisterR(axilEp, X"4C", 0, txStatusSync.locOverflow0Cnt); + axiSlaveRegisterR(axilEp, X"50", 0, txStatusSync.locOverflow1Cnt); + axiSlaveRegisterR(axilEp, X"54", 0, txStatusSync.locOverflow2Cnt); + axiSlaveRegisterR(axilEp, X"58", 0, txStatusSync.locOverflow3Cnt); + axiSlaveRegisterR(axilEp, X"5C", 0, txStatusSync.frameErrCount); + axiSlaveRegisterR(axilEp, X"60", 0, txStatusSync.frameCount); + axiSlaveRegisterR(axilEp, X"64", 0, rxStatusSync.rxClkFreq); + axiSlaveRegisterR(axilEp, X"68", 0, txStatusSync.txClkFreq); + axiSlaveRegisterR(axilEp, X"70", 0, txStatusSync.txFcSentCount); + axiSlaveRegisterR(axilEp, X"74", 0, rxStatusSync.rxFcRecvCount); + axiSlaveRegisterR(axilEp, X"78", 0, rxStatusSync.rxFcErrCount); + axiSlaveRegisterR(axilEp, X"7C", 0, rxStatusSync.remLinkReadyCnt); + axiSlaveRegisterR(axilEp, X"80", 0, txStatusSync.txFcWordLast); -- up to 128 bit word + axiSlaveRegisterR(axilEp, X"90", 0, rxStatusSync.rxFcWordLast); -- up to 128 bit word + + axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C); -- Reset if (axilRst = '1') then diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd index 9e0297b819..0b0df8210a 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcLane.vhd @@ -15,7 +15,7 @@ -- the terms contained in the LICENSE.txt file. ------------------------------------------------------------------------------- -LIBRARY ieee; +library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; @@ -29,14 +29,14 @@ use surf.SsiPkg.all; entity Pgp2fcLane is generic ( - TPD_G : time := 1 ns; - FC_WORDS_G : integer range 1 to 4 := 1; -- Number of lanes, 1-2 - VC_INTERLEAVE_G : integer := 1; -- Interleave Frames - PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter - NUM_VC_EN_G : integer range 1 to 4 := 4; - TX_ENABLE_G : boolean := true; -- Enable TX direction - RX_ENABLE_G : boolean := true -- Enable RX direction - ); + TPD_G : time := 1 ns; + FC_WORDS_G : integer range 1 to 8 := 1; -- Number of words in FC bus + VC_INTERLEAVE_G : integer := 1; -- Interleave Frames + PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter + NUM_VC_EN_G : integer range 1 to 4 := 4; + TX_ENABLE_G : boolean := true; -- Enable TX direction + RX_ENABLE_G : boolean := true -- Enable RX direction + ); port ( --------------------------------- @@ -44,55 +44,47 @@ entity Pgp2fcLane is --------------------------------- -- System clock, reset & control - pgpTxClkEn : in sl := '1'; - pgpTxClk : in sl := '0'; - pgpTxClkRst : in sl := '0'; - - -- Fast control input interface - fcTxSend : in sl := '0'; - fcTxWord : in slv(16*FC_WORDS_G-1 downto 0) := (others => '0'); + pgpTxClkEn : in sl := '1'; + pgpTxClk : in sl := '0'; + pgpTxClkRst : in sl := '0'; -- Non-VC related IO - pgpTxIn : in Pgp2fcTxCtrlInType := PGP2FC_TX_CTRL_IN_INIT_C; - pgpTxOut : out Pgp2fcTxStatusOutType; + pgpTxIn : in Pgp2fcTxInType := PGP2FC_TX_IN_INIT_C; + pgpTxOut : out Pgp2fcTxOutType; -- VC Interface - pgpTxMasters : in AxiStreamMasterArray(3 downto 0) := (others=>AXI_STREAM_MASTER_INIT_C); - pgpTxSlaves : out AxiStreamSlaveArray(3 downto 0); + pgpTxMasters : in AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + pgpTxSlaves : out AxiStreamSlaveArray(3 downto 0); -- Phy interface - phyTxLaneOut : out Pgp2fcTxPhyLaneOutType; - phyTxReady : in sl := '0'; + phyTxLaneOut : out Pgp2fcTxPhyLaneOutType; + phyTxReady : in sl := '0'; --------------------------------- -- Receiver Interface --------------------------------- -- System clock, reset & control - pgpRxClkEn : in sl := '1'; - pgpRxClk : in sl := '0'; - pgpRxClkRst : in sl := '0'; - - -- Fast control output interface - fcRxRecv : out sl; - fcRxWord : out slv(16*FC_WORDS_G-1 downto 0); + pgpRxClkEn : in sl := '1'; + pgpRxClk : in sl := '0'; + pgpRxClkRst : in sl := '0'; -- Non-VC related IO - pgpRxIn : in Pgp2fcRxCtrlInType := PGP2FC_RX_CTRL_IN_INIT_C; - pgpRxOut : out Pgp2fcRxStatusOutType; + pgpRxIn : in Pgp2fcRxInType := PGP2FC_RX_IN_INIT_C; + pgpRxOut : out Pgp2fcRxOutType; -- VC Outputs - pgpRxMasters : out AxiStreamMasterArray(3 downto 0); - pgpRxMasterMuxed : out AxiStreamMasterType; + pgpRxMasters : out AxiStreamMasterArray(3 downto 0); + pgpRxMasterMuxed : out AxiStreamMasterType; -- Receive flow control - pgpRxCtrl : in AxiStreamCtrlArray(3 downto 0) := (others=>AXI_STREAM_CTRL_UNUSED_C); + pgpRxCtrl : in AxiStreamCtrlArray(3 downto 0) := (others => AXI_STREAM_CTRL_UNUSED_C); -- PHY interface - phyRxLaneIn : in Pgp2fcRxPhyLaneInType; - phyRxReady : in sl := '0'; - phyRxInit : out sl - ); + phyRxLaneIn : in Pgp2fcRxPhyLaneInType; + phyRxReady : in sl := '0'; + phyRxInit : out sl + ); end Pgp2fcLane; @@ -103,7 +95,7 @@ architecture Pgp2fcLane of Pgp2fcLane is -- Local Signals signal intRxMaster : AxiStreamMasterType; signal remFifoStatus : AxiStreamCtrlArray(3 downto 0); - signal intRxOut : Pgp2fcRxStatusOutType; + signal intRxOut : Pgp2fcRxOutType; begin @@ -111,38 +103,36 @@ begin -- Transmit ----------------------------- - U_TxEnGen: if TX_ENABLE_G = true generate + U_TxEnGen : if TX_ENABLE_G = true generate -- Transmit - U_Pgp2fcTx: entity surf.Pgp2fcTx + U_Pgp2fcTx : entity surf.Pgp2fcTx generic map ( - TPD_G => TPD_G, - FC_WORDS_G => FC_WORDS_G, - VC_INTERLEAVE_G => VC_INTERLEAVE_G, - PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G, - NUM_VC_EN_G => NUM_VC_EN_G - ) port map ( - pgpTxClkEn => pgpTxClkEn, - pgpTxClk => pgpTxClk, - pgpTxClkRst => pgpTxClkRst, - fcSend => fcTxSend, - fcWord => fcTxWord, - pgpTxIn => pgpTxIn, - pgpTxOut => pgpTxOut, - locLinkReady => intRxOut.linkReady, - pgpTxMasters => pgpTxMasters, - pgpTxSlaves => pgpTxSlaves, - locFifoStatus => pgpRxCtrl, - remFifoStatus => remFifoStatus, - phyTxLaneOut => phyTxLaneOut, - phyTxReady => phyTxReady - ); + TPD_G => TPD_G, + FC_WORDS_G => FC_WORDS_G, + VC_INTERLEAVE_G => VC_INTERLEAVE_G, + PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G, + NUM_VC_EN_G => NUM_VC_EN_G + ) port map ( + pgpTxClkEn => pgpTxClkEn, + pgpTxClk => pgpTxClk, + pgpTxClkRst => pgpTxClkRst, + pgpTxIn => pgpTxIn, + pgpTxOut => pgpTxOut, + locLinkReady => intRxOut.linkReady, + pgpTxMasters => pgpTxMasters, + pgpTxSlaves => pgpTxSlaves, + locFifoStatus => pgpRxCtrl, + remFifoStatus => remFifoStatus, + phyTxLaneOut => phyTxLaneOut, + phyTxReady => phyTxReady + ); end generate; - U_TxDisGen: if TX_ENABLE_G = false generate - pgpTxOut <= PGP2FC_TX_STATUS_OUT_INIT_C; - pgpTxSlaves <= (others=>AXI_STREAM_SLAVE_INIT_C); - phyTxLaneOut <= PGP2FC_TX_PHY_LANE_OUT_INIT_C; + U_TxDisGen : if TX_ENABLE_G = false generate + pgpTxOut <= PGP2FC_TX_OUT_INIT_C; + pgpTxSlaves <= (others => AXI_STREAM_SLAVE_INIT_C); + phyTxLaneOut <= PGP2FC_TX_PHY_LANE_OUT_INIT_C; end generate; @@ -150,51 +140,49 @@ begin -- Receive ----------------------------- - U_RxEnGen: if RX_ENABLE_G = true generate + U_RxEnGen : if RX_ENABLE_G = true generate -- Receive - U_Pgp2fcRx: entity surf.Pgp2fcRx + U_Pgp2fcRx : entity surf.Pgp2fcRx generic map ( - TPD_G => TPD_G, - FC_WORDS_G => FC_WORDS_G, - PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G - ) port map ( - pgpRxClkEn => pgpRxClkEn, - pgpRxClk => pgpRxClk, - pgpRxClkRst => pgpRxClkRst, - fcRecv => fcRxRecv, - fcWord => fcRxWord, - pgpRxIn => pgpRxIn, - pgpRxOut => intRxOut, - pgpRxMaster => intRxMaster, - remFifoStatus => remFifoStatus, - phyRxLaneIn => phyRxLaneIn, - phyRxReady => phyRxReady, - phyRxInit => phyRxInit - ); + TPD_G => TPD_G, + FC_WORDS_G => FC_WORDS_G, + PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G + ) port map ( + pgpRxClkEn => pgpRxClkEn, + pgpRxClk => pgpRxClk, + pgpRxClkRst => pgpRxClkRst, + pgpRxIn => pgpRxIn, + pgpRxOut => intRxOut, + pgpRxMaster => intRxMaster, + remFifoStatus => remFifoStatus, + phyRxLaneIn => phyRxLaneIn, + phyRxReady => phyRxReady, + phyRxInit => phyRxInit + ); -- Demux U_RxDeMux : entity surf.AxiStreamDeMux generic map ( TPD_G => TPD_G, NUM_MASTERS_G => 4 - ) port map ( - axisClk => pgpRxClk, - axisRst => pgpRxClkRst, - sAxisMaster => intRxMaster, - sAxisSlave => open, - mAxisMasters => pgpRxMasters, - mAxisSlaves => (others=>AXI_STREAM_SLAVE_FORCE_C) - ); + ) port map ( + axisClk => pgpRxClk, + axisRst => pgpRxClkRst, + sAxisMaster => intRxMaster, + sAxisSlave => open, + mAxisMasters => pgpRxMasters, + mAxisSlaves => (others => AXI_STREAM_SLAVE_FORCE_C) + ); end generate; - U_RxDisGen: if RX_ENABLE_G = false generate - intRxOut <= PGP2FC_RX_STATUS_OUT_INIT_C; - pgpRxMasters <= (others=>AXI_STREAM_MASTER_INIT_C); - intRxMaster <= AXI_STREAM_MASTER_INIT_C; - phyRxInit <= '0'; - remFifoStatus <= (others=>AXI_STREAM_CTRL_UNUSED_C); + U_RxDisGen : if RX_ENABLE_G = false generate + intRxOut <= PGP2FC_RX_OUT_INIT_C; + pgpRxMasters <= (others => AXI_STREAM_MASTER_INIT_C); + intRxMaster <= AXI_STREAM_MASTER_INIT_C; + phyRxInit <= '0'; + remFifoStatus <= (others => AXI_STREAM_CTRL_UNUSED_C); end generate; -- De-Muxed Version diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd index a0eb2ef6ae..272039e8bf 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcPkg.vhd @@ -28,7 +28,7 @@ package Pgp2fcPkg is ----------------------------------------------------- -- Constants ----------------------------------------------------- - constant SSI_PGP2FC_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(2, TKEEP_COMP_C); + constant PGP2FC_AXIS_CONFIG_C : AxiStreamConfigType := ssiAxiStreamConfig(2, TKEEP_COMP_C); -- 8B10B Characters constant K_FCD_C : slv(7 downto 0) := "10111100"; -- K28.5, 0xBC @@ -47,51 +47,56 @@ package Pgp2fcPkg is -- ID Constant constant PGP2FC_ID_C : slv(3 downto 0) := "0111"; + constant MAX_FC_WORDS_C : integer := 8; + constant MAX_FC_BITS_C : integer := MAX_FC_WORDS_C * 16; + ----------------------------------------------------- -- PGP RX non-data types ----------------------------------------------------- - type Pgp2fcRxCtrlInType is record + type Pgp2fcRxInType is record flush : sl; -- Flush the link resetRx : sl; -- Reset RX transceiver path loopback : slv(2 downto 0); -- Transceiver loopback - end record Pgp2fcRxCtrlInType; + end record Pgp2fcRxInType; - type Pgp2fcRxCtrlInArray is array (natural range <>) of Pgp2fcRxCtrlInType; + type Pgp2fcRxInArray is array (natural range <>) of Pgp2fcRxInType; - constant PGP2FC_RX_CTRL_IN_INIT_C : Pgp2fcRxCtrlInType := ( + constant PGP2FC_RX_IN_INIT_C : Pgp2fcRxInType := ( flush => '0', resetRx => '0', loopback => "000"); - type Pgp2fcRxStatusOutType is record - phyRxReady : sl; -- RX Phy is ready - linkReady : sl; -- Local side has link - fcRecv : sl; -- Fast Control word received - fcRecvErr : sl; -- Fast Control word received with error - frameRx : sl; -- A good frame was received - frameRxErr : sl; -- An errored frame was received - cellError : sl; -- A cell error has occured - linkDown : sl; -- A link down event has occured - linkError : sl; -- A link error has occured - remLinkReady : sl; -- Far end side has link - remLinkData : slv(7 downto 0); -- Far end side User Data - remOverflow : slv(3 downto 0); -- Far end overflow status - remPause : slv(3 downto 0); -- Far end pause status - end record Pgp2fcRxStatusOutType; - - type Pgp2fcRxStatusOutArray is array (natural range <>) of Pgp2fcRxStatusOutType; - - constant PGP2FC_RX_STATUS_OUT_INIT_C : Pgp2fcRxStatusOutType := ( + type Pgp2fcRxOutType is record + phyRxReady : sl; -- RX Phy is ready + linkReady : sl; -- Local side has link + frameRx : sl; -- A good frame was received + frameRxErr : sl; -- An errored frame was received + cellError : sl; -- A cell error has occured + linkDown : sl; -- A link down event has occured + linkError : sl; -- A link error has occured + fcValid : sl; -- Fast Control word received + fcError : sl; -- Fast Control word received with error + fcWord : slv(MAX_FC_BITS_C-1 downto 0); -- Fast control word + remLinkReady : sl; -- Far end side has link + remLinkData : slv(7 downto 0); -- Far end side User Data + remOverflow : slv(3 downto 0); -- Far end overflow status + remPause : slv(3 downto 0); -- Far end pause status + end record Pgp2fcRxOutType; + + type Pgp2fcRxOutArray is array (natural range <>) of Pgp2fcRxOutType; + + constant PGP2FC_RX_OUT_INIT_C : Pgp2fcRxOutType := ( phyRxReady => '0', linkReady => '0', - fcRecv => '0', - fcRecvErr => '0', frameRx => '0', frameRxErr => '0', cellError => '0', linkDown => '0', linkError => '0', + fcValid => '0', + fcError => '0', + fcWord => (others => '0'), remLinkReady => '0', remLinkData => (others => '0'), remOverflow => (others => '0'), @@ -101,31 +106,37 @@ package Pgp2fcPkg is -- PGP2FC TX non-data types ----------------------------------------------------- - type Pgp2fcTxCtrlInType is record - flush : sl; -- Flush the link - locData : slv(7 downto 0); -- Near end side User Data - flowCntlDis : sl; -- Ignore flow control - resetTx : sl; -- Reset tx phy + type Pgp2fcTxInType is record + flush : sl; -- Flush the link + fcValid : sl; -- Fast Control word send + fcWord : slv(MAX_FC_BITS_C-1 downto 0); -- Fast Control word + locData : slv(7 downto 0); -- Near end side User Data + flowCntlDis : sl; -- Ignore flow control + resetTx : sl; -- Reset tx phy resetGt : sl; - end record Pgp2fcTxCtrlInType; + end record Pgp2fcTxInType; - type Pgp2fcTxCtrlInArray is array (natural range <>) of Pgp2fcTxCtrlInType; + type Pgp2fcTxInArray is array (natural range <>) of Pgp2fcTxInType; - constant PGP2FC_TX_CTRL_IN_INIT_C : Pgp2fcTxCtrlInType := ( + constant PGP2FC_TX_IN_INIT_C : Pgp2fcTxInType := ( flush => '0', + fcValid => '0', + fcWord => (others => '0'), locData => (others => '0'), flowCntlDis => '0', resetTx => '0', resetGt => '0'); - constant PGP2FC_TX_CTRL_IN_HALF_DUPLEX_C : Pgp2fcTxCtrlInType := ( + constant PGP2FC_TX_IN_HALF_DUPLEX_C : Pgp2fcTxInType := ( flush => '0', + fcValid => '0', + fcWord => (others => '0'), locData => (others => '0'), flowCntlDis => '1', resetTx => '0', resetGt => '0'); - type Pgp2fcTxStatusOutType is record + type Pgp2fcTxOutType is record locOverflow : slv(3 downto 0); -- Local overflow status locPause : slv(3 downto 0); -- Local pause status phyTxReady : sl; -- TX Phy is ready @@ -133,11 +144,11 @@ package Pgp2fcPkg is fcSent : sl; -- Fast Control word sent frameTx : sl; -- A good frame was transmitted frameTxErr : sl; -- An errored frame was transmitted - end record Pgp2fcTxStatusOutType; + end record Pgp2fcTxOutType; - type Pgp2fcTxStatusOutArray is array (natural range <>) of Pgp2fcTxStatusOutType; + type Pgp2fcTxOutArray is array (natural range <>) of Pgp2fcTxOutType; - constant PGP2FC_TX_STATUS_OUT_INIT_C : Pgp2fcTxStatusOutType := ( + constant PGP2FC_TX_OUT_INIT_C : Pgp2fcTxOutType := ( locOverflow => (others => '0'), locPause => (others => '0'), phyTxReady => '0', diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd index 3ffff4a02a..a01be22242 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRx.vhd @@ -15,7 +15,7 @@ -- the terms contained in the LICENSE.txt file. ------------------------------------------------------------------------------- -LIBRARY ieee; +library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; @@ -29,34 +29,29 @@ use surf.SsiPkg.all; entity Pgp2fcRx is generic ( TPD_G : time := 1 ns; - FC_WORDS_G : integer range 1 to 4 := 1; + FC_WORDS_G : integer range 1 to 8 := 1; PAYLOAD_CNT_TOP_G : integer := 7 -- Top bit for payload counter - ); + ); port ( -- System clock, reset & control - pgpRxClkEn : in sl := '1'; -- Master clock enable - pgpRxClk : in sl; -- Master clock - pgpRxClkRst : in sl; -- Synchronous reset input - - -- Fast control interface - fcRecv : out sl := '0'; - fcWord : out slv(16*FC_WORDS_G-1 downto 0); - fcErr : out sl := '0'; + pgpRxClkEn : in sl := '1'; -- Master clock enable + pgpRxClk : in sl; -- Master clock + pgpRxClkRst : in sl; -- Synchronous reset input -- Non-VC related IO - pgpRxIn : in Pgp2fcRxCtrlInType; - pgpRxOut : out Pgp2fcRxStatusOutType; + pgpRxIn : in Pgp2fcRxInType; + pgpRxOut : out Pgp2fcRxOutType := PGP2FC_RX_OUT_INIT_C; -- VC Output - pgpRxMaster : out AxiStreamMasterType; - remFifoStatus : out AxiStreamCtrlArray(3 downto 0); + pgpRxMaster : out AxiStreamMasterType; + remFifoStatus : out AxiStreamCtrlArray(3 downto 0); -- PHY interface - phyRxLaneIn : in Pgp2fcRxPhyLaneInType; - phyRxReady : in sl; - phyRxInit : out sl - ); + phyRxLaneIn : in Pgp2fcRxPhyLaneInType; + phyRxReady : in sl; + phyRxInit : out sl + ); end Pgp2fcRx; -- Define architecture @@ -71,18 +66,18 @@ architecture Pgp2fcRx of Pgp2fcRx is signal cellRxEOFE : sl; signal cellRxData : slv(15 downto 0); signal intRxLinkReady : sl; - signal crcRxIn : slv(15 downto 0); -- Receive data for CRC - signal crcRxInit : sl; -- Receive CRC value init - signal crcRxValid : sl; -- Receive data for CRC is valid + signal crcRxIn : slv(15 downto 0); -- Receive data for CRC + signal crcRxInit : sl; -- Receive CRC value init + signal crcRxValid : sl; -- Receive data for CRC is valid signal crcRxOut : slv(31 downto 0); signal crcRxOutAdjust : slv(31 downto 0); signal crcRxRst : sl; signal crcRxInAdjust : slv(31 downto 0); signal crcRxWidthAdjust : slv(2 downto 0); - signal intPhyRxData : slv(15 downto 0); -- PHY receive data - signal intPhyRxDataK : slv(1 downto 0); -- PHY receive data is K character - signal intPhyRxDispErr : slv(1 downto 0); -- PHY receive data has disparity error - signal intPhyRxDecErr : slv(1 downto 0); -- PHY receive data not in table + signal intPhyRxData : slv(15 downto 0); -- PHY receive data + signal intPhyRxDataK : slv(1 downto 0); -- PHY receive data is K character + signal intPhyRxDispErr : slv(1 downto 0); -- PHY receive data has disparity error + signal intPhyRxDecErr : slv(1 downto 0); -- PHY receive data not in table signal intRxVcValid : slv(3 downto 0); signal intRxSof : sl; signal intRxEof : sl; @@ -90,8 +85,8 @@ architecture Pgp2fcRx of Pgp2fcRx is signal intRxData : slv(15 downto 0); signal pause : slv(3 downto 0); signal overflow : slv(3 downto 0); - signal intFcRecv : sl; - signal intFcErr : sl; + signal intFcValid : sl; + signal intFcError : sl; attribute KEEP_HIERARCHY : string; attribute KEEP_HIERARCHY of @@ -102,100 +97,97 @@ architecture Pgp2fcRx of Pgp2fcRx is begin -- Status - pgpRxOut.linkReady <= intRxLinkReady; - pgpRxOut.phyRxReady <= phyRxReady; - pgpRxOut.fcRecv <= intFcRecv; - pgpRxOut.fcRecvErr <= intFcErr; - pgpRxOut.remOverflow <= overflow; - pgpRxOut.remPause <= pause; + pgpRxOut.linkReady <= intRxLinkReady; + pgpRxOut.phyRxReady <= phyRxReady; + pgpRxOut.remOverflow <= overflow; + pgpRxOut.remPause <= pause; -- Interface connection - intPhyRxData <= phyRxLaneIn.data; - intPhyRxDataK <= phyRxLaneIn.dataK; - intPhyRxDispErr <= phyRxLaneIn.dispErr; - intPhyRxDecErr <= phyRxLaneIn.decErr; + intPhyRxData <= phyRxLaneIn.data; + intPhyRxDataK <= phyRxLaneIn.dataK; + intPhyRxDispErr <= phyRxLaneIn.dispErr; + intPhyRxDecErr <= phyRxLaneIn.decErr; - fcRecv <= intFcRecv; - fcErr <= intFcErr; -- PHY Logic - U_Pgp2fcRxPhy: entity surf.Pgp2fcRxPhy + U_Pgp2fcRxPhy : entity surf.Pgp2fcRxPhy generic map ( - TPD_G => TPD_G, - FC_WORDS_G => FC_WORDS_G - ) port map ( - pgpRxClkEn => pgpRxClkEn, - pgpRxClk => pgpRxClk, - pgpRxClkRst => pgpRxClkRst, - pgpRxLinkReady => intRxLinkReady, - pgpRxLinkDown => pgpRxOut.linkDown, - pgpRxLinkError => pgpRxOut.linkError, - fcRecv => intFcRecv, - fcWord => fcWord, - fcErr => intFcErr, - pgpRemLinkReady => pgpRxOut.remLinkReady, - pgpRemData => pgpRxOut.remLinkData, - cellRxPause => cellRxPause, - cellRxSOC => cellRxSOC, - cellRxSOF => cellRxSOF, - cellRxEOC => cellRxEOC, - cellRxEOF => cellRxEOF, - cellRxEOFE => cellRxEOFE, - cellRxData => cellRxData, - phyRxData => intPhyRxData, - phyRxDataK => intPhyRxDataK, - phyRxDispErr => intPhyRxDispErr, - phyRxDecErr => intPhyRxDecErr, - phyRxReady => phyRxReady, - phyRxInit => phyRxInit - ); + TPD_G => TPD_G, + FC_WORDS_G => FC_WORDS_G + ) port map ( + pgpRxClkEn => pgpRxClkEn, + pgpRxClk => pgpRxClk, + pgpRxClkRst => pgpRxClkRst, + pgpRxLinkReady => intRxLinkReady, + pgpRxLinkDown => pgpRxOut.linkDown, + pgpRxLinkError => pgpRxOut.linkError, + fcValid => pgpRxOut.fcValid, + fcWord => pgpRxOut.fcWord(FC_WORDS_G*16-1 downto 0), + fcError => pgpRxOut.fcError, + pgpRemLinkReady => pgpRxOut.remLinkReady, + pgpRemData => pgpRxOut.remLinkData, + cellRxPause => cellRxPause, + cellRxSOC => cellRxSOC, + cellRxSOF => cellRxSOF, + cellRxEOC => cellRxEOC, + cellRxEOF => cellRxEOF, + cellRxEOFE => cellRxEOFE, + cellRxData => cellRxData, + phyRxData => intPhyRxData, + phyRxDataK => intPhyRxDataK, + phyRxDispErr => intPhyRxDispErr, + phyRxDecErr => intPhyRxDecErr, + phyRxReady => phyRxReady, + phyRxInit => phyRxInit + ); -- Cell Receiver - U_Pgp2fcRxCell: entity surf.Pgp2fcRxCell + U_Pgp2fcRxCell : entity surf.Pgp2fcRxCell generic map ( - TPD_G => TPD_G, - EN_SHORT_CELLS_G => 1, - PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G - ) port map ( - pgpRxClkEn => pgpRxClkEn, - pgpRxClk => pgpRxClk, - pgpRxClkRst => pgpRxClkRst, - pgpRxFlush => pgpRxIn.flush, - pgpRxLinkReady => intRxLinkReady, - pgpRxCellError => pgpRxOut.cellError, - cellRxPause => cellRxPause, - cellRxSOC => cellRxSOC, - cellRxSOF => cellRxSOF, - cellRxEOC => cellRxEOC, - cellRxEOF => cellRxEOF, - cellRxEOFE => cellRxEOFE, - cellRxData => cellRxData, - vcFrameRxSOF => intRxSof, - vcFrameRxEOF => intRxEof, - vcFrameRxEOFE => intRxEofe, - vcFrameRxData => intRxData, - vc0FrameRxValid => intRxVcValid(0), - vc0RemAlmostFull => pause(0), - vc0RemOverflow => overflow(0), - vc1FrameRxValid => intRxVcValid(1), - vc1RemAlmostFull => pause(1), - vc1RemOverflow => overflow(1), - vc2FrameRxValid => intRxVcValid(2), - vc2RemAlmostFull => pause(2), - vc2RemOverflow => overflow(2), - vc3FrameRxValid => intRxVcValid(3), - vc3RemAlmostFull => pause(3), - vc3RemOverflow => overflow(3), - crcRxIn => crcRxIn, - crcRxInit => crcRxInit, - crcRxValid => crcRxValid, - crcRxOut => crcRxOutAdjust - ); + TPD_G => TPD_G, + EN_SHORT_CELLS_G => 1, + PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G + ) port map ( + pgpRxClkEn => pgpRxClkEn, + pgpRxClk => pgpRxClk, + pgpRxClkRst => pgpRxClkRst, + pgpRxFlush => pgpRxIn.flush, + pgpRxLinkReady => intRxLinkReady, + pgpRxCellError => pgpRxOut.cellError, + cellRxPause => cellRxPause, + cellRxSOC => cellRxSOC, + cellRxSOF => cellRxSOF, + cellRxEOC => cellRxEOC, + cellRxEOF => cellRxEOF, + cellRxEOFE => cellRxEOFE, + cellRxData => cellRxData, + vcFrameRxSOF => intRxSof, + vcFrameRxEOF => intRxEof, + vcFrameRxEOFE => intRxEofe, + vcFrameRxData => intRxData, + vc0FrameRxValid => intRxVcValid(0), + vc0RemAlmostFull => pause(0), + vc0RemOverflow => overflow(0), + vc1FrameRxValid => intRxVcValid(1), + vc1RemAlmostFull => pause(1), + vc1RemOverflow => overflow(1), + vc2FrameRxValid => intRxVcValid(2), + vc2RemAlmostFull => pause(2), + vc2RemOverflow => overflow(2), + vc3FrameRxValid => intRxVcValid(3), + vc3RemAlmostFull => pause(3), + vc3RemOverflow => overflow(3), + crcRxIn => crcRxIn, + crcRxInit => crcRxInit, + crcRxValid => crcRxValid, + crcRxOut => crcRxOutAdjust + ); -- Pass FIFO status - process ( overflow, pause ) begin + process (overflow, pause) + begin for i in 0 to 3 loop pgpRxOut.remOverFlow(i) <= overflow(i); remFifoStatus(i).overflow <= overflow(i); @@ -204,10 +196,10 @@ begin end process; -- Generate valid/vc - process ( pgpRxClk ) is + process (pgpRxClk) is variable intMaster : AxiStreamMasterType; begin - if rising_edge (pgpRxClk ) then + if rising_edge (pgpRxClk) then intMaster := AXI_STREAM_MASTER_INIT_C; if pgpRxClkEn = '1' then @@ -218,8 +210,8 @@ begin intMaster.tLast := intRxEof; - axiStreamSetUserBit(SSI_PGP2FC_CONFIG_C,intMaster,SSI_EOFE_C,intRxEofe); - axiStreamSetUserBit(SSI_PGP2FC_CONFIG_C,intMaster,SSI_SOF_C,intRxSof,0); + axiStreamSetUserBit(PGP2FC_AXIS_CONFIG_C, intMaster, SSI_EOFE_C, intRxEofe); + axiStreamSetUserBit(PGP2FC_AXIS_CONFIG_C, intMaster, SSI_SOF_C, intRxSof, 0); pgpRxOut.frameRx <= uOr(intRxVcValid) and intRxEof and (not intRxEofe) after TPD_G; pgpRxOut.frameRxErr <= uOr(intRxVcValid) and intRxEof and intRxEofe after TPD_G; @@ -239,18 +231,18 @@ begin intMaster.tValid := '1'; intMaster.tDest(3 downto 0) := "0011"; when others => - intMaster.tValid := '0'; + intMaster.tValid := '0'; end case; end if; if pgpRxClkRst = '1' then - intMaster := AXI_STREAM_MASTER_INIT_C; + intMaster := AXI_STREAM_MASTER_INIT_C; pgpRxOut.frameRx <= '0' after TPD_G; pgpRxOut.frameRxErr <= '0' after TPD_G; else - pgpRxMaster <= intMaster after TPD_G; + pgpRxMaster <= intMaster after TPD_G; end if; end if; @@ -276,7 +268,7 @@ begin CRCDATAWIDTH => crcRxWidthAdjust, CRCIN => crcRxInAdjust, CRCRESET => crcRxRst - ); + ); end Pgp2fcRx; diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd index 9f4b3038a9..259d88450d 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcRxPhy.vhd @@ -26,8 +26,8 @@ use surf.Pgp2fcPkg.all; entity Pgp2fcRxPhy is generic ( - TPD_G : time := 1 ns; - FC_WORDS_G : integer range 1 to 4 := 1 + TPD_G : time := 1 ns; + FC_WORDS_G : integer range 1 to 8 := 1 ); port ( @@ -44,30 +44,30 @@ entity Pgp2fcRxPhy is pgpRxLinkError : out sl := '0'; -- A link error has occured -- Fast control interface - fcRecv : out sl := '0'; - fcWord : out slv(16*FC_WORDS_G-1 downto 0); - fcErr : out sl := '0'; + fcValid : out sl := '0'; + fcWord : out slv(16*FC_WORDS_G-1 downto 0); + fcError : out sl := '0'; -- Sideband data pgpRemLinkReady : out sl := '0'; -- Far end side has link pgpRemData : out slv(7 downto 0) := (others => '0'); -- Far end side User Data -- Cell Receive Interface - cellRxPause : out sl; -- Cell data pause - cellRxSOC : out sl; -- Cell data start of cell - cellRxSOF : out sl; -- Cell data start of frame - cellRxEOC : out sl; -- Cell data end of cell - cellRxEOF : out sl; -- Cell data end of frame - cellRxEOFE : out sl; -- Cell data end of frame error - cellRxData : out slv(15 downto 0); -- Cell data data + cellRxPause : out sl; -- Cell data pause + cellRxSOC : out sl; -- Cell data start of cell + cellRxSOF : out sl; -- Cell data start of frame + cellRxEOC : out sl; -- Cell data end of cell + cellRxEOF : out sl; -- Cell data end of frame + cellRxEOFE : out sl; -- Cell data end of frame error + cellRxData : out slv(15 downto 0); -- Cell data data -- Physical Interface Signals - phyRxData : in slv(15 downto 0); -- PHY receive data - phyRxDataK : in slv(1 downto 0); -- PHY receive data is K character - phyRxDispErr : in slv(1 downto 0); -- PHY receive data has disparity error - phyRxDecErr : in slv(1 downto 0); -- PHY receive data not in table - phyRxReady : in sl; -- PHY receive interface is ready - phyRxInit : out sl -- PHY receive interface init; + phyRxData : in slv(15 downto 0); -- PHY receive data + phyRxDataK : in slv(1 downto 0); -- PHY receive data is K character + phyRxDispErr : in slv(1 downto 0); -- PHY receive data has disparity error + phyRxDecErr : in slv(1 downto 0); -- PHY receive data not in table + phyRxReady : in sl; -- PHY receive interface is ready + phyRxInit : out sl -- PHY receive interface init; ); end Pgp2fcRxPhy; @@ -85,47 +85,47 @@ architecture Pgp2fcRxPhy of Pgp2fcRxPhy is signal dly1RxDataK : slv(1 downto 0) := (others => '0'); signal dly1RxDispErr : slv(1 downto 0) := (others => '0'); signal dly1RxDecErr : slv(1 downto 0) := (others => '0'); - signal rxDetectLts : sl := '0'; - signal rxDetectLtsOk : sl := '0'; + signal rxDetectLts : sl := '0'; + signal rxDetectLtsOk : sl := '0'; signal rxDetectLtsRaw : sl; - signal rxDetectInvert : sl := '0'; + signal rxDetectInvert : sl := '0'; signal rxDetectInvertRaw : sl; - signal rxDetectRemLink : sl := '0'; - signal rxDetectRemData : slv(7 downto 0) := (others => '0'); + signal rxDetectRemLink : sl := '0'; + signal rxDetectRemData : slv(7 downto 0) := (others => '0'); signal rxDetectFcWordEnRaw : sl; - signal rxDetectSOC : sl := '0'; + signal rxDetectSOC : sl := '0'; signal rxDetectSOCRaw : sl; - signal rxDetectSOF : sl := '0'; + signal rxDetectSOF : sl := '0'; signal rxDetectSOFRaw : sl; - signal rxDetectEOC : sl := '0'; + signal rxDetectEOC : sl := '0'; signal rxDetectEOCRaw : sl; - signal rxDetectEOF : sl := '0'; + signal rxDetectEOF : sl := '0'; signal rxDetectEOFRaw : sl; - signal rxDetectEOFE : sl := '0'; + signal rxDetectEOFE : sl := '0'; signal rxDetectEOFERaw : sl; signal nxtRxLinkReady : sl; signal stateCntRst : sl; - signal stateCnt : slv(19 downto 0) := (others => '0'); + signal stateCnt : slv(19 downto 0) := (others => '0'); signal ltsCntRst : sl; signal ltsCntEn : sl; - signal ltsCnt : slv(7 downto 0) := (others => '0'); - signal intRxLinkReady : sl := '0'; - signal dlyRxLinkDown : sl := '0'; - signal intRxLinkError : sl := '0'; - signal dlyRxLinkError : sl := '0'; - signal intRxInit : sl := '0'; + signal ltsCnt : slv(7 downto 0) := (others => '0'); + signal intRxLinkReady : sl := '0'; + signal dlyRxLinkDown : sl := '0'; + signal intRxLinkError : sl := '0'; + signal dlyRxLinkError : sl := '0'; + signal intRxInit : sl := '0'; signal nxtRxInit : sl; - signal intFcRecv : sl := '0'; - signal intFcBusy : sl := '0'; - signal intFcErr : sl := '0'; - signal fcWordCounter : integer range 0 to FC_WORDS_G := 0; - signal fcWordBuffer : slv(16*FC_WORDS_G-1 downto 0) := (others => '0'); + signal intFcValid : sl := '0'; + signal intFcBusy : sl := '0'; + signal intFcError : sl := '0'; + signal fcWordCounter : integer range 0 to FC_WORDS_G := 0; + signal fcWordBuffer : slv(16*FC_WORDS_G-1 downto 0) := (others => '0'); - signal crcRst : sl; - signal crcEn : sl; - signal crcDataIn : slv(15 downto 0); - signal crcOut : slv(7 downto 0); + signal crcRst : sl; + signal crcEn : sl; + signal crcDataIn : slv(15 downto 0); + signal crcOut : slv(7 downto 0); -- Physical Link State type FSM_STATE is ( @@ -134,9 +134,9 @@ architecture Pgp2fcRxPhy of Pgp2fcRxPhy is ST_WAIT_C, ST_INVRT_C, ST_READY_C - ); - signal curState : FSM_STATE := ST_LOCK_C; - signal nxtState : FSM_STATE; + ); + signal curState : FSM_STATE := ST_LOCK_C; + signal nxtState : FSM_STATE; begin @@ -147,9 +147,9 @@ begin phyRxInit <= intRxInit; -- Fast Control Receiver Interface - fcRecv <= intFcRecv; - fcWord <= fcWordBuffer when intFcRecv = '1' else (others => '0'); -- Zeroing can be removed to improve routing if required - fcErr <= intFcErr; + fcValid <= intFcValid; + fcWord <= fcWordBuffer when intFcValid = '1' else (others => '0'); -- Zeroing can be removed to improve routing if required + fcError <= intFcError; -- Cell Receive Interface cellRxPause <= intFcBusy; @@ -280,17 +280,17 @@ begin -- Lock is lost if phyRxReady = '0' then - stateCntRst <= '1'; - ltsCntEn <= '0'; - ltsCntRst <= '0'; - nxtState <= ST_RESET_C; + stateCntRst <= '1'; + ltsCntEn <= '0'; + ltsCntRst <= '0'; + nxtState <= ST_RESET_C; -- Decode or disparity error, clear lts count elsif phyRxReady = '0' or dly1RxDispErr /= 0 or dly1RxDecErr /= 0 then - stateCntRst <= '0'; - ltsCntEn <= '0'; - ltsCntRst <= '1'; - nxtState <= curState; + stateCntRst <= '0'; + ltsCntEn <= '0'; + ltsCntRst <= '1'; + nxtState <= curState; -- Training pattern seen elsif rxDetectLts = '1' then @@ -298,7 +298,7 @@ begin -- No Inversion if rxDetectInvert = '0' then - nxtState <= curState; + nxtState <= curState; -- ID & Lane Count Ok if rxDetectLtsOk = '1' then @@ -311,32 +311,32 @@ begin -- Inverted else - ltsCntEn <= '0'; - ltsCntRst <= '1'; - nxtState <= ST_INVRT_C; + ltsCntEn <= '0'; + ltsCntRst <= '1'; + nxtState <= ST_INVRT_C; end if; -- Run after we have seen 256 non-inverted training sequences -- without any disparity or decode errors. elsif ltsCnt = 255 then - stateCntRst <= '1'; - ltsCntEn <= '0'; - ltsCntRst <= '1'; - nxtState <= ST_READY_C; + stateCntRst <= '1'; + ltsCntEn <= '0'; + ltsCntRst <= '1'; + nxtState <= ST_READY_C; -- Terminal count without seeing a valid LTS elsif stateCnt = x"FFFFF" then - stateCntRst <= '1'; - ltsCntEn <= '0'; - ltsCntRst <= '1'; - nxtState <= ST_RESET_C; + stateCntRst <= '1'; + ltsCntEn <= '0'; + ltsCntRst <= '1'; + nxtState <= ST_RESET_C; -- Count cycles without LTS else - stateCntRst <= '0'; - ltsCntEn <= '0'; - ltsCntRst <= '0'; - nxtState <= curState; + stateCntRst <= '0'; + ltsCntEn <= '0'; + ltsCntRst <= '0'; + nxtState <= curState; end if; -- Wait a few clocks after inverting receive interface @@ -436,20 +436,21 @@ begin end process; -- Fast Control logic - process (pgpRxClk, pgpRxClkRst) begin + process (pgpRxClk, pgpRxClkRst) + begin if pgpRxClkRst = '1' then - intFcRecv <= '0' after TPD_G; + intFcValid <= '0' after TPD_G; intFcBusy <= '0' after TPD_G; - intFcErr <= '0' after TPD_G; + intFcError <= '0' after TPD_G; fcWordCounter <= 0 after TPD_G; fcWordBuffer <= (others => '0') after TPD_G; elsif rising_edge(pgpRxClk) then -- Defaults - intFcRecv <= '0'; - intFcBusy <= '0'; - intFcErr <= '0'; + intFcValid <= '0'; + intFcBusy <= '0'; + intFcError <= '0'; fcWordCounter <= 0; - fcWordBuffer <= fcWordBuffer; + fcWordBuffer <= fcWordBuffer; if rxDetectFcWordEnRaw = '1' or fcWordCounter /= 0 then if fcWordCounter = FC_WORDS_G then @@ -467,9 +468,9 @@ begin -- Check CRC too if (crcOut = dly0RxData(15 downto 8)) then - intFcRecv <= '1'; + intFcValid <= '1'; else - intFcErr <= '1'; + intFcError <= '1'; end if; else fcWordBuffer(fcWordCounter*16+7 downto (fcWordCounter-1)*16+8) <= dly0RxData; @@ -477,33 +478,33 @@ begin end if; end process; - crcRst <= '1' when fcWordCounter = FC_WORDS_G else '0'; - crcEn <= '1' when rxDetectFcWordEnRaw = '1' or fcWordCounter /= 0 else '0'; - crcDataIn <= dly0RxData when fcWordCounter /= FC_WORDS_G else x"00" & dly0RxData(7 downto 0); + crcRst <= '1' when fcWordCounter = FC_WORDS_G else '0'; + crcEn <= '1' when rxDetectFcWordEnRaw = '1' or fcWordCounter /= 0 else '0'; + crcDataIn <= dly0RxData when fcWordCounter /= FC_WORDS_G else x"00" & dly0RxData(7 downto 0); U_Crc7 : entity surf.CRC7Rtl - port map ( - rst => crcRst, - clk => pgpRxClk, - data_in => crcDataIn, - crc_en => crcEn, - crc_out => crcOut - ); + port map ( + rst => crcRst, + clk => pgpRxClk, + data_in => crcDataIn, + crc_en => crcEn, + crc_out => crcOut + ); -- Link init ordered set detect process (pgpRxClk, pgpRxClkRst) begin if pgpRxClkRst = '1' then - rxDetectLts <= '0' after TPD_G; - rxDetectLtsOk <= '0' after TPD_G; - rxDetectInvert <= '0' after TPD_G; - rxDetectRemLink <= '0' after TPD_G; - rxDetectRemData <= (others => '0') after TPD_G; - rxDetectSOC <= '0' after TPD_G; - rxDetectSOF <= '0' after TPD_G; - rxDetectEOC <= '0' after TPD_G; - rxDetectEOF <= '0' after TPD_G; - rxDetectEOFE <= '0' after TPD_G; + rxDetectLts <= '0' after TPD_G; + rxDetectLtsOk <= '0' after TPD_G; + rxDetectInvert <= '0' after TPD_G; + rxDetectRemLink <= '0' after TPD_G; + rxDetectRemData <= (others => '0') after TPD_G; + rxDetectSOC <= '0' after TPD_G; + rxDetectSOF <= '0' after TPD_G; + rxDetectEOC <= '0' after TPD_G; + rxDetectEOF <= '0' after TPD_G; + rxDetectEOFE <= '0' after TPD_G; elsif rising_edge(pgpRxClk) then if pgpRxClkEn = '1' then -- LTS is detected when phy is ready @@ -515,7 +516,7 @@ begin rxDetectLts <= '1' after TPD_G; -- Fast control word count and ID must match - if dly0RxData(14 downto 12) = conv_std_logic_vector(FC_WORDS_G-1,3) and + if dly0RxData(14 downto 12) = conv_std_logic_vector(FC_WORDS_G-1, 3) and dly0RxData(11 downto 8) = PGP2FC_ID_C then rxDetectLtsOk <= '1' after TPD_G; rxDetectRemLink <= dly0RxData(15) after TPD_G; @@ -576,11 +577,11 @@ begin end if; else -- rxDetectOpCodeEn <= '0' after TPD_G; - rxDetectSOC <= '0' after TPD_G; - rxDetectSOF <= '0' after TPD_G; - rxDetectEOC <= '0' after TPD_G; - rxDetectEOF <= '0' after TPD_G; - rxDetectEOFE <= '0' after TPD_G; + rxDetectSOC <= '0' after TPD_G; + rxDetectSOF <= '0' after TPD_G; + rxDetectEOC <= '0' after TPD_G; + rxDetectEOF <= '0' after TPD_G; + rxDetectEOFE <= '0' after TPD_G; end if; end if; end if; diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd index 2da156f8e5..8a3d47a04b 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTx.vhd @@ -15,7 +15,7 @@ -- the terms contained in the LICENSE.txt file. ------------------------------------------------------------------------------- -LIBRARY ieee; +library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; @@ -29,37 +29,33 @@ use surf.SsiPkg.all; entity Pgp2fcTx is generic ( TPD_G : time := 1 ns; - FC_WORDS_G : integer range 1 to 4 := 1; - VC_INTERLEAVE_G : integer := 1; -- Interleave Frames - PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter + FC_WORDS_G : integer range 1 to 8 := 1; + VC_INTERLEAVE_G : integer := 1; -- Interleave Frames + PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter NUM_VC_EN_G : integer range 1 to 4 := 4 - ); + ); port ( -- System clock, reset & control - pgpTxClkEn : in sl := '1';-- Master clock enable - pgpTxClk : in sl; -- Master clock - pgpTxClkRst : in sl; -- Synchronous reset input - - -- Fast control interface - fcSend : in sl := '0'; - fcWord : in slv(16*FC_WORDS_G-1 downto 0) := (others => '0'); + pgpTxClkEn : in sl := '1'; -- Master clock enable + pgpTxClk : in sl; -- Master clock + pgpTxClkRst : in sl; -- Synchronous reset input -- Non-VC related IO - pgpTxIn : in Pgp2fcTxCtrlInType; - pgpTxOut : out Pgp2fcTxStatusOutType; - locLinkReady : in sl; + pgpTxIn : in Pgp2fcTxInType; + pgpTxOut : out Pgp2fcTxOutType; + locLinkReady : in sl; -- VC Interface - pgpTxMasters : in AxiStreamMasterArray(3 downto 0); - pgpTxSlaves : out AxiStreamSlaveArray(3 downto 0); - locFifoStatus : in AxiStreamCtrlArray(3 downto 0); - remFifoStatus : in AxiStreamCtrlArray(3 downto 0); + pgpTxMasters : in AxiStreamMasterArray(3 downto 0); + pgpTxSlaves : out AxiStreamSlaveArray(3 downto 0); + locFifoStatus : in AxiStreamCtrlArray(3 downto 0); + remFifoStatus : in AxiStreamCtrlArray(3 downto 0); -- Phy interface - phyTxLaneOut : out Pgp2fcTxPhyLaneOutType; - phyTxReady : in sl - ); + phyTxLaneOut : out Pgp2fcTxPhyLaneOutType; + phyTxReady : in sl + ); end Pgp2fcTx; @@ -84,12 +80,12 @@ architecture Pgp2fcTx of Pgp2fcTx is signal intTxBusy : sl; signal schTxTimeout : sl; signal intPhyTxData : slv(15 downto 0); - signal intPhyTxDataK : slv(1 downto 0); - signal crcTxIn : slv(15 downto 0); -- Transmit data for CRC - signal crcTxInit : sl; -- Transmit CRC value init - signal crcTxValid : sl; -- Transmit data for CRC is valid - signal crcTxOut : slv(31 downto 0); -- Transmit calculated CRC value - signal crcTxOutAdjust : slv(31 downto 0); -- Transmit calculated CRC value + signal intPhyTxDataK : slv(1 downto 0); + signal crcTxIn : slv(15 downto 0); -- Transmit data for CRC + signal crcTxInit : sl; -- Transmit CRC value init + signal crcTxValid : sl; -- Transmit data for CRC is valid + signal crcTxOut : slv(31 downto 0); -- Transmit calculated CRC value + signal crcTxOutAdjust : slv(31 downto 0); -- Transmit calculated CRC value signal crcTxRst : sl; signal crcTxInAdjust : slv(31 downto 0); signal crcTxWidthAdjust : slv(2 downto 0); @@ -116,8 +112,8 @@ architecture Pgp2fcTx of Pgp2fcTx is begin -- Sync flow control & buffer status - U_VcFlowGen: for i in 0 to 3 generate - U_Sync: entity surf.SynchronizerVector + U_VcFlowGen : for i in 0 to 3 generate + U_Sync : entity surf.SynchronizerVector generic map ( TPD_G => TPD_G, RST_POLARITY_G => '1', @@ -125,8 +121,8 @@ begin RST_ASYNC_G => false, STAGES_G => 2, WIDTH_G => 3, - INIT_G => "0" - ) port map ( + INIT_G => "0") + port map ( clk => pgpTxClk, rst => pgpTxClkRst, dataIn(0) => locFifoStatus(i).pause, @@ -134,29 +130,27 @@ begin dataIn(2) => remFifoStatus(i).pause, dataOut(0) => syncLocPause(i), dataOut(1) => syncLocOverFlow(i), - dataOut(2) => syncRemPause(i) - ); + dataOut(2) => syncRemPause(i)); end generate; - U_LinkReady: entity surf.Synchronizer + U_LinkReady : entity surf.Synchronizer generic map ( TPD_G => TPD_G, RST_POLARITY_G => '1', OUT_POLARITY_G => '1', RST_ASYNC_G => false, STAGES_G => 2, - INIT_G => "0" - ) port map ( - clk => pgpTxClk, - rst => pgpTxClkRst, - dataIn => locLinkReady, - dataOut => syncLocLinkReady - ); + INIT_G => "0") + port map ( + clk => pgpTxClk, + rst => pgpTxClkRst, + dataIn => locLinkReady, + dataOut => syncLocLinkReady); -- Set phy lanes - phyTxLaneOut.data <= intPhyTxData; - phyTxLaneOut.dataK <= intPhyTxDataK; + phyTxLaneOut.data <= intPhyTxData; + phyTxLaneOut.dataK <= intPhyTxDataK; -- Link Ready pgpTxOut.linkReady <= intTxLinkReady; @@ -165,18 +159,19 @@ begin pgpTxOut.locOverflow <= syncLocOverFlow; pgpTxOut.locPause <= syncLocPause; - process ( pgpTxClk ) begin + process (pgpTxClk) + begin if rising_edge(pgpTxClk) then if pgpTxClkRst = '1' then - pgpTxOut.frameTx <= '0' after TPD_G; - pgpTxOut.frameTxErr <= '0' after TPD_G; - gateRemPause <= (others=>'0') after TPD_G; + pgpTxOut.frameTx <= '0' after TPD_G; + pgpTxOut.frameTxErr <= '0' after TPD_G; + gateRemPause <= (others => '0') after TPD_G; else pgpTxOut.frameTx <= cellTxEOF after TPD_G; pgpTxOut.frameTxErr <= cellTxEOFE after TPD_G; if pgpTxIn.flowCntlDis = '1' then - gateRemPause <= (others=>'0') after TPD_G; + gateRemPause <= (others => '0') after TPD_G; else gateRemPause <= syncRemPause after TPD_G; end if; @@ -185,150 +180,147 @@ begin end process; -- Physical Interface - U_Pgp2fcTxPhy: entity surf.Pgp2fcTxPhy + U_Pgp2fcTxPhy : entity surf.Pgp2fcTxPhy generic map ( - TPD_G => TPD_G, - FC_WORDS_G => FC_WORDS_G - ) port map ( - pgpTxClkEn => pgpTxClkEn, - pgpTxClk => pgpTxClk, - pgpTxClkRst => pgpTxClkRst, - pgpTxLinkReady => intTxLinkReady, - pgpBusy => intTxBusy, - fcSend => fcSend, - fcWord => fcWord, - fcSent => intFcSent, - pgpLocLinkReady => syncLocLinkReady, - pgpLocData => pgpTxIn.locData, - cellTxSOC => cellTxSOC, - cellTxSOF => cellTxSOF, - cellTxEOC => cellTxEOC, - cellTxEOF => cellTxEOF, - cellTxEOFE => cellTxEOFE, - cellTxData => cellTxData, - phyTxData => intPhyTxData, - phyTxDataK => intPhyTxDataK, - phyTxReady => phyTxReady - ); + TPD_G => TPD_G, + FC_WORDS_G => FC_WORDS_G) + port map ( + pgpTxClkEn => pgpTxClkEn, + pgpTxClk => pgpTxClk, + pgpTxClkRst => pgpTxClkRst, + pgpTxLinkReady => intTxLinkReady, + pgpBusy => intTxBusy, + fcValid => pgpTxIn.fcValid, + fcWord => pgpTxIn.fcWord(FC_WORDS_G*16-1 downto 0), + fcSent => intFcSent, + pgpLocLinkReady => syncLocLinkReady, + pgpLocData => pgpTxIn.locData, + cellTxSOC => cellTxSOC, + cellTxSOF => cellTxSOF, + cellTxEOC => cellTxEOC, + cellTxEOF => cellTxEOF, + cellTxEOFE => cellTxEOFE, + cellTxData => cellTxData, + phyTxData => intPhyTxData, + phyTxDataK => intPhyTxDataK, + phyTxReady => phyTxReady); -- Scheduler - U_Pgp2fcTxSched: entity surf.Pgp2fcTxSched + U_Pgp2fcTxSched : entity surf.Pgp2fcTxSched generic map ( - TPD_G => TPD_G, - VC_INTERLEAVE_G => VC_INTERLEAVE_G, - NUM_VC_EN_G => NUM_VC_EN_G - ) port map ( - pgpTxClkEn => pgpTxClkEn, - pgpTxClk => pgpTxClk, - pgpTxClkRst => pgpTxClkRst, - pgpTxFlush => pgpTxIn.flush, - pgpTxLinkReady => intTxLinkReady, - pgpTxBusy => intTxBusy, - schTxSOF => schTxSOF, - schTxEOF => schTxEOF, - schTxIdle => schTxIdle, - schTxReq => schTxReq, - schTxAck => schTxAck, - schTxDataVc => schTxDataVc, - schTxTimeout => schTxTimeout, - vc0FrameTxValid => intValid(0), - vc1FrameTxValid => intValid(1), - vc2FrameTxValid => intValid(2), - vc3FrameTxValid => intValid(3), - vc0RemAlmostFull => gateRemPause(0), - vc1RemAlmostFull => gateRemPause(1), - vc2RemAlmostFull => gateRemPause(2), - vc3RemAlmostFull => gateRemPause(3) - ); + TPD_G => TPD_G, + VC_INTERLEAVE_G => VC_INTERLEAVE_G, + NUM_VC_EN_G => NUM_VC_EN_G) + port map ( + pgpTxClkEn => pgpTxClkEn, + pgpTxClk => pgpTxClk, + pgpTxClkRst => pgpTxClkRst, + pgpTxFlush => pgpTxIn.flush, + pgpTxLinkReady => intTxLinkReady, + pgpTxBusy => intTxBusy, + schTxSOF => schTxSOF, + schTxEOF => schTxEOF, + schTxIdle => schTxIdle, + schTxReq => schTxReq, + schTxAck => schTxAck, + schTxDataVc => schTxDataVc, + schTxTimeout => schTxTimeout, + vc0FrameTxValid => intValid(0), + vc1FrameTxValid => intValid(1), + vc2FrameTxValid => intValid(2), + vc3FrameTxValid => intValid(3), + vc0RemAlmostFull => gateRemPause(0), + vc1RemAlmostFull => gateRemPause(1), + vc2RemAlmostFull => gateRemPause(2), + vc3RemAlmostFull => gateRemPause(3)); -- Cell Transmitter - U_Pgp2fcTxCell: entity surf.Pgp2fcTxCell + U_Pgp2fcTxCell : entity surf.Pgp2fcTxCell generic map ( - TPD_G => TPD_G - ) port map ( - pgpTxClkEn => pgpTxClkEn, - pgpTxClk => pgpTxClk, - pgpTxClkRst => pgpTxClkRst, - pgpTxLinkReady => intTxLinkReady, - pgpTxBusy => intTxBusy, - cellTxSOC => cellTxSOC, - cellTxSOF => cellTxSOF, - cellTxEOC => cellTxEOC, - cellTxEOF => cellTxEOF, - cellTxEOFE => cellTxEOFE, - cellTxData => cellTxData, - schTxSOF => schTxSOF, - schTxEOF => schTxEOF, - schTxIdle => schTxIdle, - schTxReq => schTxReq, - schTxAck => schTxAck, - schTxTimeout => schTxTimeout, - schTxDataVc => schTxDataVc, - vc0FrameTxValid => intValid(0), - vc0FrameTxReady => rawReady(0), - vc0FrameTxSOF => intTxSof(0), - vc0FrameTxEOF => intTxMasters(0).tLast, - vc0FrameTxEOFE => intTxEofe(0), - vc0FrameTxData => intTxMasters(0).tData(15 downto 0), - vc0LocAlmostFull => syncLocPause(0), - vc0LocOverflow => syncLocOverFlow(0), - vc0RemAlmostFull => gateRemPause(0), - vc1FrameTxValid => intValid(1), - vc1FrameTxReady => rawReady(1), - vc1FrameTxSOF => intTxSof(1), - vc1FrameTxEOF => intTxMasters(1).tLast, - vc1FrameTxEOFE => intTxEofe(1), - vc1FrameTxData => intTxMasters(1).tData(15 downto 0), - vc1LocAlmostFull => syncLocPause(1), - vc1LocOverflow => syncLocOverFlow(1), - vc1RemAlmostFull => gateRemPause(1), - vc2FrameTxValid => intValid(2), - vc2FrameTxReady => rawReady(2), - vc2FrameTxSOF => intTxSof(2), - vc2FrameTxEOF => intTxMasters(2).tLast, - vc2FrameTxEOFE => intTxEofe(2), - vc2FrameTxData => intTxMasters(2).tData(15 downto 0), - vc2LocAlmostFull => syncLocPause(2), - vc2LocOverflow => syncLocOverFlow(2), - vc2RemAlmostFull => gateRemPause(2), - vc3FrameTxValid => intValid(3), - vc3FrameTxReady => rawReady(3), - vc3FrameTxSOF => intTxSof(3), - vc3FrameTxEOF => intTxMasters(3).tLast, - vc3FrameTxEOFE => intTxEofe(3), - vc3FrameTxData => intTxMasters(3).tData(15 downto 0), - vc3LocAlmostFull => syncLocPause(3), - vc3LocOverflow => syncLocOverFlow(3), - vc3RemAlmostFull => gateRemPause(3), - crcTxIn => crcTxIn, - crcTxInit => crcTxInit, - crcTxValid => crcTxValid, - crcTxOut => crcTxOutAdjust - ); + TPD_G => TPD_G) + port map ( + pgpTxClkEn => pgpTxClkEn, + pgpTxClk => pgpTxClk, + pgpTxClkRst => pgpTxClkRst, + pgpTxLinkReady => intTxLinkReady, + pgpTxBusy => intTxBusy, + cellTxSOC => cellTxSOC, + cellTxSOF => cellTxSOF, + cellTxEOC => cellTxEOC, + cellTxEOF => cellTxEOF, + cellTxEOFE => cellTxEOFE, + cellTxData => cellTxData, + schTxSOF => schTxSOF, + schTxEOF => schTxEOF, + schTxIdle => schTxIdle, + schTxReq => schTxReq, + schTxAck => schTxAck, + schTxTimeout => schTxTimeout, + schTxDataVc => schTxDataVc, + vc0FrameTxValid => intValid(0), + vc0FrameTxReady => rawReady(0), + vc0FrameTxSOF => intTxSof(0), + vc0FrameTxEOF => intTxMasters(0).tLast, + vc0FrameTxEOFE => intTxEofe(0), + vc0FrameTxData => intTxMasters(0).tData(15 downto 0), + vc0LocAlmostFull => syncLocPause(0), + vc0LocOverflow => syncLocOverFlow(0), + vc0RemAlmostFull => gateRemPause(0), + vc1FrameTxValid => intValid(1), + vc1FrameTxReady => rawReady(1), + vc1FrameTxSOF => intTxSof(1), + vc1FrameTxEOF => intTxMasters(1).tLast, + vc1FrameTxEOFE => intTxEofe(1), + vc1FrameTxData => intTxMasters(1).tData(15 downto 0), + vc1LocAlmostFull => syncLocPause(1), + vc1LocOverflow => syncLocOverFlow(1), + vc1RemAlmostFull => gateRemPause(1), + vc2FrameTxValid => intValid(2), + vc2FrameTxReady => rawReady(2), + vc2FrameTxSOF => intTxSof(2), + vc2FrameTxEOF => intTxMasters(2).tLast, + vc2FrameTxEOFE => intTxEofe(2), + vc2FrameTxData => intTxMasters(2).tData(15 downto 0), + vc2LocAlmostFull => syncLocPause(2), + vc2LocOverflow => syncLocOverFlow(2), + vc2RemAlmostFull => gateRemPause(2), + vc3FrameTxValid => intValid(3), + vc3FrameTxReady => rawReady(3), + vc3FrameTxSOF => intTxSof(3), + vc3FrameTxEOF => intTxMasters(3).tLast, + vc3FrameTxEOFE => intTxEofe(3), + vc3FrameTxData => intTxMasters(3).tData(15 downto 0), + vc3LocAlmostFull => syncLocPause(3), + vc3LocOverflow => syncLocOverFlow(3), + vc3RemAlmostFull => gateRemPause(3), + crcTxIn => crcTxIn, + crcTxInit => crcTxInit, + crcTxValid => crcTxValid, + crcTxOut => crcTxOutAdjust); -- EOFE/Ready/Valid - U_Vc_Gen: for i in 0 to 3 generate + U_Vc_Gen : for i in 0 to 3 generate -- Add pipeline stages to ensure ready stays asserted - U_InputPipe: entity surf.AxiStreamPipeline + U_InputPipe : entity surf.AxiStreamPipeline generic map ( TPD_G => TPD_G, - PIPE_STAGES_G => 0 - ) port map ( + PIPE_STAGES_G => 0) + port map ( axisClk => pgpTxClk, axisRst => pgpTxClkRst, sAxisMaster => pgpTxMasters(i), sAxisSlave => pgpTxSlaves(i), mAxisMaster => intTxMasters(i), mAxisSlave => intTxSlaves(i) - ); + ); intValid(i) <= intTxMasters(i).tValid; - intTxEofe(i) <= axiStreamGetUserBit(SSI_PGP2FC_CONFIG_C,intTxMasters(i),SSI_EOFE_C); - intTxSof(i) <= axiStreamGetUserBit(SSI_PGP2FC_CONFIG_C,intTxMasters(i),SSI_SOF_C,0); + intTxEofe(i) <= axiStreamGetUserBit(PGP2FC_AXIS_CONFIG_C, intTxMasters(i), SSI_EOFE_C); + intTxSof(i) <= axiStreamGetUserBit(PGP2FC_AXIS_CONFIG_C, intTxMasters(i), SSI_SOF_C, 0); intTxSlaves(i).tReady <= rawReady(i); end generate; @@ -352,7 +344,7 @@ begin CRCDATAWIDTH => crcTxWidthAdjust, CRCIN => crcTxInAdjust, CRCRESET => crcTxRst - ); + ); end Pgp2fcTx; diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd index eeced76eab..26d1706f3e 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxCell.vhd @@ -117,48 +117,48 @@ end Pgp2fcTxCell; architecture Pgp2fcTxCell of Pgp2fcTxCell is -- Local Signals - signal muxFrameTxValid : sl; - signal muxFrameTxSOF : sl; - signal muxFrameTxEOF : sl; - signal muxFrameTxEOFE : sl; - signal muxFrameTxData : slv(15 downto 0); - signal muxRemAlmostFull : sl; - signal cellCnt : slv(PAYLOAD_CNT_TOP_G downto 0); - signal cellCntRst : sl; - signal nxtFrameTxReady : sl; - signal nxtType : slv(2 downto 0); - signal nxtTypeLast : slv(2 downto 0); - signal curTypeLast : slv(2 downto 0); - signal nxtTxSOF : sl; - signal nxtTxEOF : sl; - signal nxtTxAck : sl; - signal nxtData : slv(15 downto 0); - signal eocWord : slv(15 downto 0); - signal socWord : slv(15 downto 0); - signal crcWordA : slv(15 downto 0); - signal crcWordB : slv(15 downto 0); - signal serialCntEn : sl; - signal vc0Serial : slv(5 downto 0); - signal vc1Serial : slv(5 downto 0); - signal vc2Serial : slv(5 downto 0); - signal vc3Serial : slv(5 downto 0); - signal muxSerial : slv(5 downto 0); - signal dly0Data : slv(15 downto 0); - signal dly0Type : slv(2 downto 0); - signal dly1Data : slv(15 downto 0); - signal dly1Type : slv(2 downto 0); - signal dly2Data : slv(15 downto 0); - signal dly2Type : slv(2 downto 0); - signal dly3Data : slv(15 downto 0); - signal dly3Type : slv(2 downto 0); - signal dly4Data : slv(15 downto 0); - signal dly4Type : slv(2 downto 0); - signal int0FrameTxReady : sl; - signal int1FrameTxReady : sl; - signal int2FrameTxReady : sl; - signal int3FrameTxReady : sl; - signal intTimeout : sl; - signal intOverflow : slv(3 downto 0); + signal muxFrameTxValid : sl; + signal muxFrameTxSOF : sl; + signal muxFrameTxEOF : sl; + signal muxFrameTxEOFE : sl; + signal muxFrameTxData : slv(15 downto 0); + signal muxRemAlmostFull : sl; + signal cellCnt : slv(PAYLOAD_CNT_TOP_G downto 0); + signal cellCntRst : sl; + signal nxtFrameTxReady : sl; + signal nxtType : slv(2 downto 0); + signal nxtTypeLast : slv(2 downto 0); + signal curTypeLast : slv(2 downto 0); + signal nxtTxSOF : sl; + signal nxtTxEOF : sl; + signal nxtTxAck : sl; + signal nxtData : slv(15 downto 0); + signal eocWord : slv(15 downto 0); + signal socWord : slv(15 downto 0); + signal crcWordA : slv(15 downto 0); + signal crcWordB : slv(15 downto 0); + signal serialCntEn : sl; + signal vc0Serial : slv(5 downto 0); + signal vc1Serial : slv(5 downto 0); + signal vc2Serial : slv(5 downto 0); + signal vc3Serial : slv(5 downto 0); + signal muxSerial : slv(5 downto 0); + signal dly0Data : slv(15 downto 0) := (others => '0'); + signal dly0Type : slv(2 downto 0) := (others => '0'); + signal dly1Data : slv(15 downto 0) := (others => '0'); + signal dly1Type : slv(2 downto 0) := (others => '0'); + signal dly2Data : slv(15 downto 0) := (others => '0'); + signal dly2Type : slv(2 downto 0) := (others => '0'); + signal dly3Data : slv(15 downto 0) := (others => '0'); + signal dly3Type : slv(2 downto 0) := (others => '0'); + signal dly4Data : slv(15 downto 0) := (others => '0'); + signal dly4Type : slv(2 downto 0) := (others => '0'); + signal int0FrameTxReady : sl := '0'; + signal int1FrameTxReady : sl := '0'; + signal int2FrameTxReady : sl := '0'; + signal int3FrameTxReady : sl := '0'; + signal intTimeout : sl := '0'; + signal intOverflow : slv(3 downto 0) := (others => '0'); -- Transmit Data Marker constant TX_DATA_C : slv(2 downto 0) := "000"; diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd index 2f4c61f649..8f78be9319 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxPhy.vhd @@ -17,7 +17,7 @@ -- the terms contained in the LICENSE.txt file. ------------------------------------------------------------------------------- -LIBRARY ieee; +library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; @@ -28,44 +28,44 @@ use surf.Pgp2fcPkg.all; entity Pgp2fcTxPhy is generic ( - TPD_G : time := 1 ns; - FC_WORDS_G : integer range 1 to 4 := 1 -- Number of 16-bit words for fast control, max is packet size minus 1 - ); + TPD_G : time := 1 ns; + FC_WORDS_G : integer range 1 to 8 := 1 -- Number of 16-bit words for fast control, max is packet size minus 1 + ); port ( -- System clock, reset & control - pgpTxClkEn : in sl := '1'; -- Master clock Enable - pgpTxClk : in sl; -- Master clock - pgpTxClkRst : in sl; -- Synchronous reset input + pgpTxClkEn : in sl := '1'; -- Master clock Enable + pgpTxClk : in sl; -- Master clock + pgpTxClkRst : in sl; -- Synchronous reset input -- Link is ready - pgpTxLinkReady : out sl; -- Local side has link + pgpTxLinkReady : out sl; -- Local side has link -- Phy is busy - pgpBusy : out sl; -- Pause incoming PGP datastream + pgpBusy : out sl; -- Pause incoming PGP datastream -- Fast control interface - fcSend : in sl; -- Latch fcWord and send it out, will cause pgpBusy to assert - fcWord : in slv(16*FC_WORDS_G-1 downto 0); -- Control word to send - fcSent : out sl; -- Asserted when a fast control word is sent out + fcValid : in sl; -- Latch fcWord and send it out, will cause pgpBusy to assert + fcWord : in slv(16*FC_WORDS_G-1 downto 0); -- Control word to send + fcSent : out sl := '0'; -- Asserted when a fast control word is sent out -- Sideband data - pgpLocLinkReady : in sl; -- Far end side has link - pgpLocData : in slv(7 downto 0); -- Far end side User Data + pgpLocLinkReady : in sl; -- Far end side has link + pgpLocData : in slv(7 downto 0); -- Far end side User Data -- Cell Transmit Interface - cellTxSOC : in sl; -- Cell data start of cell - cellTxSOF : in sl; -- Cell data start of frame - cellTxEOC : in sl; -- Cell data end of cell - cellTxEOF : in sl; -- Cell data end of frame - cellTxEOFE : in sl; -- Cell data end of frame error - cellTxData : in slv(15 downto 0); -- Cell data data + cellTxSOC : in sl; -- Cell data start of cell + cellTxSOF : in sl; -- Cell data start of frame + cellTxEOC : in sl; -- Cell data end of cell + cellTxEOF : in sl; -- Cell data end of frame + cellTxEOFE : in sl; -- Cell data end of frame error + cellTxData : in slv(15 downto 0); -- Cell data data -- Physical Interface Signals - phyTxData : out slv(15 downto 0); -- PHY receive data - phyTxDataK : out slv(1 downto 0); -- PHY receive data is K character - phyTxReady : in sl -- PHY receive interface is ready - ); + phyTxData : out slv(15 downto 0); -- PHY receive data + phyTxDataK : out slv(1 downto 0); -- PHY receive data is K character + phyTxReady : in sl -- PHY receive interface is ready + ); end Pgp2fcTxPhy; @@ -74,28 +74,28 @@ end Pgp2fcTxPhy; architecture Pgp2fcTxPhy of Pgp2fcTxPhy is -- Local Signals - signal intTxLinkReady : sl; + signal intTxLinkReady : sl := '0'; signal nxtTxLinkReady : sl; signal nxtTxData : slv(15 downto 0); - signal nxtTxDataK : slv(1 downto 0); - signal intTxData : slv(15 downto 0); - signal intTxDataK : slv(1 downto 0); + signal nxtTxDataK : slv(1 downto 0); + signal intTxData : slv(15 downto 0) := (others => '0'); + signal intTxDataK : slv(1 downto 0) := (others => '0'); signal ltsAData : slv(15 downto 0); - signal ltsADataK : slv(1 downto 0); + signal ltsADataK : slv(1 downto 0); signal ltsBData : slv(15 downto 0); - signal ltsBDataK : slv(1 downto 0); + signal ltsBDataK : slv(1 downto 0); signal cellData : slv(15 downto 0); - signal cellDataK : slv(1 downto 0); + signal cellDataK : slv(1 downto 0); signal fcData : slv(15 downto 0); - signal fcDataK : slv(1 downto 0); + signal fcDataK : slv(1 downto 0); - signal fcWordLatch : slv(16*FC_WORDS_G-1 downto 0); - signal fcWordCount : integer range 0 to FC_WORDS_G; + signal fcWordLatch : slv(16*FC_WORDS_G-1 downto 0) := (others => '0'); + signal fcWordCount : integer range 0 to FC_WORDS_G := 0; - signal crcRst : sl; - signal crcEn : sl; - signal crcDataIn : slv(15 downto 0); - signal crcOut : slv(7 downto 0); + signal crcRst : sl; + signal crcEn : sl; + signal crcDataIn : slv(15 downto 0); + signal crcOut : slv(7 downto 0); -- Physical Link State type fsm_states is ( @@ -106,32 +106,33 @@ architecture Pgp2fcTxPhy of Pgp2fcTxPhy is ST_CELL_C, ST_EMPTY_C); - signal curState : fsm_states; - signal nxtState : fsm_states; - signal pendState : fsm_states; -- Next state if FC wasn't triggered - signal holdState : fsm_states; + signal curState : fsm_states := ST_LOCK_C; + signal nxtState : fsm_states; + signal pendState : fsm_states; -- Next state if FC wasn't triggered + signal holdState : fsm_states; begin -- Link status pgpTxLinkReady <= intTxLinkReady; - pgpBusy <= '1' when curState = ST_FC_C else '0'; + pgpBusy <= '1' when curState = ST_FC_C else '0'; -- State transition sync logic. - process ( pgpTxClk ) begin + process (pgpTxClk) + begin if rising_edge(pgpTxClk) then if pgpTxClkRst = '1' then - curState <= ST_LOCK_C after TPD_G; - intTxLinkReady <= '0' after TPD_G; + curState <= ST_LOCK_C after TPD_G; + intTxLinkReady <= '0' after TPD_G; elsif pgpTxClkEn = '1' then -- Status signal intTxLinkReady <= nxtTxLinkReady after TPD_G; -- PLL Lock is lost if phyTxReady = '0' then - curState <= ST_LOCK_C after TPD_G; + curState <= ST_LOCK_C after TPD_G; else - curState <= nxtState after TPD_G; + curState <= nxtState after TPD_G; end if; holdState <= pendState after TPD_G; @@ -140,18 +141,19 @@ begin end process; -- Fast Control register logic - process ( pgpTxClk ) begin + process (pgpTxClk) + begin if rising_edge(pgpTxClk) then fcSent <= '0'; - if fcSend = '1' then + if fcValid = '1' then fcWordLatch <= fcWord; end if; if (curState = ST_FC_C) then if (fcWordCount = FC_WORDS_G) then fcWordCount <= 0; - fcSent <= '1'; + fcSent <= '1'; else fcWordCount <= fcWordCount + 1; end if; @@ -163,16 +165,17 @@ begin -- Link control state machine - process ( curState, holdState, fcSend, fcWordCount, fcData, fcDataK, intTxLinkReady, cellTxEOC, - ltsAData, ltsADataK, ltsBData, ltsBDataK, cellData, cellDataK ) begin + process (curState, holdState, fcValid, fcWordCount, fcData, fcDataK, intTxLinkReady, cellTxEOC, + ltsAData, ltsADataK, ltsBData, ltsBDataK, cellData, cellDataK) + begin case curState is -- Wait for lock state when ST_LOCK_C => nxtTxLinkReady <= '0'; - nxtTxData <= (others=>'0'); - nxtTxDataK <= (others=>'0'); + nxtTxData <= (others => '0'); + nxtTxDataK <= (others => '0'); nxtState <= ST_LTS_A_C; pendState <= ST_LTS_A_C; @@ -181,24 +184,24 @@ begin nxtTxData <= ltsAData; nxtTxDataK <= ltsADataK; nxtTxLinkReady <= intTxLinkReady; - if fcSend = '1' then - nxtState <= ST_FC_C; + if fcValid = '1' then + nxtState <= ST_FC_C; else - nxtState <= ST_LTS_B_C; + nxtState <= ST_LTS_B_C; end if; - pendState <= ST_LTS_B_C; + pendState <= ST_LTS_B_C; -- Transmit Link Training word B when ST_LTS_B_C => nxtTxData <= ltsBData; nxtTxDataK <= ltsBDataK; nxtTxLinkReady <= '1'; - if fcSend = '1' then - nxtState <= ST_FC_C; + if fcValid = '1' then + nxtState <= ST_FC_C; else - nxtState <= ST_CELL_C; + nxtState <= ST_CELL_C; end if; - pendState <= ST_CELL_C; + pendState <= ST_CELL_C; -- Transmit Cell Data when ST_CELL_C => @@ -207,8 +210,8 @@ begin nxtTxDataK <= cellDataK; -- State transition - if fcSend = '1' then - nxtState <= ST_FC_C; + if fcValid = '1' then + nxtState <= ST_FC_C; else if cellTxEOC = '1' then nxtState <= ST_EMPTY_C; @@ -218,22 +221,22 @@ begin end if; if cellTxEOC = '1' then - pendState <= ST_EMPTY_C; + pendState <= ST_EMPTY_C; else - pendState <= curState; + pendState <= curState; end if; -- Empty location, used to re-adjust delay pipeline when ST_EMPTY_C => nxtTxLinkReady <= '1'; - nxtTxData <= (others=>'0'); - nxtTxDataK <= (others=>'0'); - if fcSend = '1' then - nxtState <= ST_FC_C; + nxtTxData <= (others => '0'); + nxtTxDataK <= (others => '0'); + if fcValid = '1' then + nxtState <= ST_FC_C; else - nxtState <= ST_LTS_A_C; + nxtState <= ST_LTS_A_C; end if; - pendState <= ST_LTS_A_C; + pendState <= ST_LTS_A_C; -- Transmit Control Word Data when ST_FC_C => @@ -242,105 +245,107 @@ begin nxtTxDataK <= fcDataK; if fcWordCount = FC_WORDS_G then - if fcSend = '1' then - nxtState <= ST_FC_C; + if fcValid = '1' then + nxtState <= ST_FC_C; else - nxtState <= holdState; + nxtState <= holdState; end if; else - nxtState <= curState; + nxtState <= curState; end if; - pendState <= holdState; + pendState <= holdState; -- Default state when others => nxtTxLinkReady <= '0'; - nxtTxData <= (others=>'0'); - nxtTxDataK <= (others=>'0'); + nxtTxData <= (others => '0'); + nxtTxDataK <= (others => '0'); nxtState <= ST_LOCK_C; pendState <= ST_LOCK_C; end case; end process; -- Link Training Word A - ltsAData(7 downto 0) <= K_LTS_C; - ltsADataK(0) <= '1'; - ltsAData(15 downto 8) <= D_102_C; - ltsADataK(1) <= '0'; + ltsAData(7 downto 0) <= K_LTS_C; + ltsADataK(0) <= '1'; + ltsAData(15 downto 8) <= D_102_C; + ltsADataK(1) <= '0'; -- Link Training Word B - ltsBData(7 downto 0) <= pgpLocData; - ltsBDataK(0) <= '0'; - ltsBData(14 downto 12) <= conv_std_logic_vector(FC_WORDS_G-1,3); -- Fast control word count minus 1 - ltsBData(11 downto 8) <= PGP2FC_ID_C; - ltsBData(15) <= pgpLocLinkReady; - ltsBDataK(1) <= '0'; + ltsBData(7 downto 0) <= pgpLocData; + ltsBDataK(0) <= '0'; + ltsBData(14 downto 12) <= conv_std_logic_vector(FC_WORDS_G-1, 3); -- Fast control word count minus 1 + ltsBData(11 downto 8) <= PGP2FC_ID_C; + ltsBData(15) <= pgpLocLinkReady; + ltsBDataK(1) <= '0'; -- Cell Data, lower byte - cellData(7 downto 0) <= K_SOF_C when cellTxSOF = '1' else - K_SOC_C when cellTxSOC = '1' else - K_EOFE_C when cellTxEOFE = '1' else - K_EOF_C when cellTxEOF = '1' else - K_EOC_C when cellTxEOC = '1' else - cellTxData(7 downto 0); + cellData(7 downto 0) <= K_SOF_C when cellTxSOF = '1' else + K_SOC_C when cellTxSOC = '1' else + K_EOFE_C when cellTxEOFE = '1' else + K_EOF_C when cellTxEOF = '1' else + K_EOC_C when cellTxEOC = '1' else + cellTxData(7 downto 0); -- Cell Data, upper byte cellData(15 downto 8) <= cellTxData(15 downto 8); -- Cell Data, lower control cellDataK(0) <= '1' when cellTxSOF = '1' or cellTxSOC = '1' or cellTxEOFE = '1' or - cellTxEOF = '1' or cellTxEOC = '1' else '0'; + cellTxEOF = '1' or cellTxEOC = '1' else '0'; -- Cell Data, upper control cellDataK(1) <= '0'; -- Fast Control data packaging - fcComb: process(fcWord, fcWordLatch, fcWordCount, crcOut) begin + fcComb : process(fcWord, fcWordLatch, fcWordCount, crcOut) + begin if (fcWordCount = 0) then -- First word - fcData(7 downto 0) <= K_FCD_C; - fcDataK(0) <= '1'; + fcData(7 downto 0) <= K_FCD_C; + fcDataK(0) <= '1'; fcData(15 downto 8) <= fcWordLatch(7 downto 0); - fcDataK(1) <= '0'; - crcDataIn <= fcWordLatch(7 downto 0) & K_FCD_C; + fcDataK(1) <= '0'; + crcDataIn <= fcWordLatch(7 downto 0) & K_FCD_C; elsif (fcWordCount = FC_WORDS_G) then -- Last word - fcData(7 downto 0) <= fcWordLatch(FC_WORDS_G*16-1 downto (FC_WORDS_G-1)*16+8); - fcData(15 downto 8) <= crcOut; -- CRC (unregistered, could cause timing issues) - fcDataK <= "00"; - crcDataIn <= x"00" & fcWordLatch(FC_WORDS_G*16-1 downto (FC_WORDS_G-1)*16+8); + fcData(7 downto 0) <= fcWordLatch(FC_WORDS_G*16-1 downto (FC_WORDS_G-1)*16+8); + fcData(15 downto 8) <= crcOut; -- CRC (unregistered, could cause timing issues) + fcDataK <= "00"; + crcDataIn <= x"00" & fcWordLatch(FC_WORDS_G*16-1 downto (FC_WORDS_G-1)*16+8); else -- Other words - fcData <= fcWordLatch(fcWordCount*16+7 downto (fcWordCount-1)*16+8); - fcDataK <= "00"; + fcData <= fcWordLatch(fcWordCount*16+7 downto (fcWordCount-1)*16+8); + fcDataK <= "00"; crcDataIn <= fcWordLatch(fcWordCount*16+7 downto (fcWordCount-1)*16+8); end if; end process; crcRst <= '1' when fcWordCount = FC_WORDS_G else '0'; - crcEn <= '1' when curState = ST_FC_C else '0'; + crcEn <= '1' when curState = ST_FC_C else '0'; U_Crc7 : entity surf.CRC7Rtl - port map ( - rst => crcRst, - clk => pgpTxClk, - data_in => crcDataIn, - crc_en => crcEn, - crc_out => crcOut - ); + port map ( + rst => crcRst, + clk => pgpTxClk, + data_in => crcDataIn, + crc_en => crcEn, + crc_out => crcOut + ); -- Outgoing data (1-cycle delay) -- TODO: Could a cycle be saved here? - process ( pgpTxClk ) begin + process (pgpTxClk) + begin if rising_edge(pgpTxClk) then if pgpTxClkRst = '1' then - intTxData(15 downto 0) <= (others=>'0') after TPD_G; - intTxDataK(1 downto 0) <= (others=>'0') after TPD_G; + intTxData(15 downto 0) <= (others => '0') after TPD_G; + intTxDataK(1 downto 0) <= (others => '0') after TPD_G; elsif pgpTxClkEn = '1' then -- PLL Lock is lost, zero data out if phyTxReady = '0' then - intTxData(15 downto 0) <= (others=>'0') after TPD_G; - intTxDataK(1 downto 0) <= (others=>'0') after TPD_G; + intTxData(15 downto 0) <= (others => '0') after TPD_G; + intTxDataK(1 downto 0) <= (others => '0') after TPD_G; else intTxData(15 downto 0) <= nxtTxData(15 downto 0) after TPD_G; intTxDataK(1 downto 0) <= nxtTxDataK(1 downto 0) after TPD_G; diff --git a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd index 8aa422588d..a57aee2bd9 100644 --- a/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd +++ b/protocols/pgp/pgp2fc/core/rtl/Pgp2fcTxSched.vhd @@ -33,40 +33,40 @@ entity Pgp2fcTxSched is port ( -- System clock, reset & control - pgpTxClkEn : in sl := '1'; -- Master clock Enable - pgpTxClk : in sl; -- Master clock - pgpTxClkRst : in sl; -- Synchronous reset input + pgpTxClkEn : in sl := '1'; -- Master clock Enable + pgpTxClk : in sl; -- Master clock + pgpTxClkRst : in sl; -- Synchronous reset input -- Link flush - pgpTxFlush : in sl; -- Flush the link + pgpTxFlush : in sl; -- Flush the link -- Link is ready - pgpTxLinkReady : in sl; -- Local side has link + pgpTxLinkReady : in sl; -- Local side has link -- Phy is busy - pgpTxBusy : in sl; + pgpTxBusy : in sl; -- Cell Transmit Interface - schTxSOF : in sl; -- Cell contained SOF - schTxEOF : in sl; -- Cell contained EOF - schTxIdle : out sl; -- Force IDLE transmit - schTxReq : out sl; -- Cell transmit request - schTxAck : in sl; -- Cell transmit acknowledge - schTxTimeout : out sl; -- Cell transmit timeout - schTxDataVc : out slv(1 downto 0); -- Cell transmit virtual channel + schTxSOF : in sl; -- Cell contained SOF + schTxEOF : in sl; -- Cell contained EOF + schTxIdle : out sl; -- Force IDLE transmit + schTxReq : out sl; -- Cell transmit request + schTxAck : in sl; -- Cell transmit acknowledge + schTxTimeout : out sl; -- Cell transmit timeout + schTxDataVc : out slv(1 downto 0); -- Cell transmit virtual channel -- VC Data Valid Signals - vc0FrameTxValid : in sl; -- User frame data is valid - vc1FrameTxValid : in sl; -- User frame data is valid - vc2FrameTxValid : in sl; -- User frame data is valid - vc3FrameTxValid : in sl; -- User frame data is valid + vc0FrameTxValid : in sl; -- User frame data is valid + vc1FrameTxValid : in sl; -- User frame data is valid + vc2FrameTxValid : in sl; -- User frame data is valid + vc3FrameTxValid : in sl; -- User frame data is valid -- VC Flow Control Signals - vc0RemAlmostFull : in sl; -- Remote flow control - vc1RemAlmostFull : in sl; -- Remote flow control - vc2RemAlmostFull : in sl; -- Remote flow control - vc3RemAlmostFull : in sl -- Remote flow control - ); + vc0RemAlmostFull : in sl; -- Remote flow control + vc1RemAlmostFull : in sl; -- Remote flow control + vc2RemAlmostFull : in sl; -- Remote flow control + vc3RemAlmostFull : in sl -- Remote flow control + ); end Pgp2fcTxSched; @@ -76,22 +76,22 @@ architecture Pgp2fcTxSched of Pgp2fcTxSched is -- Local Signals signal currValid : sl; - signal currVc : slv(1 downto 0); + signal currVc : slv(1 downto 0) := "00"; signal nextVc : slv(1 downto 0); signal arbVc : slv(1 downto 0); signal arbValid : sl; - signal vcInFrame : slv(3 downto 0); - signal intTxReq : sl; - signal intTxIdle : sl; + signal vcInFrame : slv(3 downto 0) := (others => '0'); + signal intTxReq : sl := '0'; + signal intTxIdle : sl := '0'; signal nxtTxReq : sl; signal nxtTxIdle : sl; signal nxtTxTimeout : sl; - signal intTxTimeout : sl; - signal vcTimerA : slv(23 downto 0); - signal vcTimerB : slv(23 downto 0); - signal vcTimerC : slv(23 downto 0); - signal vcTimerD : slv(23 downto 0); - signal vcTimeout : slv(3 downto 0); + signal intTxTimeout : sl := '0'; + signal vcTimerA : slv(23 downto 0) := (others => '0'); + signal vcTimerB : slv(23 downto 0) := (others => '0'); + signal vcTimerC : slv(23 downto 0) := (others => '0'); + signal vcTimerD : slv(23 downto 0) := (others => '0'); + signal vcTimeout : slv(3 downto 0) := (others => '0'); signal gateTxValid : slv(3 downto 0); -- Schedular state @@ -101,8 +101,8 @@ architecture Pgp2fcTxSched of Pgp2fcTxSched is constant ST_GAP_A_C : slv(2 downto 0) := "100"; constant ST_GAP_B_C : slv(2 downto 0) := "101"; constant ST_GAP_C_C : slv(2 downto 0) := "110"; - signal curState : slv(2 downto 0); - signal nxtState : slv(2 downto 0); + signal curState : slv(2 downto 0) := ST_ARB_C; + signal nxtState : slv(2 downto 0); begin @@ -268,25 +268,25 @@ begin begin case currVc is when "00" => - if gateTxValid(1) = '1' and NUM_VC_EN_G > 1 then arbVc <= "01"; arbValid <= '1'; + if gateTxValid(1) = '1' and NUM_VC_EN_G > 1 then arbVc <= "01"; arbValid <= '1'; elsif gateTxValid(2) = '1' and NUM_VC_EN_G > 2 then arbVc <= "10"; arbValid <= '1'; elsif gateTxValid(3) = '1' and NUM_VC_EN_G > 3 then arbVc <= "11"; arbValid <= '1'; elsif gateTxValid(0) = '1' then arbVc <= "00"; arbValid <= '1'; else arbVc <= "00"; arbValid <= '0'; end if; when "01" => - if gateTxValid(2) = '1' and NUM_VC_EN_G > 2 then arbVc <= "10"; arbValid <= '1'; + if gateTxValid(2) = '1' and NUM_VC_EN_G > 2 then arbVc <= "10"; arbValid <= '1'; elsif gateTxValid(3) = '1' and NUM_VC_EN_G > 3 then arbVc <= "11"; arbValid <= '1'; elsif gateTxValid(0) = '1' then arbVc <= "00"; arbValid <= '1'; elsif gateTxValid(1) = '1' and NUM_VC_EN_G > 1 then arbVc <= "01"; arbValid <= '1'; else arbVc <= "01"; arbValid <= '0'; end if; when "10" => - if gateTxValid(3) = '1' and NUM_VC_EN_G > 3 then arbVc <= "11"; arbValid <= '1'; + if gateTxValid(3) = '1' and NUM_VC_EN_G > 3 then arbVc <= "11"; arbValid <= '1'; elsif gateTxValid(0) = '1' then arbVc <= "00"; arbValid <= '1'; elsif gateTxvalid(1) = '1' and NUM_VC_EN_G > 1 then arbVc <= "01"; arbValid <= '1'; elsif gateTxvalid(2) = '1' and NUM_VC_EN_G > 2 then arbVc <= "10"; arbValid <= '1'; else arbVc <= "10"; arbValid <= '0'; end if; when "11" => - if gateTxValid(0) = '1' then arbVc <= "00"; arbValid <= '1'; + if gateTxValid(0) = '1' then arbVc <= "00"; arbValid <= '1'; elsif gateTxValid(1) = '1' and NUM_VC_EN_G > 1 then arbVc <= "01"; arbValid <= '1'; elsif gateTxValid(2) = '1' and NUM_VC_EN_G > 2 then arbVc <= "10"; arbValid <= '1'; elsif gateTxValid(3) = '1' and NUM_VC_EN_G > 3 then arbVc <= "11"; arbValid <= '1'; diff --git a/protocols/pgp/pgp2fc/core/tb/Pgp2fcLane_tb.vhd b/protocols/pgp/pgp2fc/core/tb/Pgp2fcLane_tb.vhd index 46fc39a4cc..e849f5ce36 100644 --- a/protocols/pgp/pgp2fc/core/tb/Pgp2fcLane_tb.vhd +++ b/protocols/pgp/pgp2fc/core/tb/Pgp2fcLane_tb.vhd @@ -227,7 +227,7 @@ begin FIFO_FIXED_THRESH_G => true, FIFO_PAUSE_THRESH_G => 255, SLAVE_AXI_CONFIG_G => RCEG3_AXIS_DMA_CONFIG_G, - MASTER_AXI_CONFIG_G => SSI_PGP2FC_CONFIG_C) + MASTER_AXI_CONFIG_G => PGP2FC_AXIS_CONFIG_C) port map ( sAxisClk => locClk, sAxisRst => locClkRst, @@ -323,8 +323,8 @@ begin FIFO_FIXED_THRESH_G => true, FIFO_PAUSE_THRESH_G => 511, -- AXI Stream Port Configurations - SLAVE_AXI_CONFIG_G => SSI_PGP2FC_CONFIG_C, - MASTER_AXI_CONFIG_G => SSI_PGP2FC_CONFIG_C + SLAVE_AXI_CONFIG_G => PGP2FC_AXIS_CONFIG_C, + MASTER_AXI_CONFIG_G => PGP2FC_AXIS_CONFIG_C ) port map ( -- Slave Port sAxisClk => locClk, @@ -349,7 +349,7 @@ begin PRBS_TAPS_G => (0 => 16), FIFO_ADDR_WIDTH_G => 9, FIFO_PAUSE_THRESH_G => 256, -- Almost full at 1/2 capacity - SLAVE_AXI_STREAM_CONFIG_G => SSI_PGP2FC_CONFIG_C, + SLAVE_AXI_STREAM_CONFIG_G => PGP2FC_AXIS_CONFIG_C, SLAVE_AXI_PIPE_STAGES_G => 0 ) port map ( sAxisClk => slowClk, diff --git a/protocols/pgp/pgp2fc/core/tb/RoguePgp2fcSim.vhd b/protocols/pgp/pgp2fc/core/tb/RoguePgp2fcSim.vhd new file mode 100644 index 0000000000..c6902b21d6 --- /dev/null +++ b/protocols/pgp/pgp2fc/core/tb/RoguePgp2fcSim.vhd @@ -0,0 +1,197 @@ +------------------------------------------------------------------------------- +-- Title : PGPv2fc: https://confluence.slac.stanford.edu/x/q86fD +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Wrapper on RogueStreamSim to simulate a PGPv3 +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.Pgp2fcPkg.all; +use surf.SsiPkg.all; + +entity RoguePgp2fcSim is + generic ( + TPD_G : time := 1 ns; + FC_WORDS_G : integer range 1 to 8 := 1; + PORT_NUM_G : natural range 1024 to 49151 := 9000; + NUM_VC_G : integer range 1 to 16 := 4); + port ( + -- PGP Clock and Reset + pgpClk : in sl; + pgpClkRst : in sl; + -- Non VC Rx Signals + pgpRxIn : in Pgp2fcRxInType; + pgpRxOut : out Pgp2fcRxOutType; + -- Non VC Tx Signals + pgpTxIn : in Pgp2fcTxInType; + pgpTxOut : out Pgp2fcTxOutType; + -- Frame Transmit Interface + pgpTxMasters : in AxiStreamMasterArray(NUM_VC_G-1 downto 0); + pgpTxSlaves : out AxiStreamSlaveArray(NUM_VC_G-1 downto 0); + -- Frame Receive Interface + pgpRxMasters : out AxiStreamMasterArray(NUM_VC_G-1 downto 0); + pgpRxSlaves : in AxiStreamSlaveArray(NUM_VC_G-1 downto 0)); +end entity RoguePgp2fcSim; + +architecture sim of RoguePgp2fcSim is + + constant FC_AXIS_CFG_C : AxiStreamConfigType := ssiAxiStreamConfig(2*FC_WORDS_G, TKEEP_COMP_C); + constant BYTE_AXIS_CFG_C : AxiStreamConfigType := ssiAxiStreamConfig(2, TKEEP_COMP_C); + + + signal txOut : Pgp2fcTxOutType := PGP2FC_TX_OUT_INIT_C; + signal rxOut : Pgp2fcRxOutType := PGP2FC_RX_OUT_INIT_C; + + signal pgpTxMastersLoc : AxiStreamMasterArray(NUM_VC_G-1 downto 0); + + signal txFcAxisMaster : AxiStreamMasterType := axiStreamMasterInit(FC_AXIS_CFG_C); + signal txFcAxisSlave : AxiStreamSlaveType; + signal rxFcAxisMaster : AxiStreamMasterType := axiStreamMasterInit(FC_AXIS_CFG_C); + signal rxFcAxisSlave : AxiStreamSlaveType; + + signal txByteAxisMaster : AxiStreamMasterType := axiStreamMasterInit(BYTE_AXIS_CFG_C); + signal txByteAxisSlave : AxiStreamSlaveType; + signal rxByteAxisMaster : AxiStreamMasterType := axiStreamMasterInit(BYTE_AXIS_CFG_C); + signal rxByteAxisSlave : AxiStreamSlaveType; + + + +begin + + pgpTxOut <= txOut; + pgpRxOut <= rxOut; + + TDEST_ZERO : process (pgpTxMasters) is + variable tmp : AxiStreamMasterArray(NUM_VC_G-1 downto 0); + begin + tmp := pgpTxMasters; + for i in NUM_VC_G-1 downto 0 loop + tmp(i).tDest := (others => '0'); + end loop; + pgpTxMastersLoc <= tmp; + + end process TDEST_ZERO; + + GEN_VEC : for i in NUM_VC_G-1 downto 0 generate + U_PGP_VC : entity surf.RogueTcpStreamWrap + generic map ( + TPD_G => TPD_G, + PORT_NUM_G => (PORT_NUM_G + i*2), + SSI_EN_G => true, + CHAN_MASK_G => "00000000", + TDEST_MASK_G => toSlv(i, 8), + AXIS_CONFIG_G => PGP2FC_AXIS_CONFIG_C) + port map ( + axisClk => pgpClk, -- [in] + axisRst => pgpClkRst, -- [in] + sAxisMaster => pgpTxMastersLoc(i), -- [in] + sAxisSlave => pgpTxSlaves(i), -- [out] + mAxisMaster => pgpRxMasters(i), -- [out] + mAxisSlave => pgpRxSlaves(i)); -- [in] + end generate GEN_VEC; + + U_RogueSideBandWrap_1 : entity surf.RogueSideBandWrap + generic map ( + TPD_G => TPD_G, + PORT_NUM_G => PORT_NUM_G + 8) + port map ( + sysClk => pgpClk, -- [in] + sysRst => pgpClkRst, -- [in] + txOpCode => X"00", -- [in] + txOpCodeEn => '0', -- [in] + txRemData => pgpTxIn.locData, -- [in] + rxOpCode => open, -- [out] + rxOpCodeEn => open, -- [out] + rxRemData => rxOut.remLinkData); -- [out] + + + -- Send a single txn frame for FC word + txFcAxisMaster.tValid <= pgpTxIn.fcValid; + txFcAxisMaster.tData(FC_WORDS_G*16-1 downto 0) <= pgpTxIn.fcWord(FC_WORDS_G*16-1 downto 0); + txFcAxisMaster.tLast <= pgpTxIn.fcValid; + txFcAxisMaster.tUser(1) <= pgpTxIn.fcValid; + + U_TX_Resize : entity surf.AxiStreamResize + generic map ( + -- General Configurations + TPD_G => TPD_G, + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G => FC_AXIS_CFG_C, + MASTER_AXI_CONFIG_G => BYTE_AXIS_CFG_C) + port map ( + -- Clock and Reset + axisClk => pgpClk, + axisRst => pgpClkRst, + -- Slave Port + sAxisMaster => txFcAxisMaster, + sAxisSlave => txFcAxisSlave, + -- Master Port + mAxisMaster => txByteAxisMaster, + mAxisSlave => txByteAxisSlave); + + + U_PGP_FC : entity surf.RogueTcpStreamWrap + generic map ( + TPD_G => TPD_G, + PORT_NUM_G => (PORT_NUM_G + 10), + SSI_EN_G => true, + CHAN_MASK_G => "00000000", + TDEST_MASK_G => "00000000", + AXIS_CONFIG_G => BYTE_AXIS_CFG_C) + port map ( + axisClk => pgpClk, -- [in] + axisRst => pgpClkRst, -- [in] + sAxisMaster => txByteAxisMaster, -- [in] + sAxisSlave => txByteAxisSlave, -- [out] + mAxisMaster => rxByteAxisMaster, -- [out] + mAxisSlave => rxByteAxisSlave); -- [in] + + U_RX_Resize : entity surf.AxiStreamResize + generic map ( + -- General Configurations + TPD_G => TPD_G, + -- AXI Stream Port Configurations + SLAVE_AXI_CONFIG_G => BYTE_AXIS_CFG_C, + MASTER_AXI_CONFIG_G => FC_AXIS_CFG_C) + port map ( + -- Clock and Reset + axisClk => pgpClk, + axisRst => pgpClkRst, + -- Slave Port + sAxisMaster => rxByteAxisMaster, + sAxisSlave => rxByteAxisSlave, + -- Master Port + mAxisMaster => rxFcAxisMaster, + mAxisSlave => rxFcAxisSlave); + + + -- Receive single txn frame for FC word + rxOut.fcValid <= rxFcAxisMaster.tValid; + rxOut.fcWord(FC_WORDS_G*16-1 downto 0) <= rxFcAxisMaster.tData(FC_WORDS_G*16-1 downto 0); + + txOut.phyTxReady <= '1'; + txOut.linkReady <= '1'; + + rxOut.phyRxReady <= '1'; + rxOut.linkReady <= '1'; + rxOut.remLinkReady <= '1'; + +end sim; diff --git a/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd b/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd new file mode 100644 index 0000000000..1af2dd90c3 --- /dev/null +++ b/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7.vhd @@ -0,0 +1,436 @@ +------------------------------------------------------------------------------- +-- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Gth7 Fixed Latency Module +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.Pgp2fcPkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiLitePkg.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity Pgp2fcGtp7 is + generic ( + TPD_G : time := 1 ns; + COMMON_CLK_G : boolean := false; -- set true if (stableClk = axilClk) + ---------------------------------------------------------------------------------------------- + -- GT Settings + ---------------------------------------------------------------------------------------------- + -- Sim Generics -- + SIM_GTRESET_SPEEDUP_G : string := "FALSE"; + SIM_VERSION_G : string := "2.0"; + SIMULATION_G : boolean := false; + STABLE_CLOCK_PERIOD_G : real := 4.0E-9; --units of seconds + REF_CLK_FREQ_G : real := 125.0E6; + -- TX/RX Settings - Defaults to 2.5 Gbps operation + RXOUT_DIV_G : integer := 2; + TXOUT_DIV_G : integer := 2; + RX_CLK25_DIV_G : integer := 5; -- Set by wizard + TX_CLK25_DIV_G : integer := 5; -- Set by wizard + PMA_RSV_G : bit_vector := x"00000333"; -- Set by wizard + RX_OS_CFG_G : bit_vector := "0001111110000"; -- Set by wizard + RXCDR_CFG_G : bit_vector := x"0000107FE206001041010"; -- Set by wizard + RXLPM_INCM_CFG_G : bit := '1'; -- Set by wizard + RXLPM_IPCM_CFG_G : bit := '0'; -- Set by wizard + + -- Allow TX to run in var lat mode by altering these generics + TX_BUF_EN_G : boolean := false; + TX_OUTCLK_SRC_G : string := "PLLREFCLK"; + TX_PHASE_ALIGN_G : string := "MANUAL"; + -- Configure PLL sources + DYNAMIC_QPLL_G : boolean := false; + TX_PLL_G : string := "PLL0"; + RX_PLL_G : string := "PLL1"; + + ---------------------------------------------------------------------------------------------- + -- PGP Settings + ---------------------------------------------------------------------------------------------- + FC_WORDS_G : integer range 1 to 8 := 1; + VC_INTERLEAVE_G : integer := 0; -- No interleave Frames + PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter + NUM_VC_EN_G : integer range 1 to 4 := 4; + TX_POLARITY_G : sl := '0'; + RX_POLARITY_G : sl := '0'; + TX_ENABLE_G : boolean := true; -- Enable TX direction + RX_ENABLE_G : boolean := true); -- Enable RX direction + port ( + -- GT Clocking + stableClk : in sl; -- GT needs a stable clock to "boot up" + qPllRxSelect : in slv(1 downto 0) := "00"; + qPllTxSelect : in slv(1 downto 0) := "00"; + gtQPllOutRefClk : in slv(1 downto 0) := "00"; -- Signals from QPLLs + gtQPllOutClk : in slv(1 downto 0) := "00"; + gtQPllLock : in slv(1 downto 0) := "00"; + gtQPllRefClkLost : in slv(1 downto 0) := "00"; + gtQPllReset : out slv(1 downto 0); + gtRxRefClkBufg : in sl; -- gtrefclk driving rx side, fed through clock buffer + gtTxOutClk : out sl; + + -- Gt Serial IO + gtRxN : in sl; -- GT Serial Receive Negative + gtRxP : in sl; -- GT Serial Receive Positive + gtTxN : out sl; -- GT Serial Transmit Negative + gtTxP : out sl; -- GT Serial Transmit Positive + + -- Tx Clocking + pgpTxReset : in sl; + pgpTxClk : in sl; + pgpTxMmcmReset : out sl := '0'; + pgpTxMmcmLocked : in sl := '1'; + + -- Rx clocking + pgpRxReset : in sl; + pgpRxRecClk : out sl; -- rxrecclk basically + pgpRxRecClkRst : out sl; -- Reset for recovered clock + pgpRxClk : in sl; -- Run recClk through external MMCM and sent to this input + pgpRxMmcmReset : out sl; + pgpRxMmcmLocked : in sl := '1'; + + -- Non VC Rx Signals + pgpRxIn : in Pgp2fcRxInType; + pgpRxOut : out Pgp2fcRxOutType; + + -- Non VC Tx Signals + pgpTxIn : in Pgp2fcTxInType; + pgpTxOut : out Pgp2fcTxOutType; + + -- Frame Transmit Interface - 1 Lane, Array of 4 VCs + pgpTxMasters : in AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + pgpTxSlaves : out AxiStreamSlaveArray(3 downto 0); + + -- Frame Receive Interface - 1 Lane, Array of 4 VCs + pgpRxMasters : out AxiStreamMasterArray(3 downto 0); + pgpRxMasterMuxed : out AxiStreamMasterType; + pgpRxCtrl : in AxiStreamCtrlArray(3 downto 0); + + -- Debug Interface + txPreCursor : in slv(4 downto 0) := (others => '0'); + txPostCursor : in slv(4 downto 0) := (others => '0'); + txDiffCtrl : in slv(3 downto 0) := "1000"; + drpOverride : in sl := '0'; + -- AXI-Lite Interface + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType); + +end Pgp2fcGtp7; + + +-- Define architecture +architecture rtl of Pgp2fcGtp7 is + + -------------------------------------------------------------------------------------------------- + -- Rx Signals + -------------------------------------------------------------------------------------------------- + -- Rx Clocks + + -- Rx Resets + signal gtRxResetDone : sl; + signal gtRxResetDoneL : sl; + signal gtRxUserReset : sl; + + signal pgpRxResetInt : sl; + + -- PgpRx Signals + signal gtRxData : slv(19 downto 0); -- Feed to 8B10B decoder + signal dataValid : sl; -- no decode or disparity errors + signal dataValidTmp : sl; -- no decode or disparity errors + signal phyRxLaneIn : Pgp2fcRxPhyLaneInType; + signal phyRxReady : sl; -- To RxRst + signal phyRxInit : sl; -- To RxRst + + -------------------------------------------------------------------------------------------------- + -- Tx Signals + -------------------------------------------------------------------------------------------------- + signal gtTxUsrClk : sl; + + signal gtTxResetDone : sl; + + -- PgpTx Signals + signal phyTxLaneOut : Pgp2fcTxPhyLaneOutType; + signal phyTxReady : sl; + + signal stableRst : sl; + signal drpGnt : sl; + signal drpRdy : sl; + signal drpEn : sl; + signal drpWe : sl; + signal drpAddr : slv(8 downto 0); + signal drpDi : slv(15 downto 0); + signal drpDo : slv(15 downto 0); + +begin + + pgpRxResetInt <= pgpRxReset or gtRxResetDoneL; + + -------------------------------------------------------------------------------------------------- + -- PGP Core + -------------------------------------------------------------------------------------------------- + U_Pgp2fcLane_1 : entity surf.Pgp2fcLane + generic map ( + TPD_G => TPD_G, + FC_WORDS_G => FC_WORDS_G, + VC_INTERLEAVE_G => VC_INTERLEAVE_G, + PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G, + NUM_VC_EN_G => NUM_VC_EN_G, + TX_ENABLE_G => TX_ENABLE_G, + RX_ENABLE_G => RX_ENABLE_G) + port map ( + pgpTxClkEn => '1', -- [in] + pgpTxClk => pgpTxClk, -- [in] + pgpTxClkRst => pgpTxReset, -- [in] + pgpTxIn => pgpTxIn, -- [in] + pgpTxOut => pgpTxOut, -- [out] + pgpTxMasters => pgpTxMasters, -- [in] + pgpTxSlaves => pgpTxSlaves, -- [out] + phyTxLaneOut => phyTxLaneOut, -- [out] + phyTxReady => phyTxReady, -- [in] + pgpRxClkEn => '1', -- [in] + pgpRxClk => pgpRxClk, -- [in] + pgpRxClkRst => pgpRxResetInt, -- [in] + pgpRxIn => pgpRxIn, -- [in] + pgpRxOut => pgpRxOut, -- [out] + pgpRxMasters => pgpRxMasters, -- [out] + pgpRxMasterMuxed => pgpRxMasterMuxed, -- [out] + pgpRxCtrl => pgpRxCtrl, -- [in] + phyRxLaneIn => phyRxLaneIn, -- [in] + phyRxReady => gtRxResetDone, -- [in] + phyRxInit => phyRxInit); -- [out] + + ------------------------------------------------------------------------------------------------- + -- Oneshot the phy init because clock may drop out and leave it stuck high + ------------------------------------------------------------------------------------------------- + U_gtRxUserReset : entity surf.SynchronizerOneShot + generic map ( + TPD_G => TPD_G, + IN_POLARITY_G => '1', + OUT_POLARITY_G => '1', + PULSE_WIDTH_G => 100) + port map ( + clk => stableClk, -- [in] + dataIn => phyRxInit, -- [in] + dataOut => gtRxUserReset); -- [out] + + -------------------------------------------------------------------------------------------------- + -- Rx Data Path + -- Hold Decoder and PgpRx in reset until GtRxResetDone. + -------------------------------------------------------------------------------------------------- + gtRxResetDoneL <= not gtRxResetDone; + Decoder8b10b_1 : entity surf.Decoder8b10b + generic map ( + TPD_G => TPD_G, + RST_POLARITY_G => '0', --active low polarity + NUM_BYTES_G => 2) + port map ( + clk => pgpRxClk, + rst => gtRxResetDone, + dataIn => gtRxData, + dataOut => phyRxLaneIn.data, + dataKOut => phyRxLaneIn.dataK, + codeErr => phyRxLaneIn.decErr, + dispErr => phyRxLaneIn.dispErr); + + dataValidTmp <= not (uOr(phyRxLaneIn.decErr) or uOr(phyRxLaneIn.dispErr)); + + ------------------------------------------------------------------------------------------------- + -- Filter on dataValid so that it doesn't drop immediately on errors + -- Not currently hooked up but leaving it in so we can try it someday. + ------------------------------------------------------------------------------------------------- + U_Pgp3RxGearboxAligner_1 : entity surf.Pgp3RxGearboxAligner + generic map ( + TPD_G => TPD_G, + SLIP_WAIT_G => 1) + port map ( + clk => pgpRxClk, -- [in] + rst => gtRxResetDoneL, -- [in] + rxHeader(0) => dataValidTmp, -- [in] + rxHeader(1) => '0', -- [in] + rxHeaderValid => '1', -- [in] + slip => open, -- [out] + locked => dataValid); -- [out] + + pgpRxRecClkRst <= gtRxResetDoneL; + + -------------------------------------------------------------------------------------------------- + -- Tx Data Path + -------------------------------------------------------------------------------------------------- + gtTxUsrClk <= pgpTxClk; + + -------------------------------------------------------------------------------------------------- + -- GTP 7 Core in Fixed Latency mode + -------------------------------------------------------------------------------------------------- + Gtp7Core_1 : entity surf.Gtp7Core + generic map ( + TPD_G => TPD_G, + SIM_GTRESET_SPEEDUP_G => SIM_GTRESET_SPEEDUP_G, + SIM_VERSION_G => SIM_VERSION_G, + SIMULATION_G => SIMULATION_G, + STABLE_CLOCK_PERIOD_G => STABLE_CLOCK_PERIOD_G, + REF_CLK_FREQ_G => REF_CLK_FREQ_G, + RXOUT_DIV_G => RXOUT_DIV_G, + TXOUT_DIV_G => TXOUT_DIV_G, + RX_CLK25_DIV_G => RX_CLK25_DIV_G, + TX_CLK25_DIV_G => TX_CLK25_DIV_G, + PMA_RSV_G => PMA_RSV_G, + RX_OS_CFG_G => RX_OS_CFG_G, + RXCDR_CFG_G => RXCDR_CFG_G, + RXLPM_INCM_CFG_G => RXLPM_INCM_CFG_G, + RXLPM_IPCM_CFG_G => RXLPM_IPCM_CFG_G, + DYNAMIC_QPLL_G => DYNAMIC_QPLL_G, + TX_PLL_G => TX_PLL_G, + RX_PLL_G => RX_PLL_G, + TX_EXT_DATA_WIDTH_G => 16, + TX_INT_DATA_WIDTH_G => 20, + TX_8B10B_EN_G => true, + RX_EXT_DATA_WIDTH_G => 20, + RX_INT_DATA_WIDTH_G => 20, + RX_8B10B_EN_G => false, + TX_BUF_EN_G => TX_BUF_EN_G, + TX_OUTCLK_SRC_G => TX_OUTCLK_SRC_G, + TX_DLY_BYPASS_G => toSl(not TX_BUF_EN_G), + TX_PHASE_ALIGN_G => TX_PHASE_ALIGN_G, + RX_BUF_EN_G => false, + RX_OUTCLK_SRC_G => "OUTCLKPMA", + RX_USRCLK_SRC_G => "RXOUTCLK", + RX_DLY_BYPASS_G => '1', + RX_DDIEN_G => '0', + RX_ALIGN_MODE_G => "FIXED_LAT", +-- ALIGN_COMMA_DOUBLE_G => ALIGN_COMMA_DOUBLE_G, +-- ALIGN_COMMA_ENABLE_G => ALIGN_COMMA_ENABLE_G, +-- ALIGN_COMMA_WORD_G => ALIGN_COMMA_WORD_G, +-- ALIGN_MCOMMA_DET_G => ALIGN_MCOMMA_DET_G, +-- ALIGN_MCOMMA_VALUE_G => ALIGN_MCOMMA_VALUE_G, +-- ALIGN_MCOMMA_EN_G => ALIGN_MCOMMA_EN_G, +-- ALIGN_PCOMMA_DET_G => ALIGN_PCOMMA_DET_G, +-- ALIGN_PCOMMA_VALUE_G => ALIGN_PCOMMA_VALUE_G, +-- ALIGN_PCOMMA_EN_G => ALIGN_PCOMMA_EN_G, +-- SHOW_REALIGN_COMMA_G => SHOW_REALIGN_COMMA_G, + RXSLIDE_MODE_G => "PMA", + FIXED_ALIGN_COMMA_0_G => "----------0101111100", -- Normal Comma + FIXED_ALIGN_COMMA_1_G => "----------1010000011", -- Inverted Comma + FIXED_ALIGN_COMMA_2_G => "XXXXXXXXXXXXXXXXXXXX", -- Unused + FIXED_ALIGN_COMMA_3_G => "XXXXXXXXXXXXXXXXXXXX" -- Unused +-- RX_DISPERR_SEQ_MATCH_G => RX_DISPERR_SEQ_MATCH_G, +-- DEC_MCOMMA_DETECT_G => DEC_MCOMMA_DETECT_G, +-- DEC_PCOMMA_DETECT_G => DEC_PCOMMA_DETECT_G, +-- DEC_VALID_COMMA_ONLY_G => DEC_VALID_COMMA_ONLY_G + ) + port map ( + stableClkIn => stableClk, + qPllRxSelect => qPllRxSelect, + qPllTxSelect => qPllTxSelect, + qPllRefClkIn => gtQPllOutRefClk, + qPllClkIn => gtQPllOutClk, + qPllLockIn => gtQPllLock, + qPllRefClkLostIn => gtQPllRefClkLost, + qPllResetOut => gtQPllReset, + gtRxRefClkBufg => gtRxRefClkBufg, + gtTxP => gtTxP, + gtTxN => gtTxN, + gtRxP => gtRxP, + gtRxN => gtRxN, + rxOutClkOut => pgpRxRecClk, + rxUsrClkIn => pgpRxClk, + rxUsrClk2In => pgpRxClk, + rxUserRdyOut => open, -- rx clock locked and stable, but alignment not yet done + rxMmcmResetOut => pgpRxMmcmReset, + rxMmcmLockedIn => pgpRxMmcmLocked, + rxUserResetIn => gtRxUserReset, + rxResetDoneOut => gtRxResetDone, -- Use for rxRecClkReset??? + rxDataValidIn => '1', -- From 8b10b + rxSlideIn => '0', -- Slide is controlled internally + rxDataOut => gtRxData, + rxCharIsKOut => open, -- Not using gt rx 8b10b + rxDecErrOut => open, -- Not using gt rx 8b10b + rxDispErrOut => open, -- Not using gt rx 8b10b + rxPolarityIn => RX_POLARITY_G, + rxBufStatusOut => open, -- Not using rx buff + txOutClkOut => gtTxOutClk, -- Maybe drive PGP TX with this and output it + txUsrClkIn => gtTxUsrClk, + txUsrClk2In => gtTxUsrClk, + txUserRdyOut => open, -- Not sure what to do with this + txMmcmResetOut => pgpTxMmcmReset, -- No Tx MMCM in Fixed Latency mode + txMmcmLockedIn => pgpTxMmcmLocked, + txUserResetIn => pgpTxReset, + txResetDoneOut => gtTxResetDone, + txDataIn => phyTxLaneOut.data, + txCharIsKIn => phyTxLaneOut.dataK, + txPolarityIn => TX_POLARITY_G, + txBufStatusOut => open, -- Not using tx buff + loopbackIn => pgpRxIn.loopback, + txPreCursor => txPreCursor, + txPostCursor => txPostCursor, + txDiffCtrl => txDiffCtrl, + drpOverride => drpOverride, + drpGnt => drpGnt, + drpRdy => drpRdy, + drpEn => drpEn, + drpWe => drpWe, + drpAddr => drpAddr, + drpDi => drpDi, + drpDo => drpDo); + + U_AxiLiteToDrp : entity surf.AxiLiteToDrp + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => COMMON_CLK_G, + EN_ARBITRATION_G => true, + TIMEOUT_G => 4096, + ADDR_WIDTH_G => 9, + DATA_WIDTH_G => 16) + port map ( + -- AXI-Lite Port + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave, + -- DRP Interface + drpClk => stableClk, + drpRst => stableRst, + drpGnt => drpGnt, + drpRdy => drpRdy, + drpEn => drpEn, + drpWe => drpWe, + drpAddr => drpAddr, + drpDi => drpDi, + drpDo => drpDo); + + GEN_RST : if (COMMON_CLK_G = false) generate + U_RstSync : entity surf.RstSync + generic map ( + TPD_G => TPD_G) + port map ( + clk => stableClk, + asyncRst => axilRst, + syncRst => stableRst); + end generate; + + BYP_RST_SYNC : if (COMMON_CLK_G = true) generate + stableRst <= axilRst; + end generate; + +end rtl; + diff --git a/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd b/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd new file mode 100644 index 0000000000..e22e023cbc --- /dev/null +++ b/protocols/pgp/pgp2fc/gtp7/rtl/Pgp2fcGtp7Wrapper.vhd @@ -0,0 +1,537 @@ +------------------------------------------------------------------------------- +-- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Gtp7 Fixed Latency Wrapper +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.Pgp2fcPkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiLitePkg.all; +use surf.Gtp7CfgPkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity Pgp2fcGtp7Wrapper is + generic ( + TPD_G : time := 1 ns; + COMMON_CLK_G : boolean := false; -- set true if (stableClk = axilClk) + SIM_GTRESET_SPEEDUP_G : boolean := false; + SIM_VERSION_G : string := "2.0"; + SIMULATION_G : boolean := false; + -- PGP Settings + FC_WORDS_G : integer range 1 to 8 := 1; + VC_INTERLEAVE_G : integer := 0; -- No interleave Frames + PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter + NUM_VC_EN_G : integer range 1 to 4 := 4; + AXIL_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); + EXT_RST_POLARITY_G : sl := '1'; + TX_POLARITY_G : sl := '0'; + RX_POLARITY_G : sl := '0'; + TX_ENABLE_G : boolean := true; -- Enable TX direction + RX_ENABLE_G : boolean := true; -- Enable RX direction + -- CM Configurations + TX_CM_EN_G : boolean := true; + TX_CM_TYPE_G : string := "MMCM"; + TX_CM_BANDWIDTH_G : string := "OPTIMIZED"; + TX_CM_CLKIN_PERIOD_G : real := 8.000; + TX_CM_DIVCLK_DIVIDE_G : natural := 8; + TX_CM_CLKFBOUT_MULT_F_G : real := 8.000; + TX_CM_CLKFBOUT_MULT_G : integer range 2 to 64 := 8; + TX_CM_CLKOUT_DIVIDE_F_G : real := 8.000; + TX_CM_CLKOUT_DIVIDE_G : integer range 1 to 128 := 8; + RX_CM_EN_G : boolean := true; + RX_CM_TYPE_G : string := "MMCM"; + RX_CM_BANDWIDTH_G : string := "HIGH"; + RX_CM_CLKIN_PERIOD_G : real := 8.000; + RX_CM_DIVCLK_DIVIDE_G : natural := 8; + RX_CM_CLKFBOUT_MULT_F_G : real := 8.000; + RX_CM_CLKFBOUT_MULT_G : integer range 2 to 64 := 8; + RX_CM_CLKOUT_DIVIDE_F_G : real := 8.000; + RX_CM_CLKOUT_DIVIDE_G : integer range 1 to 128 := 8; + -- MGT Configurations + PMA_RSV_G : bit_vector := x"00018480"; + RX_OS_CFG_G : bit_vector := "0000010000000"; -- Set by wizard + RXCDR_CFG_G : bit_vector := x"00003000023ff40200020"; -- Set by wizard + RXDFEXYDEN_G : sl := '0'; -- Set by wizard + -- PLL and clock configurations + STABLE_CLK_SRC_G : string := "stableClkIn"; -- or "gtClk0" or "gtClk1" + TX_REFCLK_SRC_G : string := "gtClk0"; + TX_USER_CLK_SRC_G : string := "txRefClk"; -- Could be txOutClk instead + TX_BUF_EN_G : boolean := false; + TX_OUTCLK_SRC_G : string := "PLLREFCLK"; + TX_PHASE_ALIGN_G : string := "MANUAL"; + RX_REFCLK_SRC_G : string := "gtClk0"; + TX_PLL_CFG_G : Gtp7QPllCfgType := getGtp7QPllCfg(156.25e6, 3.125e9); + RX_PLL_CFG_G : Gtp7QPllCfgType := getGtp7QPllCfg(156.25e6, 3.125e9); + DYNAMIC_QPLL_G : boolean := false; + TX_PLL_G : string := "PLL0"; + RX_PLL_G : string := "PLL0"); + port ( + -- Manual Reset + stableClkIn : in sl := '0'; + extRst : in sl; + -- Status and Clock Signals + txPllLock : out sl; + rxPllLock : out sl; + -- Output internally configured clocks + pgpTxClkOut : out sl; + pgpTxRstOut : out sl; + pgpRxClkOut : out sl; + pgpRxRstOut : out sl; + stableClkOut : out sl; + -- Non VC Rx Signals + pgpRxIn : in Pgp2fcRxInType; + pgpRxOut : out Pgp2fcRxOutType; + -- Non VC Tx Signals + pgpTxIn : in Pgp2fcTxInType; + pgpTxOut : out Pgp2fcTxOutType; + -- Frame Transmit Interface - 1 Lane, Array of 4 VCs + pgpTxMasters : in AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + pgpTxSlaves : out AxiStreamSlaveArray(3 downto 0); + -- Frame Receive Interface - 1 Lane, Array of 4 VCs + pgpRxMasters : out AxiStreamMasterArray(3 downto 0); + pgpRxMasterMuxed : out AxiStreamMasterType; + pgpRxCtrl : in AxiStreamCtrlArray(3 downto 0); + -- GT Pins + gtgClk : in sl := '0'; + gtClk0P : in sl := '0'; + gtClk0N : in sl := '0'; + gtClk1P : in sl := '0'; + gtClk1N : in sl := '0'; + gtTxP : out sl; + gtTxN : out sl; + gtRxP : in sl; + gtRxN : in sl; + -- Debug Interface + txPreCursor : in slv(4 downto 0) := (others => '0'); + txPostCursor : in slv(4 downto 0) := (others => '0'); + txDiffCtrl : in slv(3 downto 0) := "1000"; + drpOverride : in sl := '0'; + qPllRxSelect : in slv(1 downto 0) := "00"; + qPllTxSelect : in slv(1 downto 0) := "00"; + -- AXI-Lite Interface + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType); +end Pgp2fcGtp7Wrapper; + +architecture rtl of Pgp2fcGtp7Wrapper is + + constant PLL0_CFG_C : Gtp7QPllCfgType := ite(TX_PLL_G = "PLL0", TX_PLL_CFG_G, RX_PLL_CFG_G); + constant PLL1_CFG_C : Gtp7QPllCfgType := ite(TX_PLL_G = "PLL1", TX_PLL_CFG_G, RX_PLL_CFG_G); + + constant SIM_GTRESET_SPEEDUP_C : string := ite(SIM_GTRESET_SPEEDUP_G, "TRUE", "FALSE"); + + signal gtClk0 : sl := '0'; + signal gtClk0Div2 : sl; + signal gtClk1 : sl := '0'; + signal gtClk1Div2 : sl; + + signal txRefClk : sl := '0'; + signal txOutClk : sl := '0'; + signal rxRefClk : sl := '0'; + + signal stableClkRef : sl := '0'; + signal stableClkRefG : sl := '0'; + signal stableClk : sl := '0'; + signal stableRst : sl := '0'; + + signal pgpTxClkBase : sl; + signal pgpTxClk : sl; + signal pgpTxReset : sl; + signal pgpTxMmcmReset : sl; + signal pgpTxMmcmLocked : sl; + + signal pgpRxRecClk : sl; + signal pgpRxRecClkRst : sl; + signal pgpRxClkLoc : sl; + signal pgpRxReset : sl; + signal pgpRxMmcmReset : sl; + signal pgpRxMmcmLocked : sl; + + signal qPllRefClk : slv(1 downto 0) := "00"; + signal qPllOutClk : slv(1 downto 0) := "00"; + signal qPllOutRefClk : slv(1 downto 0) := "00"; + signal qPllLock : slv(1 downto 0) := "00"; + signal qPllLockDetClk : slv(1 downto 0) := "00"; + signal qPllRefClkLost : slv(1 downto 0) := "00"; + signal qPllReset : slv(1 downto 0) := "00"; + + signal locAxilWriteMasters : AxiLiteWriteMasterArray(1 downto 0) := (others => AXI_LITE_WRITE_MASTER_INIT_C); + signal locAxilWriteSlaves : AxiLiteWriteSlaveArray(1 downto 0) := (others => AXI_LITE_WRITE_SLAVE_INIT_C); + signal locAxilReadMasters : AxiLiteReadMasterArray(1 downto 0) := (others => AXI_LITE_READ_MASTER_INIT_C); + signal locAxilReadSlaves : AxiLiteReadSlaveArray(1 downto 0) := (others => AXI_LITE_READ_SLAVE_INIT_C); + +begin + + + + ------------------------------------------------------------------------------------------------- + -- Bring in the refclocks through IBUFDS_GTE2 instances + ------------------------------------------------------------------------------------------------- + BUFDS_GTE2_0_GEN : if (TX_REFCLK_SRC_G = "gtClk0" or RX_REFCLK_SRC_G = "gtClk0") generate + IBUFDS_GTE2_0 : IBUFDS_GTE2 + port map ( + I => gtClk0P, + IB => gtClk0N, + CEB => '0', + ODIV2 => gtClk0Div2, + O => gtClk0); + end generate; + + IBUFDS_GTE2_1_GEN : if (TX_REFCLK_SRC_G = "gtClk1" or RX_REFCLK_SRC_G = "gtClk1") generate + IBUFDS_GTE2_1 : IBUFDS_GTE2 + port map ( + I => gtClk1P, + IB => gtClk1N, + CEB => '0', + ODIV2 => gtClk1Div2, + O => gtClk1); + end generate; + + ------------------------------------------------------------------------------------------------- + -- Create the stable clock and reset + ------------------------------------------------------------------------------------------------- + stableClkRef <= gtClk0 when STABLE_CLK_SRC_G = "gtClk0" else + gtClk0Div2 when STABLE_CLK_SRC_G = "gtClk0Div2" else + gtClk1 when STABLE_CLK_SRC_G = "gtClk1" else + gtClk1Div2 when STABLE_CLK_SRC_G = "gtClk1Div2" else + '0'; + + + BUFG_stableClkRef : BUFG + port map ( + I => stableClkRef, + O => stableClkRefG); + + stableClk <= stableClkIn when STABLE_CLK_SRC_G = "stableClkIn" else + stableClkRefG; + + + -- Power Up Reset + PwrUpRst_Inst : entity surf.PwrUpRst + generic map ( + TPD_G => TPD_G, + SIM_SPEEDUP_G => SIMULATION_G, + IN_POLARITY_G => EXT_RST_POLARITY_G, + OUT_POLARITY_G => '1') + port map ( + arst => extRst, + clk => stableClk, + rstOut => stableRst); + + ------------------------------------------------------------------------------------------------- + -- Select the rxRefClk + ------------------------------------------------------------------------------------------------- + rxRefClk <= gtClk0 when RX_REFCLK_SRC_G = "gtClk0" else + gtClk1 when RX_REFCLK_SRC_G = "gtClk1" else + gtgClk when TX_REFCLK_SRC_G = "gtgClk" else + '0'; + + ------------------------------------------------------------------------------------------------- + -- Select the txRefClk + -- Generate TX user (PGP) clock + -- Might want option to bypass MMCM + ------------------------------------------------------------------------------------------------- + txRefClk <= gtClk0 when TX_REFCLK_SRC_G = "gtClk0" else + gtClk1 when TX_REFCLK_SRC_G = "gtClk1" else + gtgClk when TX_REFCLK_SRC_G = "gtgClk" else + '0'; + + + -- pgpTxClk and stable clock might be the same + pgpTxClkBase <= txOutClk when TX_USER_CLK_SRC_G = "txOutClk" else + stableClk when STABLE_CLK_SRC_G = TX_USER_CLK_SRC_G else + gtClk0 when TX_USER_CLK_SRC_G = "gtClk0" else + gtClk0Div2 when TX_USER_CLK_SRC_G = "gtClk0Div2" else + gtClk1 when TX_USER_CLK_SRC_G = "gtClk1" else + gtClk1Div2 when TX_USER_CLK_SRC_G = "gtClk1Div2" else + txRefClk; + + TX_CM_GEN : if (TX_CM_EN_G) generate + ClockManager7_TX : entity surf.ClockManager7 + generic map( + TPD_G => TPD_G, + TYPE_G => TX_CM_TYPE_G, + INPUT_BUFG_G => ((TX_USER_CLK_SRC_G = "txOutClk") or (TX_REFCLK_SRC_G /= STABLE_CLK_SRC_G)), + FB_BUFG_G => true, + RST_IN_POLARITY_G => '1', + NUM_CLOCKS_G => 1, + -- MMCM attributes + BANDWIDTH_G => TX_CM_BANDWIDTH_G, + CLKIN_PERIOD_G => TX_CM_CLKIN_PERIOD_G, + DIVCLK_DIVIDE_G => TX_CM_DIVCLK_DIVIDE_G, + CLKFBOUT_MULT_F_G => TX_CM_CLKFBOUT_MULT_F_G, + CLKFBOUT_MULT_G => TX_CM_CLKFBOUT_MULT_G, + CLKOUT0_DIVIDE_F_G => TX_CM_CLKOUT_DIVIDE_F_G, + CLKOUT0_DIVIDE_G => TX_CM_CLKOUT_DIVIDE_G, + CLKOUT0_RST_HOLD_G => 16) + port map( + clkIn => pgpTxClkBase, + rstIn => pgpTxMmcmReset, + clkOut(0) => pgpTxClk, + locked => pgpTxMmcmLocked); + + pgpTxReset <= extRst; + + end generate TX_CM_GEN; + + NO_TX_CM_GEN : if (not TX_CM_EN_G) generate + pgpTxMmcmLocked <= '1'; + + BUFG_pgpTxClk : BUFG + port map ( + i => pgpTxClkBase, + o => pgpTxClk); + + RstSync_pgpTxRst : entity surf.RstSync + generic map ( + TPD_G => TPD_G, + RELEASE_DELAY_G => 16, + OUT_REG_RST_G => true) + port map ( + clk => pgpTxClk, -- [in] + asyncRst => extRst, -- [in] + syncRst => pgpTxReset); -- [out] + + end generate NO_TX_CM_GEN; + + -- PGP RX Reset + RstSync_pgpRxRst : entity surf.RstSync + generic map ( + TPD_G => TPD_G, + RELEASE_DELAY_G => 16, + OUT_REG_RST_G => true) + port map ( + clk => pgpRxClkLoc, -- [in] + asyncRst => extRst, -- [in] + syncRst => pgpRxReset); -- [out] + + + ------------------------------------------------------------------------------------------------- + -- Determine PLL clocks + ------------------------------------------------------------------------------------------------- + qPllRefClk(0) <= txRefClk when (TX_PLL_G = "PLL0") else + rxRefClk when (RX_PLL_G = "PLL0") else + '0'; + + qPllRefClk(1) <= txRefClk when (TX_PLL_G = "PLL1") else + rxRefClk when (RX_PLL_G = "PLL1") else + '0'; + + -- Double check this. I think the pllLockDetClk must be different from the pll refclk +-- qPllLockDetClk(0) <= stableClk when ((TX_PLL_G = "PLL0") or (RX_PLL_G = "PLL0")) else '0'; +-- qPllLockDetClk(1) <= stableClk when ((TX_PLL_G = "PLL1") or (RX_PLL_G = "PLL1")) else '0'; + qPllLockDetClk(0) <= '0'; + qPllLockDetClk(1) <= '0'; + + -- Set the status outputs + txPllLock <= ite((TX_PLL_G = "PLL0"), qPllLock(0), qPllLock(1)); + rxPllLock <= ite((RX_PLL_G = "PLL0"), qPllLock(0), qPllLock(1)); + + + U_Gtp7QuadPll_1 : entity surf.Gtp7QuadPll + generic map ( + TPD_G => TPD_G, + SIM_RESET_SPEEDUP_G => SIM_GTRESET_SPEEDUP_C, + SIM_VERSION_G => SIM_VERSION_G, + PLL0_REFCLK_SEL_G => "001", + PLL0_FBDIV_IN_G => PLL0_CFG_C.QPLL_FBDIV_G, + PLL0_FBDIV_45_IN_G => PLL0_CFG_C.QPLL_FBDIV_45_G, + PLL0_REFCLK_DIV_IN_G => PLL0_CFG_C.QPLL_REFCLK_DIV_G, + PLL1_REFCLK_SEL_G => "001", + PLL1_FBDIV_IN_G => PLL1_CFG_C.QPLL_FBDIV_G, + PLL1_FBDIV_45_IN_G => PLL1_CFG_C.QPLL_FBDIV_45_G, + PLL1_REFCLK_DIV_IN_G => PLL1_CFG_C.QPLL_REFCLK_DIV_G) + port map ( + qPllRefClk => qPllRefClk, -- [in] + qPllOutClk => qPllOutClk, -- [out] + qPllOutRefClk => qPllOutRefClk, -- [out] + qPllLock => qPllLock, -- [out] + qPllLockDetClk => qPllLockDetClk, -- [in] + qPllRefClkLost => open, -- [out] + qPllReset => qPllReset, -- [in] + axilClk => axilClk, -- [in] + axilRst => axilRst, -- [in] + axilReadMaster => locAxilReadMasters(1), -- [in] + axilReadSlave => locAxilReadSlaves(1), -- [out] + axilWriteMaster => locAxilWriteMasters(1), -- [in] + axilWriteSlave => locAxilWriteSlaves(1)); -- [out] + + + Pgp2fcGtp7_Inst : entity surf.Pgp2fcGtp7 + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => COMMON_CLK_G, + SIM_GTRESET_SPEEDUP_G => SIM_GTRESET_SPEEDUP_C, + SIM_VERSION_G => SIM_VERSION_G, + SIMULATION_G => SIMULATION_G, + STABLE_CLOCK_PERIOD_G => 4.0E-9, --set for longest timeout + RXOUT_DIV_G => RX_PLL_CFG_G.OUT_DIV_G, + TXOUT_DIV_G => TX_PLL_CFG_G.OUT_DIV_G, + RX_CLK25_DIV_G => 7, --RX_PLL_CFG_G.CLK25_DIV_G, + TX_CLK25_DIV_G => 7, --TX_PLL_CFG_G.CLK25_DIV_G, + PMA_RSV_G => PMA_RSV_G, + RX_OS_CFG_G => RX_OS_CFG_G, + RXCDR_CFG_G => RXCDR_CFG_G, + TX_BUF_EN_G => TX_BUF_EN_G, + TX_OUTCLK_SRC_G => TX_OUTCLK_SRC_G, + TX_PHASE_ALIGN_G => TX_PHASE_ALIGN_G, + DYNAMIC_QPLL_G => DYNAMIC_QPLL_G, + TX_PLL_G => TX_PLL_G, + RX_PLL_G => RX_PLL_G, + VC_INTERLEAVE_G => VC_INTERLEAVE_G, + FC_WORDS_G => FC_WORDS_G, + PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G, + NUM_VC_EN_G => NUM_VC_EN_G, + TX_POLARITY_G => TX_POLARITY_G, + RX_POLARITY_G => RX_POLARITY_G, + TX_ENABLE_G => TX_ENABLE_G, + RX_ENABLE_G => RX_ENABLE_G) + port map ( + -- GT Clocking + stableClk => stableClk, + qPllRxSelect => qPllRxSelect, + qPllTxSelect => qPllTxSelect, + gtQPllOutRefClk => qPllOutRefClk, + gtQPllOutClk => qPllOutClk, + gtQPllLock => qPllLock, + gtQPllRefClkLost => qPllRefClkLost, + gtQPllReset => qPllReset, + gtRxRefClkBufg => '0', -- Probably can remove this + gtTxOutClk => txOutClk, + -- Gt Serial IO + gtTxP => gtTxP, + gtTxN => gtTxN, + gtRxP => gtRxP, + gtRxN => gtRxN, + -- Tx Clocking + pgpTxReset => pgpTxReset, + pgpTxClk => pgpTxClk, + pgpTxMmcmReset => pgpTxMmcmReset, + pgpTxMmcmLocked => pgpTxMmcmLocked, + + -- Rx clocking + pgpRxReset => pgpRxReset, --extRst, + pgpRxRecClk => pgpRxRecClk, + pgpRxRecClkRst => pgpRxRecClkRst, + pgpRxClk => pgpRxClkLoc, -- RecClk fed back, optionally though MMCM + pgpRxMmcmReset => pgpRxMmcmReset, + pgpRxMmcmLocked => pgpRxMmcmLocked, + -- Non VC Rx Signals + pgpRxIn => pgpRxIn, + pgpRxOut => pgpRxOut, + -- Non VC Tx Signals + pgpTxIn => pgpTxIn, + pgpTxOut => pgpTxOut, + -- Frame Transmit Interface - 1 Lane, Array of 4 VCs + pgpTxMasters => pgpTxMasters, + pgpTxSlaves => pgpTxSlaves, + -- Frame Receive Interface - 1 Lane, Array of 4 VCs + pgpRxMasters => pgpRxMasters, + pgpRxMasterMuxed => pgpRxMasterMuxed, + pgpRxCtrl => pgpRxCtrl, + -- Debug Interface + txPreCursor => txPreCursor, + txPostCursor => txPostCursor, + txDiffCtrl => txDiffCtrl, + drpOverride => drpOverride, + -- AXI-Lite Interface + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => locAxilReadMasters(0), + axilReadSlave => locAxilReadSlaves(0), + axilWriteMaster => locAxilWriteMasters(0), + axilWriteSlave => locAxilWriteSlaves(0)); + + ------------------------------------------------------------------------------------------------- + -- Clock manager to clean up recovered clock + ------------------------------------------------------------------------------------------------- + RxClkMmcmGen : if (RX_CM_EN_G) generate + ClockManager7_1 : entity surf.ClockManager7 + generic map ( + TPD_G => TPD_G, + TYPE_G => RX_CM_TYPE_G, + INPUT_BUFG_G => false, + FB_BUFG_G => true, + NUM_CLOCKS_G => 1, + BANDWIDTH_G => RX_CM_BANDWIDTH_G, + CLKIN_PERIOD_G => RX_CM_CLKIN_PERIOD_G, + DIVCLK_DIVIDE_G => RX_CM_DIVCLK_DIVIDE_G, + CLKFBOUT_MULT_F_G => RX_CM_CLKFBOUT_MULT_F_G, + CLKFBOUT_MULT_G => RX_CM_CLKFBOUT_MULT_G, + CLKOUT0_DIVIDE_F_G => RX_CM_CLKOUT_DIVIDE_F_G, + CLKOUT0_DIVIDE_G => RX_CM_CLKOUT_DIVIDE_G, + CLKOUT0_RST_HOLD_G => 16) + port map ( + clkIn => pgpRxRecClk, + rstIn => pgpRxMmcmReset, + clkOut(0) => pgpRxClkLoc, + locked => pgpRxMmcmLocked); + + -- I think this is right, sync reset to mmcm clk + RstSync_1 : entity surf.RstSync + generic map ( + TPD_G => TPD_G) + port map ( + clk => pgpRxClkLoc, + asyncRst => pgpRxRecClkRst, + syncRst => pgpRxRstOut); + end generate RxClkMmcmGen; + + RxClkNoMmcmGen : if (not RX_CM_EN_G) generate + pgpRxClkLoc <= pgpRxRecClk; + pgpRxRstOut <= pgpRxRecClkRst; + pgpRxMmcmLocked <= '1'; + end generate RxClkNoMmcmGen; + + pgpRxClkOut <= pgpRxClkLoc; + pgpTxClkOut <= pgpTxClk; + pgpTxRstOut <= pgpTxReset; + + stableClkOut <= stableClk; + + ------------------------------------------------------------------------------------------------- + -- AXI-Lite crossbar + ------------------------------------------------------------------------------------------------- + U_AxiLiteCrossbar_1 : entity surf.AxiLiteCrossbar + generic map ( + TPD_G => TPD_G, + NUM_SLAVE_SLOTS_G => 1, + NUM_MASTER_SLOTS_G => 2, + MASTERS_CONFIG_G => genAxiLiteConfig(2, AXIL_BASE_ADDR_G, 16, 12), + DEBUG_G => true) + port map ( + axiClk => axilClk, -- [in] + axiClkRst => axilRst, -- [in] + sAxiWriteMasters(0) => axilWriteMaster, -- [in] + sAxiWriteSlaves(0) => axilWriteSlave, -- [out] + sAxiReadMasters(0) => axilReadMaster, -- [in] + sAxiReadSlaves(0) => axilReadSlave, -- [out] + mAxiWriteMasters => locAxilWriteMasters, -- [out] + mAxiWriteSlaves => locAxilWriteSlaves, -- [in] + mAxiReadMasters => locAxilReadMasters, -- [out] + mAxiReadSlaves => locAxilReadSlaves); -- [in] + +end rtl; diff --git a/protocols/pgp/pgp2fc/gtp7/ruckus.tcl b/protocols/pgp/pgp2fc/gtp7/ruckus.tcl new file mode 100644 index 0000000000..2110a84e87 --- /dev/null +++ b/protocols/pgp/pgp2fc/gtp7/ruckus.tcl @@ -0,0 +1,5 @@ +# Load RUCKUS library +source -quiet $::env(RUCKUS_DIR)/vivado/proc.tcl + +# Load Source Code +loadSource -lib surf -dir "$::DIR_PATH/rtl" diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp new file mode 100644 index 0000000000..b705a004c6 --- /dev/null +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:44598e02aeab4733c5c014c81bf55c67b402f5340221ca793d1c43a8699c80c0 +size 313487 diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci new file mode 100644 index 0000000000..1d790d3728 --- /dev/null +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/Pgp2fcGtyCore.xci @@ -0,0 +1,934 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "Pgp2fcGtyCore", + "component_reference": "xilinx.com:ip:gtwizard_ultrascale:1.7", + "ip_revision": "16", + "gen_directory": "../../../../TrackerPcieBittware_project.gen/sources_1/ip/Pgp2fcGtyCore", + "parameters": { + "component_parameters": { + "GT_TYPE": [ { "value": "GTY", "resolve_type": "user", "usage": "all" } ], + "INTERNAL_GT_PRIM_TYPE": [ { "value": "gtye4", "resolve_type": "generated", "enabled": false, "usage": "all" } ], + "GT_REV": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "GT_DIRECTION": [ { "value": "BOTH", "resolve_type": "user", "usage": "all" } ], + "RX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ], + "TX_ENABLE": [ { "value": "true", "resolve_type": "generated", "format": "bool", "enabled": false, "usage": "all" } ], + "CHANNEL_ENABLE": [ { "value": "X0Y4", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TX_MASTER_CHANNEL": [ { "value": "X0Y4", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "RX_MASTER_CHANNEL": [ { "value": "X0Y4", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "INTERNAL_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_TOTAL_NUM_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "LOCATE_COMMON": [ { "value": "CORE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "INTERNAL_NUM_COMMONS_CORE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_NUM_COMMONS_EXAMPLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "INTERNAL_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ], + "INTERNAL_RX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "enabled": false, "usage": "all" } ], + "RX_PPM_OFFSET": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "OOB_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "INS_LOSS_NYQ": [ { "value": "14", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCIE_CORECLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCIE_USERCLK_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "TX_LINE_RATE": [ { "value": "3.7142857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "TX_PLL_TYPE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TX_REFCLK_FREQUENCY": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "TX_DATA_ENCODING": [ { "value": "8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TX_USER_DATA_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TX_INT_DATA_WIDTH": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TX_BUFFER_MODE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "TX_OUTCLK_SOURCE": [ { "value": "TXPLLREFCLK_DIV1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ], + "RX_LINE_RATE": [ { "value": "3.7142857", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RX_PLL_TYPE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_REFCLK_FREQUENCY": [ { "value": "185.714285", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RX_DATA_DECODING": [ { "value": "8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_USER_DATA_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_INT_DATA_WIDTH": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_BUFFER_MODE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ], + "RX_JTOL_FC": [ { "value": "2.2281258", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_OUTCLK_SOURCE": [ { "value": "RXOUTCLKPMA", "resolve_type": "user", "usage": "all" } ], + "SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ], + "RX_TERMINATION_PROG_VALUE": [ { "value": "800", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_COUPLING": [ { "value": "AC", "resolve_type": "user", "usage": "all" } ], + "RX_BUFFER_BYPASS_MODE": [ { "value": "MULTI", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "RX_BUFFER_RESET_ON_CB_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "RX_BUFFER_RESET_ON_COMMAALIGN": [ { "value": "DISABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "RX_BUFFER_RESET_ON_RATE_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "TX_BUFFER_RESET_ON_RATE_CHANGE": [ { "value": "ENABLE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "RESET_SEQUENCE_INTERVAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_COMMA_PRESET": [ { "value": "K28.5", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_COMMA_VALID_ONLY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_COMMA_P_ENABLE": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RX_COMMA_M_ENABLE": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RX_COMMA_DOUBLE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RX_COMMA_P_VAL": [ { "value": "0110000011", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_COMMA_M_VAL": [ { "value": "1001111100", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_COMMA_MASK": [ { "value": "1111111111", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_COMMA_ALIGN_WORD": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_COMMA_SHOW_REALIGN_ENABLE": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RX_SLIDE_MODE": [ { "value": "OFF", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "RX_CB_NUM_SEQ": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "RX_CB_LEN_SEQ": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "RX_CB_MAX_SKEW": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "RX_CB_MAX_LEVEL": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "RX_CB_MASK": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ], + "RX_CB_VAL": [ { "value": "00000000000000000000000000000000000000000000000000000000000000000000000000000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ], + "RX_CB_K": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ], + "RX_CB_DISP": [ { "value": "00000000", "resolve_type": "generated", "enabled": false, "usage": "all" } ], + "RX_CB_MASK_0_0": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "RX_CB_VAL_0_0": [ { "value": "00000000", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "RX_CB_K_0_0": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "RX_CB_DISP_0_0": [ { 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"float", "usage": "all" } ], + "C_RX_SLIDE_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RX_USER_CLOCKING_CONTENTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RX_USER_CLOCKING_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RX_USER_CLOCKING_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RX_USER_DATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_RX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_RX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_SECONDARY_QPLL_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_SECONDARY_QPLL_REFCLK_FREQUENCY": [ { "value": "257.8125", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TOTAL_NUM_CHANNELS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TOTAL_NUM_COMMONS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TOTAL_NUM_COMMONS_EXAMPLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TXPROGDIV_FREQ_ENABLE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TXPROGDIV_FREQ_SOURCE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TXPROGDIV_FREQ_VAL": [ { "value": "185.714285", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TX_BUFFBYPASS_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_BUFFER_BYPASS_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_BUFFER_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_DATA_ENCODING": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_ENABLE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_INT_DATA_WIDTH": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_LINE_RATE": [ { "value": "3.7142857", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TX_MASTER_CHANNEL_IDX": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_OUTCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TX_OUTCLK_SOURCE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_PLL_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_REFCLK_FREQUENCY": [ { "value": "185.714285", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TX_USER_CLOCKING_CONTENTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USER_CLOCKING_INSTANCE_CTRL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USER_CLOCKING_SOURCE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USER_DATA_WIDTH": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TX_USRCLK_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_TX_USRCLK2_FREQUENCY": [ { "value": "185.7142850", "resolve_type": "generated", "format": "float", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "virtexuplus" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xcvu9p" } ], + "PACKAGE": [ { "value": "fsgd2104" } ], + "PREFHDL": [ { "value": "VHDL" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "16" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../TrackerPcieBittware_project.gen/sources_1/ip/Pgp2fcGtyCore" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2023.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "gtwiz_userclk_tx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_userclk_tx_active_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_userclk_rx_active_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_tx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_tx_start_user_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_tx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_tx_error_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_rx_reset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_rx_start_user_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_rx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_buffbypass_rx_error_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_clk_freerun_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_all_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_tx_pll_and_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_tx_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_rx_pll_and_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_rx_datapath_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_rx_cdr_stable_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_tx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_reset_rx_done_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtwiz_userdata_tx_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "gtwiz_userdata_rx_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "cplllockdetclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "cplllocken_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ], + "cpllrefclksel_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x1" } ], + "drpaddr_in": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ], + "drpclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "drpdi_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "drpen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "drpwe_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtgrefclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "gtrefclk0_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtyrxn_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtyrxp_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "loopback_in": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], + "rx8b10ben_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxcdrreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "rxcommadeten_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxmcommaalignen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpcommaalignen_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "rxpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "rxpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxusrclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxusrclk2_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "tx8b10ben_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txctrl0_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "txctrl1_in": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "txctrl2_in": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "txpcsreset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "txpmareset_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "txpolarity_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txusrclk_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txusrclk2_in": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "cpllfbclklost_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "cplllock_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "cpllrefclklost_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "drpdo_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "drprdy_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtpowergood_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtytxn_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "gtytxp_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxbyteisaligned_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxbyterealign_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxcommadet_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxctrl0_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "rxctrl1_out": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "rxctrl2_out": [ { "direction": "out", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "rxctrl3_out": [ { "direction": "out", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "rxdlysresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxphaligndone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxrecclkout_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "rxsyncdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txoutclk_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txpmaresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "txresetdone_out": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ] + } + } + } +} \ No newline at end of file diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/reference/PgpGtyCore.dcp b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/reference/PgpGtyCore.dcp new file mode 100644 index 0000000000..09345c2008 --- /dev/null +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/reference/PgpGtyCore.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:53ae761ec01ce7e2973284a6c8d6f1148f527bbdd20efd1062bec0921ff7d2c8 +size 445718 diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/reference/PgpGtyCore.txt b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/reference/PgpGtyCore.txt new file mode 100644 index 0000000000..40796a74ec --- /dev/null +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/reference/PgpGtyCore.txt @@ -0,0 +1,20 @@ +## LLR - 22SEPT2020 +## After generating each of the .DCP files from their corresponding .XCI files, +## performed the following TCL commands in the DCP to generate a modified DCP file: + +# Remove the IO Lock Constraints +set_property is_loc_fixed false [get_ports [list gtytxp_out[0]]] +set_property is_loc_fixed false [get_ports [list gtytxn_out[0]]] +set_property is_loc_fixed false [get_ports [list gtyrxp_in[0]]] +set_property is_loc_fixed false [get_ports [list gtyrxn_in[0]]] + +# Removed the IO location Constraints +set_property package_pin "" [get_ports [list gtytxp_out[0]]] +set_property package_pin "" [get_ports [list gtytxn_out[0]]] +set_property package_pin "" [get_ports [list gtyrxp_in[0]]] +set_property package_pin "" [get_ports [list gtyrxn_in[0]]] + +# Removed the Placement Constraints +set_property is_bel_fixed false [get_cells -hierarchical *GTYE4_CHANNEL_PRIM_INST*] +set_property is_loc_fixed false [get_cells -hierarchical *GTYE4_CHANNEL_PRIM_INST*] +unplace_cell [get_cells -hierarchical *GTYE4_CHANNEL_PRIM_INST*] diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ip/reference/TimingGty_extref.xci b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/reference/TimingGty_extref.xci new file mode 100644 index 0000000000..ba61b6da28 --- /dev/null +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ip/reference/TimingGty_extref.xci @@ -0,0 +1,1433 @@ + + + xilinx.com + xci + unknown + 1.0 + + + TimingGty_extref + + + "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000" + 1 + 3714.2857 + 0 + 0 + 78.125 + 67 + 3 + 2 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 0 + 250 + 0 + 0 + 0 + 0 + 0 + 0 + "00000000" + "00000000" + 1 + 1 + 0 + "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + "00000000" + 0 + "00000000" + 1 + 0 + 5000 + "00000000000000000000000000000000000000000000000000000000000000000000000000000000" + 1 + "1010000011" + 1 + "0101111100" + 1 + 1 + 20 + 3.7142857 + 12 + 1 + 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0000000000..8c885043ee --- /dev/null +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd @@ -0,0 +1,450 @@ +------------------------------------------------------------------------------- +-- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: PGPv2b GTY Ultrascale IP Core Wrapper +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity Pgp2fcGtyCoreWrapper is + generic ( + TPD_G : time := 1 ns; + SEL_FABRIC_REFCLK_G : boolean := false; + USE_ALIGN_CHECK_G : boolean := true; + AXI_CLK_FREQ_G : real := 125.0e6; + AXI_BASE_ADDR_G : slv(31 downto 0) := (others => '0')); + port ( + stableClk : in sl; + stableRst : in sl; + + -- GTY FPGA IO + gtRefClk : in sl; + gtFabricRefClk : in sl; + gtUserRefClk : in sl; + gtRxP : in sl; + gtRxN : in sl; + gtTxP : out sl; + gtTxN : out sl; + + -- Rx ports + rxReset : in sl; + rxUsrClkActive : in sl; + rxResetDone : out sl; + rxUsrClk : in sl; + rxData : out slv(15 downto 0); + rxDataK : out slv(1 downto 0); + rxDispErr : out slv(1 downto 0); + rxDecErr : out slv(1 downto 0); + rxPolarity : in sl; + rxOutClk : out sl; + rxRecClk : out sl; -- raw recovered clock + + -- Tx Ports + txReset : in sl; + txUsrClk : in sl; + txUsrClkActive : in sl; + txResetDone : out sl; + txData : in slv(15 downto 0); + txDataK : in slv(1 downto 0); + txPolarity : in sl; + txOutClk : out sl; + loopback : in slv(2 downto 0); + + -- AXI-Lite DRP interface + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType); + +end entity Pgp2fcGtyCoreWrapper; + +architecture mapping of Pgp2fcGtyCoreWrapper is + + component Pgp2fcGtyCore + port ( + gtwiz_userclk_tx_reset_in : in std_logic_vector (0 downto 0); + gtwiz_userclk_tx_active_in : in std_logic_vector (0 downto 0); + gtwiz_userclk_rx_active_in : in std_logic_vector (0 downto 0); + gtwiz_buffbypass_tx_reset_in : in std_logic_vector (0 downto 0); + gtwiz_buffbypass_tx_start_user_in : in std_logic_vector (0 downto 0); + gtwiz_buffbypass_tx_done_out : out std_logic_vector (0 downto 0); + gtwiz_buffbypass_tx_error_out : out std_logic_vector (0 downto 0); + gtwiz_buffbypass_rx_reset_in : in std_logic_vector (0 downto 0); + gtwiz_buffbypass_rx_start_user_in : in std_logic_vector (0 downto 0); + gtwiz_buffbypass_rx_done_out : out std_logic_vector (0 downto 0); + gtwiz_buffbypass_rx_error_out : out std_logic_vector (0 downto 0); + gtwiz_reset_clk_freerun_in : in std_logic_vector (0 downto 0); + gtwiz_reset_all_in : in std_logic_vector (0 downto 0); + gtwiz_reset_tx_pll_and_datapath_in : in std_logic_vector (0 downto 0); + gtwiz_reset_tx_datapath_in : in std_logic_vector (0 downto 0); + gtwiz_reset_rx_pll_and_datapath_in : in std_logic_vector (0 downto 0); + gtwiz_reset_rx_datapath_in : in std_logic_vector (0 downto 0); + gtwiz_reset_rx_cdr_stable_out : out std_logic_vector (0 downto 0); + gtwiz_reset_tx_done_out : out std_logic_vector (0 downto 0); + gtwiz_reset_rx_done_out : out std_logic_vector (0 downto 0); + gtwiz_userdata_tx_in : in std_logic_vector (15 downto 0); + gtwiz_userdata_rx_out : out std_logic_vector (15 downto 0); + cpllrefclksel_in : in std_logic_vector (2 downto 0); + cplllockdetclk_in : in std_logic_vector (0 downto 0); + cplllocken_in : in std_logic_vector (0 downto 0); + drpaddr_in : in std_logic_vector (9 downto 0); + drpclk_in : in std_logic_vector (0 downto 0); + drpdi_in : in std_logic_vector (15 downto 0); + drpen_in : in std_logic_vector (0 downto 0); + drpwe_in : in std_logic_vector (0 downto 0); + gtgrefclk_in : in std_logic_vector (0 downto 0); + gtrefclk0_in : in std_logic_vector (0 downto 0); + gtyrxn_in : in std_logic_vector (0 downto 0); + gtyrxp_in : in std_logic_vector (0 downto 0); + loopback_in : in std_logic_vector (2 downto 0); + rx8b10ben_in : in std_logic_vector (0 downto 0); + rxcdrreset_in : in std_logic_vector (0 downto 0); + rxcommadeten_in : in std_logic_vector (0 downto 0); + rxmcommaalignen_in : in std_logic_vector (0 downto 0); + rxpcommaalignen_in : in std_logic_vector (0 downto 0); + rxpcsreset_in : in std_logic_vector (0 downto 0); + rxpmareset_in : in std_logic_vector (0 downto 0); + rxpolarity_in : in std_logic_vector (0 downto 0); + rxusrclk_in : in std_logic_vector (0 downto 0); + rxusrclk2_in : in std_logic_vector (0 downto 0); + tx8b10ben_in : in std_logic_vector (0 downto 0); + txctrl0_in : in std_logic_vector (15 downto 0); + txctrl1_in : in std_logic_vector (15 downto 0); + txctrl2_in : in std_logic_vector (7 downto 0); + txpcsreset_in : in std_logic_vector (0 downto 0); + txpmareset_in : in std_logic_vector (0 downto 0); + txpolarity_in : in std_logic_vector (0 downto 0); + txusrclk_in : in std_logic_vector (0 downto 0); + txusrclk2_in : in std_logic_vector (0 downto 0); + cpllfbclklost_out : out std_logic_vector (0 downto 0); + cplllock_out : out std_logic_vector (0 downto 0); + cpllrefclklost_out : out std_logic_vector (0 downto 0); + drpdo_out : out std_logic_vector (15 downto 0); + drprdy_out : out std_logic_vector (0 downto 0); + gtpowergood_out : out std_logic_vector (0 downto 0); + gtytxn_out : out std_logic_vector (0 downto 0); + gtytxp_out : out std_logic_vector (0 downto 0); + rxbyteisaligned_out : out std_logic_vector (0 downto 0); + rxbyterealign_out : out std_logic_vector (0 downto 0); + rxcommadet_out : out std_logic_vector (0 downto 0); + rxctrl0_out : out std_logic_vector (15 downto 0); + rxctrl1_out : out std_logic_vector (15 downto 0); + rxctrl2_out : out std_logic_vector (7 downto 0); + rxctrl3_out : out std_logic_vector (7 downto 0); + rxdlysresetdone_out : out std_logic_vector (0 downto 0); + rxoutclk_out : out std_logic_vector (0 downto 0); + rxrecclkout_out : out std_logic_vector (0 downto 0); + rxphaligndone_out : out std_logic_vector (0 downto 0); + rxpmaresetdone_out : out std_logic_vector (0 downto 0); + rxresetdone_out : out std_logic_vector (0 downto 0); + rxsyncdone_out : out std_logic_vector (0 downto 0); + txoutclk_out : out std_logic_vector (0 downto 0); + txpmaresetdone_out : out std_logic_vector (0 downto 0); + txresetdone_out : out std_logic_vector (0 downto 0)); + end component; + + constant AXI_CROSSBAR_MASTERS_CONFIG_C : AxiLiteCrossbarMasterConfigArray(1 downto 0) := ( + 0 => ( + baseAddr => (AXI_BASE_ADDR_G), + addrBits => 12, + connectivity => x"FFFF"), + 1 => ( + baseAddr => (AXI_BASE_ADDR_G+x"1000"), + addrBits => 12, + connectivity => x"FFFF")); + + signal axilWriteMasters : AxiLiteWriteMasterArray(1 downto 0); + signal axilWriteSlaves : AxiLiteWriteSlaveArray(1 downto 0); + signal axilReadMasters : AxiLiteReadMasterArray(1 downto 0); + signal axilReadSlaves : AxiLiteReadSlaveArray(1 downto 0); + + signal mAxilWriteMaster : AxiLiteWriteMasterType; + signal mAxilWriteSlave : AxiLiteWriteSlaveType; + signal mAxilReadMaster : AxiLiteReadMasterType; + signal mAxilReadSlave : AxiLiteReadSlaveType; + + signal drpAddr : slv(9 downto 0) := (others => '0'); + signal drpDi : slv(15 downto 0) := (others => '0'); + signal drpDo : slv(15 downto 0) := (others => '0'); + signal drpEn : sl := '0'; + signal drpWe : sl := '0'; + signal drpRdy : sl := '0'; + signal dummy0_6 : slv(5 downto 0) := (others => '0'); + signal dummy1_14 : slv(13 downto 0) := (others => '0'); + signal dummy2_14 : slv(13 downto 0) := (others => '0'); + signal dummy3_6 : slv(5 downto 0) := (others => '0'); + signal dummy4_1 : sl := '0'; + signal dummy5_1 : sl := '0'; + signal txctrl2 : slv(7 downto 0) := (others => '0'); + + signal cPllRefClkSel : slv(2 downto 0) := (others => '0'); + signal cPllFbClkLost : sl := '0'; + signal cPllLock : sl := '0'; + signal cPllRefClkLost : sl := '0'; + signal rxCdrReset : sl := '0'; + signal rxPcsReset : sl := '0'; + signal rxPmaReset : sl := '0'; + signal txPcsReset : sl := '0'; + signal txPmaReset : sl := '0'; + signal rxPmaResetDone : sl := '0'; + signal txPmaResetDone : sl := '0'; + signal rxByteIsAligned : sl := '0'; + signal rxByteReAlign : sl := '0'; + signal rxCommaDet : sl := '0'; + signal txUsrActive : sl := '0'; + signal rxUsrActive : sl := '0'; + signal rxMcommaAlignEn : sl := '1'; + signal rxPcommaAlignEn : sl := '1'; + signal buffBypassTxReset : sl := '0'; + signal buffBypassTxStart : sl := '0'; + signal buffBypassTxDone : sl := '0'; + signal buffBypassTxError : sl := '0'; + signal buffBypassRxReset : sl := '0'; + signal buffBypassRxStart : sl := '0'; + signal buffBypassRxDone : sl := '0'; + signal buffBypassRxError : sl := '0'; + signal rxDlysResetDone : sl := '0'; + signal rxPhyAlignDone : sl := '0'; + signal rxSyncDone : sl := '0'; + signal txResetGt : sl := '0'; + signal rxResetGt : sl := '0'; + signal rxResetAlignCheck : sl := '0'; + signal rstSyncRxIn : sl := '0'; + signal rxStatusLocked : sl := '0'; + signal rxOutClkGt : sl := '0'; + signal txOutClkGt : sl := '0'; + signal rxOutClkB : sl := '0'; + signal txOutClkB : sl := '0'; + +begin + + -- Has to be generated from aurora core in order to work properly. + -- Also, look out for the K-character 8b/10b alignment parameters; + -- sometimes the core resets these to the default value (K28.5). + -- The 8b/10b decoder aligns automatically for K28.1 (PGP2FC). + -- The core features a GTGrefclk port, that should be connected + -- to a fabric-generated clock (idea stolen from LCLS-II timing repo). + -- This will only work if the fabric clock is 185.714MHz, and if + -- the associated generic is set to true. + U_Pgp2fcGtyCore : Pgp2fcGtyCore + port map ( + gtwiz_userclk_tx_active_in(0) => txUsrActive, + gtwiz_userclk_rx_active_in(0) => rxUsrActive, + gtwiz_reset_clk_freerun_in(0) => stableClk, + gtwiz_reset_all_in(0) => stableRst, + gtwiz_buffbypass_tx_reset_in(0) => buffBypassTxReset, + gtwiz_buffbypass_tx_start_user_in(0) => buffBypassTxStart, + gtwiz_buffbypass_tx_done_out(0) => buffBypassTxDone, + gtwiz_buffbypass_tx_error_out(0) => buffBypassTxError, + gtwiz_buffbypass_rx_reset_in(0) => buffBypassRxReset, + gtwiz_buffbypass_rx_start_user_in(0) => buffBypassRxStart, + gtwiz_buffbypass_rx_done_out(0) => buffBypassRxDone, + gtwiz_buffbypass_rx_error_out(0) => buffBypassRxError, + gtwiz_userclk_tx_reset_in(0) => buffBypassTxReset, + gtwiz_reset_tx_pll_and_datapath_in(0) => '0', + gtwiz_reset_tx_datapath_in(0) => txReset, + gtwiz_reset_rx_pll_and_datapath_in(0) => '0', + gtwiz_reset_rx_datapath_in(0) => rxResetGt, + gtwiz_reset_rx_cdr_stable_out => open, + gtwiz_reset_tx_done_out => open, + gtwiz_reset_rx_done_out => open, + gtwiz_userdata_tx_in => txData, + gtwiz_userdata_rx_out => rxData, + cpllrefclksel_in => cPllRefClkSel, + cplllockdetclk_in(0) => stableClk, + cplllocken_in(0) => '1', + cpllfbclklost_out(0) => cPllFbClkLost, + cplllock_out(0) => cPllLock, + cpllrefclklost_out(0) => cPllRefClkLost, + drpclk_in(0) => stableClk, + drpaddr_in => drpAddr, + drpdi_in => drpDi, + drpen_in(0) => drpEn, + drpwe_in(0) => drpWe, + drpdo_out => drpDo, + drprdy_out(0) => drpRdy, + gtyrxn_in(0) => gtRxN, + gtyrxp_in(0) => gtRxP, + gtgrefclk_in(0) => gtFabricRefClk, + gtrefclk0_in(0) => gtRefClk, + loopback_in => loopback, + rx8b10ben_in(0) => '1', + rxcdrreset_in(0) => rxCdrReset, + rxcommadeten_in(0) => '1', + rxmcommaalignen_in(0) => rxMcommaAlignEn, + rxpcommaalignen_in(0) => rxPcommaAlignEn, + rxpcsreset_in(0) => rxPcsReset, + rxpmareset_in(0) => rxPmaReset, + txpcsreset_in(0) => txPcsReset, + txpmareset_in(0) => txPmaReset, + rxpolarity_in(0) => rxPolarity, + rxusrclk_in(0) => rxUsrClk, + rxusrclk2_in(0) => rxUsrClk, + tx8b10ben_in(0) => '1', + txctrl0_in => X"0000", + txctrl1_in => X"0000", + txctrl2_in => txctrl2, + txpolarity_in(0) => txPolarity, + txusrclk_in(0) => txUsrClk, + txusrclk2_in(0) => txUsrClk, + gtytxn_out(0) => gtTxN, + gtytxp_out(0) => gtTxP, + rxbyteisaligned_out(0) => rxByteIsAligned, + rxbyterealign_out(0) => rxByteReAlign, + rxcommadet_out(0) => rxCommaDet, + rxctrl0_out(1 downto 0) => rxDataK, + rxctrl0_out(15 downto 2) => dummy1_14, + rxctrl1_out(1 downto 0) => rxDispErr, + rxctrl1_out(15 downto 2) => dummy2_14, + rxctrl2_out => open, + rxctrl3_out(1 downto 0) => rxDecErr, + rxctrl3_out(7 downto 2) => dummy0_6, + rxdlysresetdone_out(0) => rxDlysResetDone, + rxphaligndone_out(0) => rxPhyAlignDone, + rxoutclk_out(0) => rxOutClkGt, + rxrecclkout_out(0) => rxRecClk, + txoutclk_out(0) => txOutClkGt, -- unused + rxpmaresetdone_out(0) => rxPmaResetDone, + rxresetdone_out(0) => rxResetDone, + rxsyncdone_out(0) => rxSyncDone, + txpmaresetdone_out(0) => txPmaResetDone, + txresetdone_out(0) => txResetDone); + + TIMING_RECCLK_BUFG_GT : BUFG_GT + port map ( + I => rxOutClkGt, + CE => '1', + CEMASK => '1', + CLR => '0', + CLRMASK => '1', + DIV => "000", + O => rxOutClkB); + + -- if one does not use the userRefClk for the txOutClk, placement errors occur + txOutClkB <= gtUserRefClk; + + U_XBAR : entity surf.AxiLiteCrossbar + generic map ( + TPD_G => TPD_G, + NUM_SLAVE_SLOTS_G => 2, + NUM_MASTER_SLOTS_G => 2, + MASTERS_CONFIG_G => AXI_CROSSBAR_MASTERS_CONFIG_C) + port map ( + axiClk => axilClk, + axiClkRst => axilRst, + sAxiWriteMasters(0) => axilWriteMaster, + sAxiWriteMasters(1) => mAxilWriteMaster, + sAxiWriteSlaves(0) => axilWriteSlave, + sAxiWriteSlaves(1) => mAxilWriteSlave, + sAxiReadMasters(0) => axilReadMaster, + sAxiReadMasters(1) => mAxilReadMaster, + sAxiReadSlaves(0) => axilReadSlave, + sAxiReadSlaves(1) => mAxilReadSlave, + mAxiWriteMasters => axilWriteMasters, + mAxiWriteSlaves => axilWriteSlaves, + mAxiReadMasters => axilReadMasters, + mAxiReadSlaves => axilReadSlaves); + + U_AlignCheck : entity surf.GtRxAlignCheck + generic map ( + TPD_G => TPD_G, + GT_TYPE_G => "GTYE4", + AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, + DRP_ADDR_G => AXI_CROSSBAR_MASTERS_CONFIG_C(1).baseAddr) + port map ( + -- Clock Monitoring + txClk => txUsrClk, + rxClk => rxUsrClk, + refClk => gtUserRefClk, + -- GTH Status/Control Interface + resetIn => rxReset, + resetDone => buffBypassRxDone, + resetErr => buffBypassRxError, + resetOut => rxResetAlignCheck, + locked => rxStatusLocked, + -- Clock and Reset + axilClk => axilClk, + axilRst => axilRst, + -- Slave AXI-Lite Interface + mAxilReadMaster => mAxilReadMaster, + mAxilReadSlave => mAxilReadSlave, + mAxilWriteMaster => mAxilWriteMaster, + mAxilWriteSlave => mAxilWriteSlave, + -- Slave AXI-Lite Interface + sAxilReadMaster => axilReadMasters(0), + sAxilReadSlave => axilReadSlaves(0), + sAxilWriteMaster => axilWriteMasters(0), + sAxilWriteSlave => axilWriteSlaves(0)); + + U_AxiLiteToDrp_1 : entity surf.AxiLiteToDrp + generic map ( + TPD_G => TPD_G, + COMMON_CLK_G => false, + EN_ARBITRATION_G => false, + ADDR_WIDTH_G => 10, + DATA_WIDTH_G => 16) + port map ( + axilClk => axilClk, -- [in] + axilRst => axilRst, -- [in] + axilReadMaster => axilReadMasters(1), -- [in] + axilReadSlave => axilReadSlaves(1), -- [out] + axilWriteMaster => axilWriteMasters(1), -- [in] + axilWriteSlave => axilWriteSlaves(1), -- [out] + drpClk => stableClk, -- [in] + drpRst => stableRst, -- [in] + drpReq => open, -- [out] + drpRdy => drpRdy, -- [in] + drpEn => drpEn, -- [out] + drpWe => drpWe, -- [out] + drpUsrRst => open, -- [out] + drpAddr => drpAddr, -- [out] + drpDi => drpDi, -- [out] + drpDo => drpDo); -- [in] + + txctrl2 <= "000000" & txDataK; + txUsrActive <= txUsrClkActive and txPmaResetDone; + rxUsrActive <= rxUsrClkActive and rxPmaResetDone; + + cPllRefClkSel <= ite(SEL_FABRIC_REFCLK_G, "111", "001"); + + rstSyncRxIn <= ite(USE_ALIGN_CHECK_G, rxResetAlignCheck, rxReset); + rxResetGt <= ite(USE_ALIGN_CHECK_G, rxResetAlignCheck, rxReset); + + txOutClk <= txOutClkB; + rxOutClk <= rxOutClkB; + + U_RstSyncTx : entity surf.RstSync + generic map (TPD_G => TPD_G) + port map (clk => gtUserRefClk, + asyncRst => txReset, + syncRst => buffBypassTxReset); + + U_RstSyncRx : entity surf.RstSync + generic map (TPD_G => TPD_G) + port map (clk => gtUserRefClk, + asyncRst => rstSyncRxIn, + syncRst => buffBypassRxReset); + +end architecture mapping; diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd new file mode 100644 index 0000000000..e79c1a662e --- /dev/null +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyUltra.vhd @@ -0,0 +1,233 @@ +------------------------------------------------------------------------------- +-- Title : PGPv2b: https://confluence.slac.stanford.edu/x/q86fD +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: PGPv2b GTY Ultrascale Core Module +------------------------------------------------------------------------------- +-- This file is part of 'SLAC Firmware Standard Library'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'SLAC Firmware Standard Library', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiLitePkg.all; +use surf.Pgp2fcPkg.all; + +library UNISIM; +use UNISIM.VCOMPONENTS.all; + +entity Pgp2fcGtyUltra is + generic ( + TPD_G : time := 1 ns; + SIMULATION_G : boolean := false; + ---------------------------------------------------------------------------------------------- + -- PGP Settings + ---------------------------------------------------------------------------------------------- + FC_WORDS_G : integer range 1 to 8 := 1; + TX_POLARITY_G : sl := '0'; + RX_POLARITY_G : sl := '0'; + AXI_CLK_FREQ_G : real := 125.0e6; + AXI_BASE_ADDR_G : slv(31 downto 0) := (others => '0'); + TX_ENABLE_G : boolean := true; + RX_ENABLE_G : boolean := true; + PAYLOAD_CNT_TOP_G : integer := 7; -- Top bit for payload counter + VC_INTERLEAVE_G : integer := 0; -- Interleave Frames + NUM_VC_EN_G : integer range 1 to 4 := 4); + port ( + -- GT Clocking + stableClk : in sl; -- GT needs a stable clock to "boot up" + stableRst : in sl; + gtRefClk : in sl; + gtFabricRefClk : in sl; + gtUserRefClk : in sl; + rxRecClk : out sl; + -- Gt Serial IO + pgpGtTxP : out sl; + pgpGtTxN : out sl; + pgpGtRxP : in sl; + pgpGtRxN : in sl; + -- Tx Clocking + pgpTxReset : in sl; + pgpTxResetDone : out sl; + pgpTxOutClk : out sl; -- recovered clock + pgpTxClk : in sl; + pgpTxMmcmLocked : in sl; + -- Rx clocking + pgpRxReset : in sl; + pgpRxResetDone : out sl; + pgpRxOutClk : out sl; -- recovered clock + pgpRxClk : in sl; + pgpRxMmcmLocked : in sl; + -- Non VC Rx Signals + pgpRxIn : in Pgp2fcRxInType; + pgpRxOut : out Pgp2fcRxOutType; + -- Non VC Tx Signals + pgpTxIn : in Pgp2fcTxInType; + pgpTxOut : out Pgp2fcTxOutType; + -- Frame Transmit Interface - 1 Lane, Array of 4 VCs + pgpTxMasters : in AxiStreamMasterArray(3 downto 0) := (others => AXI_STREAM_MASTER_INIT_C); + pgpTxSlaves : out AxiStreamSlaveArray(3 downto 0); + -- Frame Receive Interface - 1 Lane, Array of 4 VCs + pgpRxMasters : out AxiStreamMasterArray(3 downto 0); + pgpRxMasterMuxed : out AxiStreamMasterType; + pgpRxCtrl : in AxiStreamCtrlArray(3 downto 0); + -- AXI-Lite DRP interface + axilClk : in sl := '0'; + axilRst : in sl := '0'; + axilReadMaster : in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C; + axilReadSlave : out AxiLiteReadSlaveType; + axilWriteMaster : in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C; + axilWriteSlave : out AxiLiteWriteSlaveType); +end Pgp2fcGtyUltra; + +architecture mapping of Pgp2fcGtyUltra is + + signal resetGtSync : sl; + signal gtHardReset : sl; + + -- PgpRx Signals + signal resetRxSync : sl; + signal gtRxUserReset : sl; + signal phyRxLaneIn : Pgp2fcRxPhyLaneInType; + signal phyRxReady : sl; + signal phyRxInit : sl; + + -- PgpTx Signals + signal gtTxUserReset : sl; + signal phyTxLaneOut : Pgp2fcTxPhyLaneOutType; + signal phyTxReady : sl; + + signal phyRxInitSync : sl; + +begin + + pgpTxResetDone <= phyTxReady; + pgpRxResetDone <= phyRxReady; + + U_RstSync_1 : entity surf.PwrUpRst + generic map ( + TPD_G => TPD_G, + DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + port map ( + arst => pgpTxIn.resetGt, -- [in] + clk => stableClk, -- [in] + rstOut => resetGtSync); -- [out] + + gtHardReset <= resetGtSync or stableRst; + + U_RstSync_4 : entity surf.SynchronizerOneShot + generic map ( + TPD_G => TPD_G, + PULSE_WIDTH_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + port map ( + clk => stableClk, -- [in] + dataIn => phyRxInit, -- [in] + dataOut => phyRxInitSync); -- [out] + + -- Sync pgpRxIn.rxReset to stableClk and tie to gtRxUserReset + U_RstSync_2 : entity surf.PwrUpRst + generic map ( + TPD_G => TPD_G, + DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + port map ( + arst => pgpRxIn.resetRx, -- [in] + clk => stableClk, -- [in] + rstOut => resetRxSync); -- [out] + + gtRxUserReset <= phyRxInitSync or resetRxSync; + + U_RstSync_3 : entity surf.PwrUpRst + generic map ( + TPD_G => TPD_G, + DURATION_G => ite(SIMULATION_G, 12500, 125000000)) -- 100us in sim; 1s in silicon + port map ( + arst => pgpTxIn.resetTx, -- [in] + clk => stableClk, -- [in] + rstOut => gtTxUserReset); -- [out] + + U_Pgp2fcLane : entity surf.Pgp2fcLane + generic map ( + FC_WORDS_G => FC_WORDS_G, + VC_INTERLEAVE_G => VC_INTERLEAVE_G, + PAYLOAD_CNT_TOP_G => PAYLOAD_CNT_TOP_G, + NUM_VC_EN_G => NUM_VC_EN_G, + TX_ENABLE_G => TX_ENABLE_G, + RX_ENABLE_G => RX_ENABLE_G) + port map ( + pgpTxClk => pgpTxClk, + pgpTxClkRst => pgpTxReset, + pgpTxIn => pgpTxIn, + pgpTxOut => pgpTxOut, + pgpTxMasters => pgpTxMasters, + pgpTxSlaves => pgpTxSlaves, + phyTxLaneOut => phyTxLaneOut, + phyTxReady => phyTxReady, + pgpRxClk => pgpRxClk, + pgpRxClkRst => pgpRxReset, + pgpRxIn => pgpRxIn, + pgpRxOut => pgpRxOut, + pgpRxMasters => pgpRxMasters, + pgpRxMasterMuxed => pgpRxMasterMuxed, + pgpRxCtrl => pgpRxCtrl, + phyRxLaneIn => phyRxLaneIn, + phyRxReady => phyRxReady, + phyRxInit => phyRxInit); + + -------------------------- + -- Wrapper for GTY IP core + -------------------------- + PgpGtyCoreWrapper_1 : entity surf.Pgp2fcGtyCoreWrapper + generic map ( + TPD_G => TPD_G, + AXI_CLK_FREQ_G => AXI_CLK_FREQ_G, + AXI_BASE_ADDR_G => AXI_BASE_ADDR_G) + port map ( + stableClk => stableClk, + stableRst => gtHardReset, + gtRefClk => gtRefClk, + gtFabricRefClk => gtFabricRefClk, + gtUserRefClk => gtUserRefClk, + gtRxP => pgpGtRxP, + gtRxN => pgpGtRxN, + gtTxP => pgpGtTxP, + gtTxN => pgpGtTxN, + rxReset => gtRxUserReset, + rxUsrClkActive => pgpRxMmcmLocked, + rxResetDone => phyRxReady, + rxUsrClk => pgpRxClk, + rxData => phyRxLaneIn.data, + rxDataK => phyRxLaneIn.dataK, + rxDispErr => phyRxLaneIn.dispErr, + rxDecErr => phyRxLaneIn.decErr, + rxPolarity => RX_POLARITY_G, + rxOutClk => pgpRxOutClk, + rxRecClk => rxRecClk, + txReset => gtTxUserReset, + txUsrClk => pgpTxClk, + txUsrClkActive => pgpTxMmcmLocked, + txResetDone => phyTxReady, + txData => phyTxLaneOut.data, + txDataK => phyTxLaneOut.dataK, + txPolarity => TX_POLARITY_G, + txOutClk => pgpTxOutClk, + loopback => pgpRxIn.loopback, + axilClk => axilClk, + axilRst => axilRst, + axilReadMaster => axilReadMaster, + axilReadSlave => axilReadSlave, + axilWriteMaster => axilWriteMaster, + axilWriteSlave => axilWriteSlave); + +end mapping; diff --git a/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl b/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl new file mode 100644 index 0000000000..565e8facf8 --- /dev/null +++ b/protocols/pgp/pgp2fc/gtyUltraScale+/ruckus.tcl @@ -0,0 +1,14 @@ +# Load RUCKUS library +source $::env(RUCKUS_QUIET_FLAG) $::env(RUCKUS_PROC_TCL) + +# Load local source Code and constraints +if { $::env(VIVADO_VERSION) >= 2020.1 } { + + loadSource -lib surf -dir "$::DIR_PATH/rtl" + + loadSource -lib surf -path "$::DIR_PATH/ip/Pgp2fcGtyCore.dcp" + #loadIpCore -path "$::DIR_PATH/ip/Pgp2fcGtyCore.xci" + +} else { + puts "\n\nWARNING: $::DIR_PATH requires Vivado 2020.1 (or later)\n\n" +} diff --git a/protocols/pgp/pgp2fc/ruckus.tcl b/protocols/pgp/pgp2fc/ruckus.tcl index cce4e6d70f..ec2b8d8d31 100644 --- a/protocols/pgp/pgp2fc/ruckus.tcl +++ b/protocols/pgp/pgp2fc/ruckus.tcl @@ -4,3 +4,22 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl # Load the Core loadRuckusTcl "$::DIR_PATH/core" +# Get the family type +set family [getFpgaArch] + + +if { ${family} eq {artix7} } { + loadRuckusTcl "$::DIR_PATH/gtp7" +} + +if { ${family} eq {kintexuplus} || + ${family} eq {zynquplus} || + ${family} eq {zynquplusRFSOC} } { + # loadRuckusTcl "$::DIR_PATH/gthUltraScale+" + loadRuckusTcl "$::DIR_PATH/gtyUltraScale+" +} + +if { ${family} eq {virtexuplus} || + ${family} eq {virtexuplusHBM} } { + loadRuckusTcl "$::DIR_PATH/gtyUltraScale+" +} diff --git a/protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7.vhd b/protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7.vhd index b24447cc84..69c0c8d633 100644 --- a/protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7.vhd +++ b/protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7.vhd @@ -86,10 +86,10 @@ entity Pgp4Gtp7 is pgpClk : out sl; pgpClkRst : out sl; -- Non VC Rx Signals - pgpRxIn : in Pgp4RxInType; + pgpRxIn : in Pgp4RxInType := PGP4_RX_IN_INIT_C; pgpRxOut : out Pgp4RxOutType; -- Non VC Tx Signals - pgpTxIn : in Pgp4TxInType; + pgpTxIn : in Pgp4TxInType := PGP4_TX_IN_INIT_C; pgpTxOut : out Pgp4TxOutType; -- Frame Transmit Interface pgpTxMasters : in AxiStreamMasterArray(NUM_VC_G-1 downto 0); diff --git a/protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7Wrapper.vhd b/protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7Wrapper.vhd index dfa49e03a6..c5b8375388 100644 --- a/protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7Wrapper.vhd +++ b/protocols/pgp/pgp4/gtp7/rtl/Pgp4Gtp7Wrapper.vhd @@ -82,10 +82,10 @@ entity Pgp4Gtp7Wrapper is pgpClk : out slv(NUM_LANES_G-1 downto 0); pgpClkRst : out slv(NUM_LANES_G-1 downto 0); -- Non VC Rx Signals - pgpRxIn : in Pgp4RxInArray(NUM_LANES_G-1 downto 0); + pgpRxIn : in Pgp4RxInArray(NUM_LANES_G-1 downto 0) := (others => PGP4_RX_IN_INIT_C); pgpRxOut : out Pgp4RxOutArray(NUM_LANES_G-1 downto 0); -- Non VC Tx Signals - pgpTxIn : in Pgp4TxInArray(NUM_LANES_G-1 downto 0); + pgpTxIn : in Pgp4TxInArray(NUM_LANES_G-1 downto 0) := (others => PGP4_TX_IN_INIT_C); pgpTxOut : out Pgp4TxOutArray(NUM_LANES_G-1 downto 0); -- Frame Transmit Interface pgpTxMasters : in AxiStreamMasterArray((NUM_LANES_G*NUM_VC_G)-1 downto 0); diff --git a/python/surf/devices/analog_devices/_Ad9249.py b/python/surf/devices/analog_devices/_Ad9249.py index f497266b13..a25c07934c 100644 --- a/python/surf/devices/analog_devices/_Ad9249.py +++ b/python/surf/devices/analog_devices/_Ad9249.py @@ -421,6 +421,158 @@ def readBlocks(self, *, recurse=True, variable=None, checkEach=False, index=-1, for key,value in self.devices.items(): value.readBlocks(recurse=True, checkEach=checkEach, **kwargs) + +class Ad9249ReadoutGroup2(pr.Device): + def __init__(self, + name = 'Ad9249Readout', + description = 'Configure readout of 1 bank of an AD9249', + fpga = '7series', + channels = 8, + **kwargs): + + assert (channels > 0 and channels <= 8), f'channels ({channels}) must be between 0 and 8' + super().__init__(name=name, description=description, **kwargs) + + if fpga == '7series': + delayBits = 6 + elif fpga == 'ultrascale': + delayBits = 9 + else: + delayBits = 6 + + + self.add(pr.RemoteVariable( + name = 'Delay', + description = 'IDELAY value', + offset = 0x00, + bitSize = delayBits, + bitOffset = 0, + base = pr.UInt, + mode = 'RW', + verify = False, + groups = 'NoConfig', + )) + + self.add(pr.RemoteCommand( + name='Relock', + hidden=False, + offset=0x20, + bitSize=1, + bitOffset=0, + base=pr.UInt, + function=pr.RemoteCommand.toggle)) + + self.add(pr.RemoteVariable( + name = 'ErrorDetCount', + description = 'Number of times that frame lock has been lost since reset', + offset = 0x30, + disp = '{:d}', + bitSize = 16, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'LostLockCount', + description = 'Number of times that frame lock has been lost since reset', + offset = 0x50, + bitSize = 16, + bitOffset = 0, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'Locked', + description = 'Readout has locked on to the frame boundary', + offset = 0x50, + bitSize = 1, + bitOffset = 16, + base = pr.Bool, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'AdcFrameSync', + description = 'Last deserialized FCO value for debug', + offset = 0x58, + bitSize = 14, + base = pr.UInt, + mode = 'RO', + )) + + self.add(pr.RemoteVariable( + name = 'Invert', + description = 'Optional ADC data inversion (offset binary only)', + offset = 0x60, + bitSize = 1, + bitOffset = 0, + base = pr.Bool, + mode = 'RW', + )) + + for i in range(channels): + self.add(pr.RemoteVariable( + name = f'AdcChannel[{i:d}]', + description = f'Last deserialized channel {i:d} ADC value for debug', + offset = 0x80 + (i*4), + bitSize = 32, + bitOffset = 0, + base = pr.UInt, + disp = '{:09_x}', + mode = 'RO', + )) + + for i in range(channels): + self.add(pr.LinkVariable( + name = f'AdcVoltage[{i}]', + mode = 'RO', + disp = '{:1.9f}', + variable = self.AdcChannel[i], + linkedGet = lambda read, check, r=self.AdcChannel[i]: 2*pr.twosComplement(r.get(read=read, check=check)>>18, 14)/2**14, + units = 'V')) + + self.add(pr.RemoteCommand( + name = 'LostLockCountReset', + description = 'Reset LostLockCount', + function = pr.BaseCommand.toggle, + offset = 0x5C, + bitSize = 1, + bitOffset = 0, + )) + + self.add(pr.RemoteCommand( + name='FreezeDebug', + description='Freeze all of the AdcChannel registers', + hidden=True, + offset=0xA0, + bitSize=1, + bitOffset=0, + base=pr.UInt, + function=pr.RemoteCommand.touch)) + + def readBlocks(self, *, recurse=True, variable=None, checkEach=False, index=-1, **kwargs): + """ + Perform background reads + """ + checkEach = checkEach or self.forceCheckEach + + if variable is not None: + pr.startTransaction(variable._block, type=rim.Read, checkEach=checkEach, variable=variable, index=index, **kwargs) + + else: + self.FreezeDebug(1) + for block in self._blocks: + if block.bulkOpEn: + pr.startTransaction(block, type=rim.Read, checkEach=checkEach, **kwargs) + self.FreezeDebug(0) + + if recurse: + for key,value in self.devices.items(): + value.readBlocks(recurse=True, checkEach=checkEach, **kwargs) + + class AdcTester(pr.Device): def __init__(self, **kwargs): """Create AdcTester""" diff --git a/python/surf/protocols/pgp/_Pgp2fcAxi.py b/python/surf/protocols/pgp/_Pgp2fcAxi.py index 6d73e2783f..fb091aae2f 100644 --- a/python/surf/protocols/pgp/_Pgp2fcAxi.py +++ b/python/surf/protocols/pgp/_Pgp2fcAxi.py @@ -258,33 +258,33 @@ def __init__(self, pollInterval = 1 )) - self.add(pr.RemoteVariable( - name = "ProtocolErrorCount", - offset = 0xB0, - disp = '{:d}', - bitSize = errorCountBits, - bitOffset = 0, - mode = "RO", - base = pr.UInt, - pollInterval = 1 - )) - - self.add(pr.RemoteCommand( - name = 'AlignReset', - offset = 0xA0, - bitSize = 1, - bitOffset = 0, - function = pr.BaseCommand.toggle, - )) - - self.add(pr.RemoteVariable( - name = "AlignOverride", - offset = 0xA0, - bitSize = 1, - bitOffset = 1, - mode = "RW", - base = pr.Bool, - )) +# self.add(pr.RemoteVariable( +# name = "ProtocolErrorCount", +# offset = 0xB0, +# disp = '{:d}', +# bitSize = errorCountBits, +# bitOffset = 0, +# mode = "RO", +# base = pr.UInt, +# pollInterval = 1 +# )) + +# self.add(pr.RemoteCommand( +# name = 'AlignReset', +# offset = 0xA0, +# bitSize = 1, +# bitOffset = 0, +# function = pr.BaseCommand.toggle, +# )) + +# self.add(pr.RemoteVariable( +# name = "AlignOverride", +# offset = 0xA0, +# bitSize = 1, +# bitOffset = 1, +# mode = "RW", +# base = pr.Bool, +# )) # self.add(pr.RemoteVariable( # name = "AlignSlide", @@ -295,49 +295,49 @@ def __init__(self, # base = pr.Bool, # )) - self.add(pr.RemoteCommand( - name = 'AlignSlide', - offset = 0xA4, - bitSize = 1, - bitOffset = 0, - function = pr.BaseCommand.touchZero, - )) - - self.add(pr.RemoteVariable( - name = "Aligned", - offset = 0xA8, - bitSize = 1, - bitOffset = 0, - mode = "RO", - base = pr.Bool, - )) - - self.add(pr.RemoteVariable( - name = "AlignSlideDone", - offset = 0xA8, - bitSize = 1, - bitOffset = 1, - mode = "RO", - base = pr.Bool, - )) - - self.add(pr.RemoteVariable( - name = "AlignPhase", - offset = 0xA8, - bitSize = 1, - bitOffset = 2, - mode = "RO", - base = pr.UInt, - )) - - self.add(pr.RemoteVariable( - name = "AlignPhaseDone", - offset = 0xA8, - bitSize = 1, - bitOffset = 3, - mode = "RO", - base = pr.Bool, - )) +# self.add(pr.RemoteCommand( +# name = 'AlignSlide', +# offset = 0xA4, +# bitSize = 1, +# bitOffset = 0, +# function = pr.BaseCommand.touchZero, +# )) + +# self.add(pr.RemoteVariable( +# name = "Aligned", +# offset = 0xA8, +# bitSize = 1, +# bitOffset = 0, +# mode = "RO", +# base = pr.Bool, +# )) + +# self.add(pr.RemoteVariable( +# name = "AlignSlideDone", +# offset = 0xA8, +# bitSize = 1, +# bitOffset = 1, +# mode = "RO", +# base = pr.Bool, +# )) + +# self.add(pr.RemoteVariable( +# name = "AlignPhase", +# offset = 0xA8, +# bitSize = 1, +# bitOffset = 2, +# mode = "RO", +# base = pr.UInt, +# )) + +# self.add(pr.RemoteVariable( +# name = "AlignPhaseDone", +# offset = 0xA8, +# bitSize = 1, +# bitOffset = 3, +# mode = "RO", +# base = pr.Bool, +# )) # self.add(pr.RemoteVariable( # name = "AlignPhaseReq", @@ -348,13 +348,13 @@ def __init__(self, # base = pr.Bool, # )) - self.add(pr.RemoteCommand( - name = 'AlignPhaseReq', - offset = 0xAC, - bitSize = 1, - bitOffset = 0, - function = pr.BaseCommand.touchZero, - )) +# self.add(pr.RemoteCommand( +# name = 'AlignPhaseReq', +# offset = 0xAC, +# bitSize = 1, +# bitOffset = 0, +# function = pr.BaseCommand.touchZero, +# )) self.add(pr.RemoteCommand( name = 'CountReset', diff --git a/python/surf/xilinx/_AxiSysMonUltraScale.py b/python/surf/xilinx/_AxiSysMonUltraScale.py index c2de0bf748..f2371904fc 100644 --- a/python/surf/xilinx/_AxiSysMonUltraScale.py +++ b/python/surf/xilinx/_AxiSysMonUltraScale.py @@ -20,7 +20,9 @@ def __init__( **kwargs): super().__init__(description=description, **kwargs) - self.simpleViewList = simpleViewList + if simpleViewList is not None: + self.simpleViewList = simpleViewList[:] + self.simpleViewList.append('enable') def addPair(name, offset, bitSize, units, bitOffset, description, function, pollInterval=0): self.add(pr.RemoteVariable( @@ -528,8 +530,8 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll ) # Default to simple view - self.simpleView() - + if simpleViewList is not None: + self.simpleView() @staticmethod def convTempSYSMONE1(dev, var): @@ -568,9 +570,8 @@ def convAuxVoltage(var): return round(var.dependencies[0].value() * 244e-6,3) def simpleView(self): - if self.simpleViewList is not None: - # Hide all the variable - self.hideVariables(hidden=True) - # Then unhide the most interesting ones - vars = self.simpleViewList - self.hideVariables(hidden=False, variables=vars) + # Hide all the variable + self.hideVariables(hidden=True) + # Then unhide the most interesting ones + vars = self.simpleViewList + self.hideVariables(hidden=False, variables=vars) diff --git a/python/surf/xilinx/_GtRxAlignCheck.py b/python/surf/xilinx/_GtRxAlignCheck.py new file mode 100644 index 0000000000..63a13964b6 --- /dev/null +++ b/python/surf/xilinx/_GtRxAlignCheck.py @@ -0,0 +1,186 @@ +#----------------------------------------------------------------------------- +# Title : PyRogue Timing frame phase lock +#----------------------------------------------------------------------------- +# Description: +# PyRogue Timing frame phase lock +#----------------------------------------------------------------------------- +# This file is part of the 'LCLS Timing Core'. It is subject to +# the license terms in the LICENSE.txt file found in the top-level directory +# of this distribution and at: +# https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +# No part of the 'LCLS Timing Core', including this file, may be +# copied, modified, propagated, or distributed except according to the terms +# contained in the LICENSE.txt file. +#----------------------------------------------------------------------------- + +import pyrogue as pr + +class GtRxAlignCheck(pr.Device): + def __init__( self, + name = "GtRxAlignCheck", + description = "Timing frame phase lock", + **kwargs): + super().__init__(name=name, description=description, **kwargs) + + ############################## + # Variables + ############################## + + # self.addRemoteVariables( + # name = "PhaseCount", + # description = "Timing frame phase", + # offset = 0x00, + # bitSize = 16, + # bitOffset = 0, + # mode = "RO", + # pollInterval = 1, + # number = 128, + # stride = 2, + # hidden = True, + # ) + + self.addRemoteVariables( + name = "PhaseCount", + description = "Timing frame phase", + offset = 0x00, + bitSize = 32, + bitOffset = 0, + mode = "RO", + pollInterval = 1, + number = 64, + stride = 4, + hidden = True, + ) + + self.add(pr.RemoteVariable( + name = "PhaseTarget", + description = "Timing frame phase lock target", + offset = 0x100, + bitSize = 7, + bitOffset = 0, + mode = "RW", + )) + + self.add(pr.RemoteVariable( + name = "Mask", + description = "Register Mask Value", + offset = 0x100, + bitSize = 7, + bitOffset = 8, + mode = "RW", + )) + + self.add(pr.RemoteVariable( + name = "ResetLen", + description = "Reset length", + offset = 0x100, + bitSize = 4, + bitOffset = 16, + mode = "RW", + )) + + self.add(pr.RemoteVariable( + name = "LastPhase", + description = "Last timing frame phase seen", + offset = 0x104, + bitSize = 7, + bitOffset = 0, + mode = "RO", + pollInterval = 1, + )) + + self.add(pr.RemoteVariable( + name = "TxClkFreqRaw", + offset = 0x108, + bitSize = 32, + bitOffset = 0, + mode = 'RO', + hidden = True, + pollInterval = 1, + )) + + self.add(pr.LinkVariable( + name = "TxClkFreq", + units = "MHz", + mode = 'RO', + dependencies = [self.TxClkFreqRaw], + linkedGet = lambda: self.TxClkFreqRaw.value() * 1.0e-6, + disp = '{:0.3f}', + )) + + self.add(pr.RemoteVariable( + name = "RxClkFreqRaw", + offset = 0x10C, + bitSize = 32, + bitOffset = 0, + mode = 'RO', + hidden = True, + pollInterval = 1, + )) + + self.add(pr.LinkVariable( + name = "RxClkFreq", + units = "MHz", + mode = 'RO', + dependencies = [self.RxClkFreqRaw], + linkedGet = lambda: self.RxClkFreqRaw.value() * 1.0e-6, + disp = '{:0.3f}', + )) + + self.add(pr.RemoteVariable( + name = "Locked", + description = 'If True, align checker successfully aligned the transceiver', + offset = 0x110, + bitSize = 1, + bitOffset = 0, + mode = 'RO', + base = pr.Bool, + )) + + self.add(pr.RemoteVariable( + name = "Override", + description = 'If set to True, the Align Checker will stop resetting the transceiver, regardless of the phase read-out from the DRP interface', + offset = 0x114, + bitSize = 1, + bitOffset = 0, + mode = 'RW', + base = pr.Bool, + )) + + self.add(pr.RemoteCommand( + name = "RstRetryCnt", + description = 'Reset the Retry Counter back to zero', + offset = 0x118, + bitSize = 1, + bitOffset = 0, + function = pr.RemoteCommand.touchOne + )) + + self.add(pr.RemoteVariable( + name = "RetryCnt", + description = 'How many retries it took to align. Does not roll-over', + offset = 0x11C, + bitSize = 16, + bitOffset = 0, + mode = 'RO', + base = pr.UInt, + )) + + self.add(pr.RemoteVariable( + name = "RefClkFreqRaw", + offset = 0x120, + bitSize = 32, + bitOffset = 0, + mode = 'RO', + hidden = True, + pollInterval = 1, + )) + + self.add(pr.LinkVariable( + name = "RefClkFreq", + units = "MHz", + mode = 'RO', + dependencies = [self.RefClkFreqRaw], + linkedGet = lambda: self.RefClkFreqRaw.value() * 1.0e-6, + disp = '{:0.3f}', + )) diff --git a/python/surf/xilinx/_Xadc.py b/python/surf/xilinx/_Xadc.py index a53c99cefd..71bdd85dab 100644 --- a/python/surf/xilinx/_Xadc.py +++ b/python/surf/xilinx/_Xadc.py @@ -30,8 +30,9 @@ def __init__(self, if isinstance(auxChannels, int): auxChannels = list(range(auxChannels)) - self.simpleViewList = simpleViewList - self.simpleViewList.append('enable') + if simpleViewList is not None: + self.simpleViewList = simpleViewList[:] + self.simpleViewList.append('enable') def addPair(name, offset, bitSize, units, bitOffset, description, function, pollInterval=0): self.add(pr.RemoteVariable( @@ -572,8 +573,8 @@ def addPair(name, offset, bitSize, units, bitOffset, description, function, poll ) # Default to simple view - self.simpleView() - + if simpleViewList is not None: + self.simpleView() @staticmethod def convTemp(dev, var): diff --git a/python/surf/xilinx/__init__.py b/python/surf/xilinx/__init__.py index 785fc59e28..978aa9aaed 100644 --- a/python/surf/xilinx/__init__.py +++ b/python/surf/xilinx/__init__.py @@ -11,6 +11,7 @@ from surf.xilinx._AxiSysMonUltraScale import * from surf.xilinx._ClockManager import * from surf.xilinx._GpioPs import * +from surf.xilinx._GtRxAlignCheck import * from surf.xilinx._Gtye4Channel import * from surf.xilinx._Gtye4Common import * from surf.xilinx._Gthe3Channel import * diff --git a/xilinx/general/rtl/GtRxAlignCheck.vhd b/xilinx/general/rtl/GtRxAlignCheck.vhd new file mode 100644 index 0000000000..533e2f673a --- /dev/null +++ b/xilinx/general/rtl/GtRxAlignCheck.vhd @@ -0,0 +1,336 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: GTH RX Byte Alignment Checker module +------------------------------------------------------------------------------- +-- This file is part of 'LCLS Timing Core'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'LCLS Timing Core', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; + +entity GtRxAlignCheck is + generic ( + TPD_G : time := 1 ns; + GT_TYPE_G : string := "GTHE3"; -- or GTYE3, GTHE4, GTYE4 + AXI_CLK_FREQ_G : real := 125.0e6; + DRP_ADDR_G : slv(31 downto 0)); + port ( + -- Clock Monitoring + txClk : in sl; + rxClk : in sl; + refClk : in sl; + -- GTH Status/Control Interface + resetIn : in sl; + resetOut : out sl; + resetDone : in sl; + resetErr : in sl; + locked : out sl; + -- Clock and Reset + axilClk : in sl; + axilRst : in sl; + -- Master AXI-Lite Interface + mAxilReadMaster : out AxiLiteReadMasterType; + mAxilReadSlave : in AxiLiteReadSlaveType; + mAxilWriteMaster : out AxiLiteWriteMasterType; + mAxilWriteSlave : in AxiLiteWriteSlaveType; + -- Slave AXI-Lite Interface + sAxilReadMaster : in AxiLiteReadMasterType; + sAxilReadSlave : out AxiLiteReadSlaveType; + sAxilWriteMaster : in AxiLiteWriteMasterType; + sAxilWriteSlave : out AxiLiteWriteSlaveType); +end entity GtRxAlignCheck; + +architecture rtl of GtRxAlignCheck is + + ---------------------------------------------------------------------- + -- GTHE3 = x"0000_0540" (DRP_ADDR=0x150, see UG576 (v1.5) on page 508) + -- GTYE3 = x"0000_0940" (DRP_ADDR=0x250, see UG578 (v1.3) on page 396) + -- GTHE4 = x"0000_0940" (DRP_ADDR=0x250, see UG576 (v1.5) on page 421) + -- GTYE4 = x"0000_0940" (DRP_ADDR=0x250, see UG578 (v1.3) on page 443) + ---------------------------------------------------------------------- + constant COMMA_ALIGN_LATENCY_OFFSET_C : slv(31 downto 0) := ite((GT_TYPE_G = "GTHE3"), x"0000_0540", x"0000_0940"); + constant COMMA_ALIGN_LATENCY_ADDR_C : slv(31 downto 0) := (DRP_ADDR_G + COMMA_ALIGN_LATENCY_OFFSET_C); + + constant LOCK_VALUE_C : integer := 16; + constant MASK_VALUE_C : integer := 126; + + type StateType is ( + RESET_S, + READ_S, + ACK_S, + LOCKED_S); + + type RegType is record + locked : sl; + rst : sl; + rstRetryCnt : sl; + override : sl; + rstlen : slv(3 downto 0); + rstcnt : slv(3 downto 0); + retryCnt : slv(15 downto 0); + tgt : slv(6 downto 0); + mask : slv(6 downto 0); + last : slv(15 downto 0); + sample : Slv8Array(39 downto 0); + sAxilWriteSlave : AxiLiteWriteSlaveType; + sAxilReadSlave : AxiLiteReadSlaveType; + req : AxiLiteReqType; + state : StateType; + end record; + constant REG_INIT_C : RegType := ( + locked => '0', + rst => '1', + rstRetryCnt => '0', + override => '0', + rstlen => toSlv(3, 4), + rstcnt => toSlv(0, 4), + retryCnt => toSlv(0, 16), + tgt => toSlv(LOCK_VALUE_C, 7), + mask => toSlv(MASK_VALUE_C, 7), + last => toSlv(0, 16), + sample => (others => (others => '0')), + sAxilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C, + sAxilReadSlave => AXI_LITE_READ_SLAVE_INIT_C, + req => AXI_LITE_REQ_INIT_C, + state => READ_S); + + signal r : RegType := REG_INIT_C; + signal rin : RegType; + + signal ack : AxiLiteAckType; + + + signal txClkFreq : slv(31 downto 0); + signal rxClkFreq : slv(31 downto 0); + signal refClkFreq : slv(31 downto 0); + + -- attribute dont_touch : string; + -- attribute dont_touch of r : signal is "TRUE"; + -- attribute dont_touch of ack : signal is "TRUE"; + -- attribute dont_touch of txClkFreq : signal is "TRUE"; + -- attribute dont_touch of rxClkFreq : signal is "TRUE"; + +begin + + U_refClkFreq : entity surf.SyncClockFreq + generic map ( + TPD_G => TPD_G, + REF_CLK_FREQ_G => AXI_CLK_FREQ_G, -- Units of Hz + REFRESH_RATE_G => 1.0, -- Units of Hz + CNT_WIDTH_G => 32) -- Counters' width + port map ( + -- Frequency Measurement and Monitoring Outputs (locClk domain) + freqOut => refClkFreq, + -- Clocks + clkIn => refClk, + locClk => axilClk, + refClk => axilClk); + + U_txClkFreq : entity surf.SyncClockFreq + generic map ( + TPD_G => TPD_G, + REF_CLK_FREQ_G => AXI_CLK_FREQ_G, -- Units of Hz + REFRESH_RATE_G => 1.0, -- Units of Hz + CNT_WIDTH_G => 32) -- Counters' width + port map ( + -- Frequency Measurement and Monitoring Outputs (locClk domain) + freqOut => txClkFreq, + -- Clocks + clkIn => txClk, + locClk => axilClk, + refClk => axilClk); + + U_rxClkFreq : entity surf.SyncClockFreq + generic map ( + TPD_G => TPD_G, + REF_CLK_FREQ_G => AXI_CLK_FREQ_G, -- Units of Hz + REFRESH_RATE_G => 1.0, -- Units of Hz + CNT_WIDTH_G => 32) -- Counters' width + port map ( + -- Frequency Measurement and Monitoring Outputs (locClk domain) + freqOut => rxClkFreq, + -- Clocks + clkIn => rxClk, + locClk => axilClk, + refClk => axilClk); + + comb : process (ack, axilRst, r, resetDone, resetErr, resetIn, rxClkFreq, + sAxilReadMaster, sAxilWriteMaster, txClkFreq, refClkFreq) is + variable v : RegType; + variable axilEp : AxiLiteEndpointType; + variable i : natural; + begin + -- Latch the current value + v := r; + + -- Reset the flags + v.rst := '0'; + -- Reset the strobes + v.rstRetryCnt := '0'; + + ------------------------ + -- AXI-Lite Transactions + ------------------------ + + -- Determine the transaction type + axiSlaveWaitTxn(axilEp, sAxilWriteMaster, sAxilReadMaster, v.sAxilWriteSlave, v.sAxilReadSlave); + + for i in 0 to r.sample'length-1 loop + axiSlaveRegister(axilEp, toSlv(4*(i/4), 12), 8*(i mod 4), v.sample(i)); + end loop; + axiSlaveRegister (axilEp, x"100", 0, v.tgt); + axiSlaveRegister (axilEp, x"100", 8, v.mask); + axiSlaveRegister (axilEp, x"100", 16, v.rstlen); + axiSlaveRegister (axilEp, x"104", 0, v.last); + axiSlaveRegisterR(axilEp, x"108", 0, txClkFreq); + axiSlaveRegisterR(axilEp, x"10C", 0, rxClkFreq); + axiSlaveRegisterR(axilEp, x"110", 0, v.locked); + axiSlaveRegister (axilEp, x"114", 0, v.override); + axiSlaveRegister (axilEp, x"118", 0, v.rstRetryCnt); + axiSlaveRegisterR(axilEp, x"11C", 0, v.retryCnt); + axiSlaveRegisterR(axilEp, x"120", 0, refClkFreq); + + + -- Close out the transaction + axiSlaveDefault(axilEp, v.sAxilWriteSlave, v.sAxilReadSlave, AXI_RESP_OK_C); + + -- State Machine + case r.state is + ---------------------------------------------------------------------- + when RESET_S => + -- Set the flags + v.rst := '1'; + v.locked := '0'; + -- Check the counter + if (r.rstcnt = r.rstlen) then + -- Wait for the reset transition + if (resetDone = '0') then + -- Reset the counter + v.rstcnt := (others => '0'); + -- Next state + v.state := READ_S; + end if; + else + -- Increment the counter + v.rstcnt := r.rstcnt + 1; + end if; + ---------------------------------------------------------------------- + when READ_S => + -- Reset the flag + v.locked := '0'; + -- Wait for the reset transition and check state of master AXI-Lite + if (resetDone = '1') and (ack.done = '0') then + -- Start the master AXI-Lite transaction + v.req.request := '1'; + v.req.rnw := '1'; -- read operation + v.req.address := COMMA_ALIGN_LATENCY_ADDR_C; + -- Next state + v.state := ACK_S; + end if; + ---------------------------------------------------------------------- + when ACK_S => + -- AXI-Lite transaction handshaking + if (ack.done = '1') then + -- Reset the flag + v.req.request := '0'; + -- Get the index pointer + i := conv_integer(ack.rdData(6 downto 0)); + -- Increment the counter + v.sample(i) := r.sample(i) + 1; + -- Save the last byte alignment check + v.last := ack.rdData(15 downto 0); + -- Check the byte alignment + if ( (((ack.rdData(6 downto 0) xor r.tgt) and r.mask) = toSlv(0, 7)) + or v.override = '1') then + -- Next state + v.state := LOCKED_S; + else + -- Set the flag + v.rst := '1'; + -- Next state + v.state := RESET_S; + end if; + end if; + ---------------------------------------------------------------------- + when LOCKED_S => + -- Set the flag (can now be reset only by an external resetIn/resetErr) + v.locked := '1'; + ---------------------------------------------------------------------- + end case; + + -- Check for software controlled sampler reset + if (axilEp.axiStatus.writeEnable = '1') and (sAxilWriteMaster.awaddr(8 downto 0) = toSlv(256, 9)) then + v.sample := (others => (others => '0')); + end if; + + -- Check for user reset + if (resetIn = '1') or (resetErr = '1') then + -- Setup flags for reset state + v.rst := '1'; + v.req.request := '0'; + -- Reset the counter + v.rstcnt := (others => '0'); + -- Next state + v.state := RESET_S; + end if; + + -- Increment the reset retry counter (if triggered internally) + if (r.rstRetryCnt = '1') then + -- Reset clause first + v.retryCnt := (others => '0'); + elsif (v.rst = '1' and r.rst = '0' and resetIn = '0' and resetErr = '0') then + -- Edge-triggered + v.retryCnt := r.retryCnt + 1; + end if; + + -- Reset + if (axilRst = '1') then + v := REG_INIT_C; + end if; + + -- Register the variable for next clock cycle + rin <= v; + + -- Outputs + sAxilReadSlave <= r.sAxilReadSlave; + sAxilWriteSlave <= r.sAxilWriteSlave; + locked <= r.locked; + resetOut <= r.rst; + + end process comb; + + seq : process (axilClk) is + begin + if rising_edge(axilClk) then + r <= rin after TPD_G; + end if; + end process seq; + + U_AxiLiteMaster : entity surf.AxiLiteMaster + generic map ( + TPD_G => TPD_G) + port map ( + req => r.req, + ack => ack, + axilClk => axilClk, + axilRst => axilRst, + axilWriteMaster => mAxilWriteMaster, + axilWriteSlave => mAxilWriteSlave, + axilReadMaster => mAxilReadMaster, + axilReadSlave => mAxilReadSlave); + +end rtl; diff --git a/yaml/Pgp2bAxi.yaml b/yaml/Pgp2bAxi.yaml index 3d6cc02f13..4abc6f9180 100644 --- a/yaml/Pgp2bAxi.yaml +++ b/yaml/Pgp2bAxi.yaml @@ -97,6 +97,33 @@ Pgp2bAxi: &Pgp2bAxi mode: RW description: "Auto Status Send Enable (PPI)" ######################################################### + TxDiffCtrl: + at: + offset: 0x1C + class: IntField + sizeBits: 5 + lsBit: 0 + mode: RW + description: "GT Tx Diff Voltage Control" + ######################################################### + TxPreCursor: + at: + offset: 0x1C + class: IntField + sizeBits: 5 + lsBit: 5 + mode: RW + description: "GT Tx Pre Cursor Control" + ######################################################### + TxPostCursor: + at: + offset: 0x1D + class: IntField + sizeBits: 5 + lsBit: 2 + mode: RW + description: "GT Tx Pre Cursor Control" + ######################################################### RxPhyReady: at: offset: 0x20 diff --git a/yaml/SsiPrbsRx.yaml b/yaml/SsiPrbsRx.yaml index b0d2b46c66..9cadc9af86 100644 --- a/yaml/SsiPrbsRx.yaml +++ b/yaml/SsiPrbsRx.yaml @@ -57,13 +57,13 @@ SsiPrbsRx: &SsiPrbsRx mode: RO description: Number of word errors ######################################################### - BitStrbErrCnt: - at: - offset: 0x14 - class: IntField - name: BitStrbErrCnt - mode: RO - description: Number of bit errors +# BitStrbErrCnt: +# at: +# offset: 0x14 +# class: IntField +# name: BitStrbErrCnt +# mode: RO +# description: Number of bit errors ######################################################### RxFifoOverflowCnt: at: @@ -107,7 +107,7 @@ SsiPrbsRx: &SsiPrbsRx ######################################################### Status: at: - offset: 0x1C0 + offset: 0x70 class: IntField name: Status mode: RO @@ -115,7 +115,7 @@ SsiPrbsRx: &SsiPrbsRx ######################################################### PacketLength: at: - offset: 0x1C4 + offset: 0x74 class: IntField name: PacketLength mode: RO @@ -123,23 +123,23 @@ SsiPrbsRx: &SsiPrbsRx ######################################################### PacketRate: at: - offset: 0x1C8 + offset: 0x78 class: IntField name: PacketRate mode: RO description: '' ######################################################### - BitErrCnt: - at: - offset: 0x1CC - class: IntField - name: BitErrCnt - mode: RO - description: '' +# BitErrCnt: +# at: +# offset: 0x1CC +# class: IntField +# name: BitErrCnt +# mode: RO +# description: '' ######################################################### WordErrCnt: at: - offset: 0x1D0 + offset: 0x80 class: IntField name: WordErrCnt mode: RO @@ -147,7 +147,7 @@ SsiPrbsRx: &SsiPrbsRx ######################################################### RolloverEnable: at: - offset: 0x3C0 + offset: 0xF0 class: IntField name: RolloverEnable mode: RW @@ -155,7 +155,7 @@ SsiPrbsRx: &SsiPrbsRx ######################################################### CntRst: at: - offset: 0x3FC + offset: 0xFC class: IntField name: CntRst sizeBits: 1