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Merge remote-tracking branch 'origin/pre-release' into pgp-fc-rec
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@bengineerd
bengineerd committed Feb 15, 2024
2 parents 8aa8c2c + 0060ce2 commit 1dfbb6e
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2 changes: 1 addition & 1 deletion LICENSE.txt
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@@ -1,5 +1,5 @@

Copyright (c) 2023, The Board of Trustees of the Leland Stanford Junior
Copyright (c) 2024, The Board of Trustees of the Leland Stanford Junior
University, through SLAC National Accelerator Laboratory (subject to receipt
of any required approvals from the U.S. Dept. of Energy). All rights reserved.
Redistribution and use in source and binary forms, with or without
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32 changes: 14 additions & 18 deletions devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd
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Expand Up @@ -32,14 +32,14 @@ use surf.Ad9249Pkg.all;

entity Ad9249Deserializer is
generic (
TPD_G : time := 1 ns;
SIM_DEVICE_G : string := "ULTRASCALE";
IODELAY_GROUP_G : string := "DEFAULT_GROUP";
IDELAY_CASCADE_G : boolean := false;
IDELAYCTRL_FREQ_G : real := 300.0;
DEFAULT_DELAY_G : slv(8 downto 0) := (others => '0');
ADC_INVERT_CH_G : sl := '0';
BIT_REV_G : sl := '0');
TPD_G : time := 1 ns;
SIM_DEVICE_G : string := "ULTRASCALE";
IODELAY_GROUP_G : string := "DEFAULT_GROUP";
IDELAY_CASCADE_G : boolean := false;
IDELAYCTRL_FREQ_G : real := 300.0;
DEFAULT_DELAY_G : slv(8 downto 0) := (others => '0');
ADC_INVERT_CH_G : sl := '0';
BIT_REV_G : sl := '0');
port (
-- Serial Data from ADC
dClk : in sl; -- Data clock
Expand Down Expand Up @@ -207,13 +207,12 @@ begin
RST => dRstDiv4 -- 1-bit input: Asynchronous Reset
);



U_Gearbox : entity surf.Gearbox
generic map (
TPD_G => TPD_G,
SLAVE_WIDTH_G => 8,
MASTER_WIDTH_G => 14
TPD_G => TPD_G,
SLAVE_WIDTH_G => 8,
MASTER_WIDTH_G => 14,
MASTER_BIT_REVERSE_G => toBoolean(BIT_REV_G)
)
port map (
clk => dClkDiv4,
Expand All @@ -224,11 +223,8 @@ begin
slaveData => masterData,
-- Master Interface
masterValid => adcValid,
masterData => iAdcData,
masterReady => '1'
);

adcData <= iAdcData when BIT_REV_G = '0' else bitReverse(iAdcData(6 downto 0)) & bitReverse(iAdcData(13 downto 7));
masterData => adcData,
masterReady => '1');

end rtl;

170 changes: 85 additions & 85 deletions devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -45,36 +45,36 @@ entity Ad9249ReadoutGroup is
SIM_SPEEDUP_G : boolean := false);
port (
-- Master system clock, 125Mhz
axilClk : in sl;
axilRst : in sl;
axilClk : in sl;
axilRst : in sl;

-- Axi Interface
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType;
axilReadMaster : in AxiLiteReadMasterType;
axilReadSlave : out AxiLiteReadSlaveType;
axilWriteMaster : in AxiLiteWriteMasterType;
axilWriteSlave : out AxiLiteWriteSlaveType;
axilReadMaster : in AxiLiteReadMasterType;
axilReadSlave : out AxiLiteReadSlaveType;

-- Reset for adc deserializer (axilClk domain)
adcClkRst : in sl;
adcClkRst : in sl;

-- clocks must be provided with USE_MMCME_G = false
-- this option is necessary if there is many ADCs
-- one external MMCM should be instantiated to be used with all Ad9249ReadoutGroups
adcBitClkIn : in sl; -- 350.0 MHz
adcBitClkDiv4In : in sl; -- 87.5 MHz
adcBitRstIn : in sl;
adcBitRstDiv4In : in sl;
adcBitClkIn : in sl; -- 350.0 MHz
adcBitClkDiv4In : in sl; -- 87.5 MHz
adcBitRstIn : in sl;
adcBitRstDiv4In : in sl;

-- Serial Data from ADC
adcSerial : in Ad9249SerialGroupType;
adcSerial : in Ad9249SerialGroupType;

-- Deserialized ADC Data
adcStreamClk : in sl;
adcStreams : out AxiStreamMasterArray(NUM_CHANNELS_G-1 downto 0) :=
(others => axiStreamMasterInit((false, 2, 8, 0, TKEEP_NORMAL_C, 0, TUSER_NORMAL_C)));
adcStreamClk : in sl;
adcStreams : out AxiStreamMasterArray(NUM_CHANNELS_G-1 downto 0) :=
(others => axiStreamMasterInit((false, 2, 8, 0, TKEEP_NORMAL_C, 0, TUSER_NORMAL_C)));
-- optional ready to allow evenout samples readout in adcStreamClk
adcReady : in slv(NUM_CHANNELS_G-1 downto 0) := (others => '1')
);
adcReady : in slv(NUM_CHANNELS_G-1 downto 0) := (others => '1')
);
end Ad9249ReadoutGroup;

-- Define architecture
Expand Down Expand Up @@ -111,7 +111,7 @@ architecture rtl of Ad9249ReadoutGroup is
readoutDebug1 => (others => (others => '0')),
lockedCountRst => '0',
invert => '0'
);
);

signal lockedSync : sl;
signal lockedFallCount : slv(15 downto 0);
Expand All @@ -123,24 +123,24 @@ architecture rtl of Ad9249ReadoutGroup is
-- ADC Readout Clocked Registers
-------------------------------------------------------------------------------------------------
type AdcRegType is record
slip : sl;
count : slv(5 downto 0);
slip : sl;
count : slv(5 downto 0);
--loadDelay : sl;
--delayValue : slv(8 downto 0);
locked : sl;
fifoWrData : Slv16Array(NUM_CHANNELS_G-1 downto 0);
fifoWrDataEn : slv(NUM_CHANNELS_G-1 downto 0);
locked : sl;
fifoWrData : Slv16Array(NUM_CHANNELS_G-1 downto 0);
fifoWrDataEn : slv(NUM_CHANNELS_G-1 downto 0);
end record;

constant ADC_REG_INIT_C : AdcRegType := (
slip => '0',
count => (others => '0'),
slip => '0',
count => (others => '0'),
--loadDelay => '0',
--delayValue => (others => '0'),
locked => '0',
fifoWrData => (others => (others => '0')),
fifoWrDataEn => (others => '0')
);
locked => '0',
fifoWrData => (others => (others => '0')),
fifoWrDataEn => (others => '0')
);

signal adcR : AdcRegType := ADC_REG_INIT_C;
signal adcRin : AdcRegType;
Expand All @@ -157,9 +157,9 @@ architecture rtl of Ad9249ReadoutGroup is
signal adcBitRst : sl;
signal adcClkRstSync : sl;

signal adcFrame : slv(13 downto 0);
signal adcFrameSync : slv(13 downto 0);
signal adcData : Slv14Array(NUM_CHANNELS_G-1 downto 0);
signal adcFrame : slv(13 downto 0);
signal adcFrameSync : slv(13 downto 0);
signal adcData : Slv14Array(NUM_CHANNELS_G-1 downto 0);

signal curDelayFrame : slv(8 downto 0);
signal curDelayData : slv9Array(NUM_CHANNELS_G-1 downto 0);
Expand All @@ -173,7 +173,7 @@ architecture rtl of Ad9249ReadoutGroup is
signal frameDelay : slv(8 downto 0);
signal frameDelaySet : sl;

signal invertSync : sl;
signal invertSync : sl;

begin
-------------------------------------------------------------------------------------------------
Expand All @@ -198,7 +198,7 @@ begin
rdClk => axilClk,
rdRst => axilRst,
cntRst => axilR.lockedCountRst
);
);

Synchronizer_1 : entity surf.Synchronizer
generic map (
Expand Down Expand Up @@ -240,9 +240,9 @@ begin
begin
v := axilR;

v.dataDelaySet := (others => '0');
v.frameDelaySet := '0';
v.lockedCountRst := '0';
v.dataDelaySet := (others => '0');
v.frameDelaySet := '0';
v.lockedCountRst := '0';

-- Store last two samples read from ADC
for i in 0 to NUM_CHANNELS_G-1 loop
Expand Down Expand Up @@ -318,14 +318,14 @@ begin
G_MMCM : if USE_MMCME_G = true generate

AdcClk_I_Ibufds : IBUFDS
generic map (
DQS_BIAS => "FALSE"
)
port map (
I => adcSerial.dClkP,
IB => adcSerial.dClkN,
O => adcDclk
);
generic map (
DQS_BIAS => "FALSE"
)
port map (
I => adcSerial.dClkP,
IB => adcSerial.dClkN,
O => adcDclk
);

------------------------------------------
-- Generate clocks from ADC incoming clock
Expand All @@ -335,22 +335,22 @@ begin
-- clkOut(1) : 87.50 MHz adcBitClkDiv4 clock
U_iserdesClockGen : entity surf.ClockManagerUltraScale
generic map(
TPD_G => 1 ns,
TYPE_G => "MMCM", -- or "PLL"
INPUT_BUFG_G => true,
FB_BUFG_G => true,
RST_IN_POLARITY_G => '1', -- '0' for active low
NUM_CLOCKS_G => 2,
TPD_G => 1 ns,
TYPE_G => "MMCM", -- or "PLL"
INPUT_BUFG_G => true,
FB_BUFG_G => true,
RST_IN_POLARITY_G => '1', -- '0' for active low
NUM_CLOCKS_G => 2,
-- MMCM attributes
BANDWIDTH_G => "OPTIMIZED",
CLKIN_PERIOD_G => 2.85, -- Input period in ns );
DIVCLK_DIVIDE_G => 10,
CLKFBOUT_MULT_F_G => 20.0,
CLKFBOUT_MULT_G => 5,
CLKOUT0_DIVIDE_F_G => 1.0,
CLKOUT0_DIVIDE_G => 2,
CLKOUT1_DIVIDE_G => 8
)
BANDWIDTH_G => "OPTIMIZED",
CLKIN_PERIOD_G => 2.85, -- Input period in ns );
DIVCLK_DIVIDE_G => 10,
CLKFBOUT_MULT_F_G => 20.0,
CLKFBOUT_MULT_G => 5,
CLKOUT0_DIVIDE_F_G => 1.0,
CLKOUT0_DIVIDE_G => 2,
CLKOUT1_DIVIDE_G => 8
)
port map(
clkIn => adcDclk,
rstIn => '0',
Expand All @@ -359,16 +359,16 @@ begin
rstOut(0) => adcBitRst,
rstOut(1) => adcBitRstDiv4,
locked => open
);
);

end generate G_MMCM;

G_NO_MMCM : if USE_MMCME_G = false generate

adcBitClk <= adcBitClkIn;
adcBitClkDiv4 <= adcBitClkDiv4In;
adcBitRst <= adcBitRstIn;
adcBitRstDiv4 <= adcBitRstDiv4In;
adcBitClk <= adcBitClkIn;
adcBitClkDiv4 <= adcBitClkDiv4In;
adcBitRst <= adcBitRstIn;
adcBitRstDiv4 <= adcBitRstDiv4In;

end generate G_NO_MMCM;

Expand All @@ -386,7 +386,7 @@ begin
ADC_INVERT_CH_G => '1',
BIT_REV_G => '0')
port map (
dClk => adcBitClk, -- Data clock
dClk => adcBitClk, -- Data clock
dRst => adcBitRst,
dClkDiv4 => adcBitClkDiv4,
dRstDiv4 => adcBitRstDiv4,
Expand All @@ -398,7 +398,7 @@ begin
bitSlip => adcR.slip,
adcData => adcFrame,
adcValid => adcFrameValid
);
);

U_FrmDlyFifo : entity surf.SynchronizerFifo
generic map (
Expand Down Expand Up @@ -436,7 +436,7 @@ begin
ADC_INVERT_CH_G => ADC_INVERT_CH_G(i),
BIT_REV_G => '1')
port map (
dClk => adcBitClk, -- Data clock
dClk => adcBitClk, -- Data clock
dRst => adcBitRst,
dClkDiv4 => adcBitClkDiv4,
dRstDiv4 => adcBitRstDiv4,
Expand Down Expand Up @@ -481,7 +481,7 @@ begin
----------------------------------------------------------------------------------------------
-- Slip bits until correct alignment seen
----------------------------------------------------------------------------------------------
v.slip := '0';
v.slip := '0';
if (adcR.count = 0) then
if adcFrameValid = '1' then
if (adcFrame = FRAME_PATTERN_C) then
Expand Down Expand Up @@ -537,24 +537,24 @@ begin
end process adcSeq;

RstSync_1 : entity surf.RstSync
generic map (
TPD_G => TPD_G
)
port map (
clk => adcBitClkDiv4,
asyncRst => adcClkRst,
syncRst => adcClkRstSync
);
generic map (
TPD_G => TPD_G
)
port map (
clk => adcBitClkDiv4,
asyncRst => adcClkRst,
syncRst => adcClkRstSync
);

-- synchronize data cross-clocks
G_FIFO_SYNC : for i in NUM_CHANNELS_G-1 downto 0 generate


U_DataFifo : entity surf.SynchronizerFifo
generic map (
TPD_G => TPD_G,
DATA_WIDTH_G => 16,
ADDR_WIDTH_G => 4)
TPD_G => TPD_G,
DATA_WIDTH_G => 16,
ADDR_WIDTH_G => 4)
port map (
rst => adcBitRstDiv4,
wr_clk => adcBitClkDiv4,
Expand All @@ -564,17 +564,17 @@ begin
rd_en => fifoDataRdEn(i),
valid => fifoDataValid(i),
dout => adcStreams(i).tdata(15 downto 0)
);
);

fifoDataRdEn(i) <= adcReady(i) and fifoDataValid(i);
adcStreams(i).tDest <= toSlv(i, 8);
adcStreams(i).tValid <= fifoDataValid(i);

U_DataFifoDebug : entity surf.SynchronizerFifo
generic map (
TPD_G => TPD_G,
DATA_WIDTH_G => 16,
ADDR_WIDTH_G => 4)
TPD_G => TPD_G,
DATA_WIDTH_G => 16,
ADDR_WIDTH_G => 4)
port map (
rst => adcBitRstDiv4,
wr_clk => adcBitClkDiv4,
Expand All @@ -584,7 +584,7 @@ begin
rd_en => debugDataValid(i),
valid => debugDataValid(i),
dout => debugData(i)
);
);

end generate;

Expand Down
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