u-boot-sifive: reduce DDR speed to 1600MT/s

As a workaround for a DDR controller issue.

Signed-off-by: Thomas Perrot <[email protected]>

recipes-bsp/u-boot/files/riscv64/0006-riscv-sifive-fu740-reduce-DDR-speed-from-1866MT-s-to.patch

@@ -0,0 +1,27 @@
+From 45f9941ddc6346b38aa9eb7f033e1e169b63bdc7 Mon Sep 17 00:00:00 2001
+From: Thomas Perrot <[email protected]>
+Date: Fri, 8 Dec 2023 11:24:37 +0100
+Subject: [PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to
+ 1600MT/s
+
+Signed-off-by: Thomas Perrot <[email protected]>
+---
+ arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi
+index 706224b384d2..956237c3218e 100644
+--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
++++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
+@@ -77,7 +77,7 @@
+ 			       0x0 0x100b2000 0x0 0x2000
+ 			       0x0 0x100b8000 0x0 0x1000>;
+ 			clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
+-			clock-frequency = <933333324>;
++			clock-frequency = <800000004>;
+ 			bootph-pre-ram;
+ 		};
+ 	};
+-- 
+2.43.0
+

recipes-bsp/u-boot/u-boot-sifive_2023.10.bb

@@ -15,6 +15,7 @@ SRC_URI:append:riscv64 = " \
     file://0003-board-sifive-Set-LED-s-color-to-blue-before-jumping-.patch \
     file://0004-board-sifive-spl-Set-remote-thermal-of-TMP451-to-85-.patch \
     file://0005-riscv-dts-Add-few-PMU-events.patch \
+    file://0006-riscv-sifive-fu740-reduce-DDR-speed-from-1866MT-s-to.patch \
     "
 
 # Only add opensbi dependency if opensbi is in image deps