uart_testplan.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  name: "uart"
  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                     "uart_sec_cm_testplan.hjson"]
  testpoints: [
    {
      name: smoke
      desc: '''
            - UART smoke test with few bytes transmitted and received asynchronously and
              in parallel with scoreboard checks
            - TX and RX have 2 independent threads respectively.
              -  program one Tx item in register and wait for it to complete at uart interface,
                 before send another one
              - sequencally send one Rx byte, then immediately read from register and check it'''
      stage: V1
      tests: ["uart_smoke"]
    }
    {
      name: base_random_seq
      desc: '''
            - This is the basic sequence that is extended by most of random sequence.
            - TX and RX have 2 independent threads respectively.
              - TX: keep programming csr wdata with random delay when fifo isn't full
              - RX: 2 processes. One is to send item through uart interface when fifo isn't full
                and the other is to read csr rdata when fifo isn't empty'''
      stage: V2
      tests: ["uart_tx_rx"]
    }
    {
      name: parity
      desc: '''Send / receive bytes with parity and odd parity enabled randomly.'''
      stage: V2
      tests: ["uart_smoke", "uart_tx_rx"]
    }
    {
      name: parity_error
      desc: '''
            - Enable parity and randomly set even/odd parity
            - Inject parity error randomly on data sent from rx and ensure the interrupt is
              raised'''
      stage: V2
      tests: ["uart_rx_parity_err", "uart_intr"]
    }
    {
      name: watermark
      desc: '''
            - Program random tx/rx fifo watermark level and keep sending random tx/rx data
              to fifo.
            - As the number of pending data entries in the tx/rx fifo reaches the programmed
              watermark level (fifo size >= watermark level), ensure that the watermark interrupt
              is asserted
            - Ensure interrupt stays asserted until cleared as well as fifo level dropped.
              The tx/rx watermark interrupt is sticky'''
      stage: V2
      tests: ["uart_tx_rx", "uart_intr"]
    }
    {
      name: fifo_full
      desc: '''Send over 32 bytes of data but stop when fifo is full'''
      stage: V2
      tests: ["uart_fifo_full"]
    }
    {
      name: fifo_overflow
      desc: '''
            - Keep sending over 32 bytes of data over tx/rx fifo
            - Ensure excess data bytes are dropped and check overflow interrupt
            - This uart_fifo_overflow_vseq is extent from uart_fifo_full_vseq and override the
              constraint to be able to send data over fifo size'''
      stage: V2
      tests: ["uart_fifo_overflow"]
    }
    {
      name: fifo_reset
      desc: '''
            - Fill up the tx/rx fifo. After a random number of bytes shows up on fifo, reset
              the fifo and ensure that the remaining data bytes do not show up
            - this sequence is extent from uart_fifo_overflow_vseq, so it can also reset when fifo
              is at any level, including full or overflow'''
      stage: V2
      tests: ["uart_fifo_reset"]
    }
    {
      name: rx_frame_err
      desc: '''
            - Inject frame error in parity and non-parity cases by not setting stop bit = 1
            - Ensure the interrupt gets asserted'''
      stage: V2
      tests: ["uart_intr"]
    }
    {
      name: rx_break_err
      desc: '''
            - Program random number of break detection characters
            - create a frame error scenario and send random number of 0 bytes
            - If that random number exceeds the programmed break characters
            - Ensure that the break_err interrupt is asserted'''
      stage: V2
      tests: ["uart_intr"]
    }
    {
      name: rx_timeout
      desc: '''
            - Program timeout_ctrl register to randomize the timeout. Send random number of
              data over rx
            - Wait until it's about to timeout, then check timeout interrupt doesn't fire. Wait
              for timeout and check timeout interrupt fires
            - Wait until it's about to timeout, then use either read csr rdata or send RX item
              through uart interface to reset timeout timer in order to ensure timeout never
              fires'''
      stage: V2
      tests: ["uart_intr"]
    }
    {
      name: perf
      desc: '''Run fifo_full_vseq with very small delays'''
      stage: V2
      tests: ["uart_perf"]
    }
    {
      name: sys_loopback
      desc: '''
            - Enable system looback, then drive uart TX and data will be loopbacked through RX
            - After loopback is done, uart.RDATA will be equal to the data programmed to
              uart.WDATA'''
      stage: V2
      tests: ["uart_loopback"]
    }
    {
      name: line_loopback
      desc: '''
             - Enable line loopback and drive uart_rx with random data and random delay
             - Check uart_tx has same value as uart_rx. There is not synchronizer register between
               uart_rx and uart_tx during line loopback'''
      stage: V2
      tests: ["uart_loopback"]
    }
    {
      name: rx_noise_filter
      desc: '''
            - Use 16x fast clk to sample it, data on uart_rx need to be stable for 3 clocks,
              otherwise, data change won't be taken
            - Enable noise filter and drive many glitches. Each glitch doesn't lasts less than
              3 clocks
            - Ensure the noise will be filterred out and it doesn't affect next normal
              transaction'''
      stage: V2
      tests: ["uart_noise_filter"]
    }
    {
      name: rx_start_bit_filter
      desc: '''
            - Start bit should last for at least half baud clock, otherwise, it will be dropped
            - It's always enabled. Drive start bit for less than half cycle.
            - Ensure the start bit will be dropped'''
      stage: V2
      tests: ["uart_rx_start_bit_filter"]
    }
    {
      name: tx_overide
      desc: '''Enable override control and use register programming to drive uart output
            directly.'''
      stage: V2
      tests: ["uart_tx_ovrd"]
    }
    {
      name: rx_oversample
      desc: '''
            - Use 16x baud clock to sample uart rx
            - Drive uart rx with 16 bits value, using 16x baud clock
            - Read RX oversampled value and ensure it's same as driven value'''
      stage: V2
      tests: ["uart_rx_oversample"]
    }
    {
      name: long_b2b_transfer
      desc: '''
            - Reduce delay to fill TX fifo and read RX fifo to ensure back2back transfers
            - Use long back2back transfer to ensure clock difference won't be accumulated across transactions
            - Uart monitor checks the clock offset between sender and receiver is never over 1/4 of the period'''
      stage: V2
      tests: ["uart_long_xfer_wo_dly"]
    }
    {
      name: stress_all
      desc: '''
            - Combine above sequences in one test to run sequentially, except csr sequence and
              uart_rx_oversample_vseq (requires zero_delays)
            - Randomly add reset between each sequence'''
      stage: V2
      tests: ["uart_stress_all"]
    }
    {
      name: stress_all_with_reset
      desc: '''Have random reset in parallel with stress_all and tl_errors sequences'''
      stage: V2
      tests: ["uart_stress_all_with_rand_reset"]
    }
  ]

  covergroups: [
    {
      name: foo_cg
      desc: '''
            '''
    }
  ]
}