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cu_base_project_syn.prj
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cu_base_project_syn.prj
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#-- Synopsys, Inc.
#-- Project file /home/justin/iCECube/cu_base_project/cu_base_project_syn.prj
#project files
add_file -verilog -lib work "cu_base_project_source/cu_top.v"
add_file -verilog -lib work "cu_base_project_source/reset_conditioner.v"
add_file -constraint -lib work "cu_base_project_source/cu.sdc"
#implementation: "cu_base_project_Implmnt"
impl -add cu_base_project_Implmnt -type fpga
#implementation attributes
set_option -vlog_std v2001
set_option -project_relative_includes 1
#device options
set_option -technology SBTiCE40
set_option -part iCE40HX8K
set_option -package CB132
set_option -speed_grade
set_option -part_companion ""
#compilation/mapping options
# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0
# Silicon Blue iCE40
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 2
set_option -fixgeneratedclocks 0
# NFilter
set_option -popfeed 0
set_option -constprop 0
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_format "edif"
project -result_file ./cu_base_project_Implmnt/cu_base_project.edf
project -log_file "./cu_base_project_Implmnt/cu_base_project.srr"
impl -active cu_base_project_Implmnt
project -run synthesis -clean