moore.vcd

$date
  Mon Aug 31 21:00:08 2020
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module numeric_std $end
$upscope $end
$scope module moore_tb $end
$comment state is not handled $end
$comment next_state is not handled $end
$var reg 1 ! clk $end
$var reg 1 " reset $end
$var reg 1 # enable $end
$var reg 1 $ i $end
$var reg 2 % o[1:0] $end
$var reg 4 & s[3:0] $end
$scope module moore_test $end
$var reg 1 ' clk $end
$var reg 1 ( reset $end
$var reg 1 ) enable $end
$var reg 1 * i $end
$var reg 2 + o[1:0] $end
$var reg 4 , s[3:0] $end
$comment state is not handled $end
$comment next_state is not handled $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0!
0"
0#
1$
b00 %
b0000 &
0'
0(
0)
1*
b00 +
b0000 ,
#10
1!
1#
b10 %
b0001 &
1'
1)
b10 +
b0001 ,
#20
0!
0'
#30
1!
b00 %
b0100 &
1'
b00 +
b0100 ,
#40
0!
0'
#50
1!
0$
b01 %
b0101 &
1'
0*
b01 +
b0101 ,
#100
1$
1*
#150
0!
0'
#160
1!
1'
#170