Wrong codegen for simd_select_bitmask on big-endian targets #127205
Labels
A-codegen
Area: Code generation
A-LLVM
Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.
A-SIMD
Area: SIMD (Single Instruction Multiple Data)
C-bug
Category: This is a bug.
T-compiler
Relevant to the compiler team, which will review and decide on the PR/issue.
Given the testcase
on a big-endian target, this passes with optimizations but fails without. LLVM optimizations correctly implement the semantics of the IR this generates (so the resulting program is trivial), but without optimizations all the IR reaches the backend and somewhere in the LLVM machine backend, things go wrong.
See here for some analysis.
Cc @uweigand @nikic
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