diff --git a/Makefile b/Makefile index a1530991..639fe902 100755 --- a/Makefile +++ b/Makefile @@ -2,6 +2,7 @@ CC=$(RISCV)/bin/riscv64-unknown-elf-gcc DRAFT=riscv-debug-draft STABLE=riscv-debug-stable +FROZEN=riscv-debug-frozen RELEASE=riscv-debug-release NOTES=riscv-debug-workgroup-notes @@ -28,16 +29,17 @@ INCLUDES_TEX += jtagdtm.tex INCLUDES_TEX += implementations.tex INCLUDES_TEX += debugger_implementation.tex INCLUDES_TEX += riscv-debug-spec.tex -INCLUDES_TEX += future.tex FIGURES = fig/* -all: stable $(NOTES).pdf +all: frozen $(NOTES).pdf draft: $(DRAFT).pdf stable: $(STABLE).pdf +frozen: $(FROZEN).pdf + release: $(RELEASE).pdf %.pdf: %.tex $(REGISTERS_TEX) $(FIGURES) $(INCLUDES_TEX) vc.tex changelog.tex diff --git a/README.md b/README.md index e8081ac3..70ff2dd6 100755 --- a/README.md +++ b/README.md @@ -1,10 +1,10 @@ RISC-V Debug Specification ========================== -The current master branch is v1.0.0-stable. +The current master branch is v1.0.0-frozen. You may be looking for one of the following pre-built PDFs: -* [Latest stable](https://github.com/riscv/riscv-debug-spec/blob/master/riscv-debug-stable.pdf) +* [Latest frozen](https://github.com/riscv/riscv-debug-spec/blob/master/riscv-debug-frozen.pdf) * [Latest release](https://github.com/riscv/riscv-debug-spec/blob/release/riscv-debug-release.pdf) Build Instructions diff --git a/future.tex b/future.tex deleted file mode 100644 index 25b8dc76..00000000 --- a/future.tex +++ /dev/null @@ -1,40 +0,0 @@ -\chapter{Future Ideas} -\label{sec:future} - -\textbf{All items in this section are future ideas and should not be considered part of the specification.} - -Some future version of this spec may implement some of the following features. - -\begin{enumerate} - \item The spec defines several additions to the Device Tree which enable a - debugger to discover hart IDs and supported triggers for all the harts - in the system. - \item DTMs can function as general bus subordinates, so they would look like - regular RAM to bus managers. - \item Harts can be divided into groups. All the harts in the same group can - be halted/run/stepped simultaneously. When a hart hits a breakpoint, all - the other harts in the same group also halt within a few clock cycles. - \item DTMs are specified for protocols like USB, I2C, SPI, and SWD. - \item The debugger can communicate with the power manager to power cores up - or down, and to query their status. - \item Serial ports can raise an interrupt when a send/receive queue becomes full/empty. - \item The debug interrupt can be masked by running code. If the interrupt is - asserted, then deasserted, and then asserted again the debug interrupt - happens anyway. This mechanism can be used to e.g.\ read/write memory with - minimal interruption, making sure never to interrupt during a critical - piece of code. - \item The Debug Module can include a serial interface for re-using - the DTM interface as a generic communication interface. -\end{enumerate} - -\section{Serial Ports} - -The Debug Module may implement up to 8 serial ports. They support basic flow -control and full duplex data transfer between a component and the debugger, -essentially allowing the Debug Transport to be used to communicate -with a debug monitor running on a hart, or more generally emulate devices which -aren't present. All these uses require software support, and are not further specified here. -Only the DMI side of the Debug Module serial registers are defined in this -specification as the core side interface should look like a peripheral device. - -\input{serial.tex} diff --git a/preface.tex b/preface.tex index 30fbdd3f..d3935c77 100644 --- a/preface.tex +++ b/preface.tex @@ -1,4 +1,14 @@ \chapter{Preface} +\ifdefstring{\releasename}{Frozen}{ + {\bf + This specification is Frozen. + + Change is extremely unlikely. A high threshold will be used, and a change + will only occur because of some truly critical issue being identified during + the public review cycle. Any other desired or needed changes can be the + subject of a follow-on new extension.} +}{} + \ifdefstring{\releasename}{STABLE}{ {\bf This stable specification might change before being accepted as standard. We're trying to only make backwards-compatible changes, but diff --git a/riscv-debug-draft.tex b/riscv-debug-draft.tex index d63033a4..d6cf1573 100644 --- a/riscv-debug-draft.tex +++ b/riscv-debug-draft.tex @@ -1,4 +1,5 @@ \newif\ifrelease \releasefalse \newcommand{\releasename}{DRAFT} +\newcommand{\versionnum}{1.0\ifrelease\else-\releasename\fi} \input{riscv-debug-spec.tex} diff --git a/riscv-debug-stable.pdf b/riscv-debug-frozen.pdf similarity index 55% rename from riscv-debug-stable.pdf rename to riscv-debug-frozen.pdf index 7ff550c2..b111a1f5 100644 Binary files a/riscv-debug-stable.pdf and b/riscv-debug-frozen.pdf differ diff --git a/riscv-debug-frozen.tex b/riscv-debug-frozen.tex new file mode 100644 index 00000000..6211d111 --- /dev/null +++ b/riscv-debug-frozen.tex @@ -0,0 +1,5 @@ +\newif\ifrelease +\releasefalse +\newcommand{\releasename}{Frozen} +\newcommand{\versionnum}{1.0.0-rc1} +\input{riscv-debug-spec.tex} diff --git a/riscv-debug-release.tex b/riscv-debug-release.tex index cc9b512f..d99f7c90 100644 --- a/riscv-debug-release.tex +++ b/riscv-debug-release.tex @@ -1,3 +1,4 @@ \newif\ifrelease \releasetrue +\newcommand{\versionnum}{1.0\ifrelease\else-\releasename\fi} \input{riscv-debug-spec.tex} diff --git a/riscv-debug-spec.tex b/riscv-debug-spec.tex index 4ee9b431..dc926845 100755 --- a/riscv-debug-spec.tex +++ b/riscv-debug-spec.tex @@ -82,8 +82,6 @@ \input{vc.tex} -\newcommand{\versionnum}{1.0\ifrelease\else-\releasename\fi} - \begin{document} \title{RISC-V Debug Specification\\ @@ -92,7 +90,7 @@ } \author{Editors: \\ Paul Donahue \textless pdonahue@ventanamicro.com\textgreater, Ventana Micro Systems \\ -Tim Newsome \textless tim@sifive.com\textgreater, SiFive, Inc.} +Tim Newsome \textless tim@casualhacker.net\textgreater} \date{\GITAuthorDate} \maketitle @@ -132,11 +130,13 @@ \ifrelease \else +\ifdefstring{\releasename}{Frozen}{}{ \chapter{Change Log} \begin{versionhistory} \input{changelog.tex} \end{versionhistory} +} \fi \end{document} diff --git a/riscv-debug-stable.tex b/riscv-debug-stable.tex index ee4cbfd2..b38d394f 100644 --- a/riscv-debug-stable.tex +++ b/riscv-debug-stable.tex @@ -1,4 +1,5 @@ \newif\ifrelease \releasefalse \newcommand{\releasename}{STABLE} +\newcommand{\versionnum}{1.0\ifrelease\else-\releasename\fi} \input{riscv-debug-spec.tex} diff --git a/xml/serial.xml b/xml/serial.xml deleted file mode 100644 index 3a72ed62..00000000 --- a/xml/serial.xml +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - If \FdmiSercsSerialcount is 0, this register is not present. - - - Number of supported serial ports. - - - - Select which serial port is accessed by \RdmiSerrx and \RdmiSertx. - - - - - - - - - - - - - - - - - - - - - - - - 1 when the debugger-to-core queue for serial port 0 has - over or underflowed. This bit will remain set until it is reset by - writing 1 to this bit. - - - 1 when the core-to-debugger queue for serial port 0 is not empty. - - - 1 when the debugger-to-core queue for serial port 0 is full. - - - - - If \FdmiSercsSerialcount is 0, this register is not present. - - This register provides access to the write data queue of the serial port - selected by \FdmiSercsSerial in \RdmiSercs. - - If the {\tt error} bit is not set and the queue is not full, a write to this register - adds the written data to the core-to-debugger queue. - Otherwise the {\tt error} bit is set and the write returns error. - - A read to this register returns the last data written. - - - - - - If \FdmiSercsSerialcount is 0, this register is not present. - - This register provides access to the read data queues of the serial port - selected by \FdmiSercsSerial in \RdmiSercs. - - If the {\tt error} bit is not set and the queue is not empty, a read from this register reads the - oldest entry in the debugger-to-core queue, and removes that entry from the queue. - Otherwise the {\tt error} bit is set and the read returns error. - - - -